CN108418585B

CN108418585B - Successive approximation type analog-to-digital converter based on code value estimation

Info

Publication number: CN108418585B
Application number: CN201810258406.8A
Authority: CN
Inventors: 张勇; 李婷; 黄正波; 倪亚波; 付东兵
Original assignee: CETC 24 Research Institute
Current assignee: Chongqing Jixin Technology Co ltd
Priority date: 2018-03-27
Filing date: 2018-03-27
Publication date: 2021-09-07
Anticipated expiration: 2038-03-27
Also published as: CN108418585A

Abstract

The invention relates to a successive approximation type analog-to-digital converter based on code value estimation, and belongs to the field of semiconductor integrated circuits. The existing successive approximation type analog-to-digital converter needs to judge bit by bit from MSB to LSB, needs N +1 clock cycles for completing one conversion, can jump over the bit judgment cycle of a high-order capacitor by adopting the successive approximation type analog-to-digital converter based on the code value estimation technology, reduces the number of clock cycles needed by one conversion, greatly reduces power consumption and improves conversion speed. According to the invention, the digital code obtained in the next conversion cycle is roughly estimated through code value estimation, and the bit decision cycle of the high-order capacitor can be skipped, so that the purposes of improving the conversion speed and reducing the power consumption are achieved.

Description

Successive approximation type analog-to-digital converter based on code value estimation

Technical Field

The invention belongs to the field of semiconductor integrated circuits, and relates to a successive approximation type analog-to-digital converter based on code value estimation.

Background

A circuit structure of a conventional successive approximation type analog-to-digital converter (sar ADC) is shown in fig. 1, where an N-bit sar ADC includes N binary weighted capacitors, and during a sampling phase, a switch connected to an input signal Vip and Vin in a switch S1 is turned on, a switch S2 is turned on, an upper plate of the capacitor is connected to the input signal, a lower plate of the capacitor is connected to a common mode level, the sampling phase is switched after the sampling phase is completed, the switch connected to the input signal Vip and Vin in a switch S1 is turned off, a switch S2 is turned off, and the lower plate of the capacitor is floating.

Disclosure of Invention

In view of this, the present invention provides a successive approximation type analog-to-digital converter based on code value estimation, where the existing successive approximation type analog-to-digital converter needs to perform bit-by-bit decision from MSB to LSB, and needs N +1 clock cycles to complete one conversion, and a successive approximation type analog-to-digital converter based on a code value estimation technology can skip a bit decision cycle of a high-bit capacitor, reduce the number of clock cycles needed for one conversion, and roughly estimate a digital code obtained in a next conversion cycle, so that the bit decision cycle of the high-bit capacitor can be skipped, thereby increasing conversion speed and reducing power consumption of the converter.

In order to achieve the purpose, the invention provides the following technical scheme:

the successive approximation type analog-to-digital converter based on code value estimation meets the following conditions:

at lower input signal frequencies, the oversampling rate is higher, and if the digital code values D1, D2 at times T1 and T2 are known, the approximation of the digital code at time T3 is expressed, in the case of a first order approximation, as:

D3E＝2*D2-D1

according to the estimated value D3E, a judgment result of the high-order capacitor is obtained, the high-order capacitor is directly set according to D3E, so that the bit judgment of the high-order capacitor is skipped, the judgment time is shortened, the power consumption consumed by the high-order capacitor is reduced, and an error delta D exists between the estimated value D3E and a true value D3:

ΔD＝|D3-D3E|

the existence of the error deltad indicates that the low-bit capacitor needs to make a bit-by-bit decision, so that the estimated value gradually approaches the true value. If the input signal frequency is high and the oversampling rate is not high, if a first-order approximation is adopted, the error Δ D may be large, the number of high-order capacitors that can be skipped may be reduced, and at this time, a more accurate first-order slope approximation is used to obtain the estimated code value, if the digital code values D1, D2, and D3 at times T1, T2, and T3 are known, and under the condition of the first-order slope approximation, the approximation of the digital code at time T4 is expressed as:

D4E＝D1+3*(D3-D2)

and obtaining a judgment result of the high-order capacitor according to the estimated value D4E, and setting the high-order capacitor directly according to D4E, so that the bit judgment time of the high-order capacitor is skipped, and the power consumption consumed by the high-order capacitor is reduced.

The invention has the beneficial effects that: the successive approximation type analog-digital converter based on the code value estimation technology can skip the bit judgment period of a high-order capacitor, reduce the number of clock cycles required by one-time conversion, improve the conversion speed and reduce the power consumption of the converter.

Drawings

In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:

FIG. 1 is a conventional N-bit successive approximation ADC;

FIG. 2 illustrates the digital code estimation principle;

FIG. 3 is a successive approximation DAC based on code value estimation.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a conventional N-bit successive approximation ADC; many sar adc in the industry have a high oversampling rate, the input signal can be equivalent to a very slowly changing signal relative to the sampling period, and the digital code value of the next transition point can be roughly estimated from the digital codes of the previous cycles, the principle of which is shown in fig. 2, and the two cases are divided, where the oversampling rate is high when the frequency of the input signal is low, and if the digital code values D1 and D2 at the time T1 and T2 are known, in the case of the first order approximation, the approximation of the digital code at the time T3 is expressed as:

D3E＝2*D2-D1

ΔD＝|D3-D3E|

the existence of the error deltad indicates that the low-bit capacitor needs to make a bit-by-bit decision, so that the estimated value gradually approaches the true value. If the input signal frequency is high and the oversampling rate is not high, if a first-order approximation is adopted, the error Δ D may be large, the number of high-order capacitors that can be skipped may be reduced, at this time, a more accurate first-order slope approximation may be used to obtain the estimated code value, and it is necessary to know the digital code values D1, D2, and D3 at three times of T1, T2, and T3, where in the case of the first-order slope approximation, the approximation of the digital code at the time of T4 is expressed as:

D4E＝D1+3*(D3-D2)

As shown in fig. 3, compared with a conventional successive approximation type analog-to-digital converter, a capacitor array is divided into two parts, namely an MSB part and an LSB part, and accordingly, an approximation logic is also divided into two parts, namely an MSB setting logic and an LSB successive approximation logic, and certainly, the next digital code can be estimated only by obtaining an accurate value of a previous digital code, so that the complete working process is as follows:

firstly, ADC works at reduced speed, and accurate front-segment digital code is obtained by adopting approximation logic of traditional SAR ADC

The first step is that the slope of the code value is detected, the difference value of the code value before and after the code value is verified, and if the difference value is smaller, the code value in the next normal working process can be predicted by using a low-speed conversion result.

And thirdly, normally working, selecting a code value estimation algorithm according to the frequency characteristic of the signal, using first-order approximation when the oversampling rate is higher, adopting first-order slope approximation if the oversampling rate is higher, combining the obtained front-section digital codes, and skipping a bit decision period of a high-order capacitor by estimating the next digital codes, thereby improving the conversion speed and reducing the power consumption of the converter.

Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims

1. A successive approximation type analog-to-digital converter based on code value estimation is characterized in that: the analog-to-digital converter satisfies the following conditions:

D3E＝2*D2-D1

obtaining a judgment result of the high-order capacitor according to the estimated value D3E, setting the high-order capacitor directly according to D3E, skipping the bit judgment of the high-order capacitor, reducing the judgment time and simultaneously reducing the power consumption consumed by the high-order capacitor, wherein an error delta D exists between the estimated value D3E and the true value D3:

ΔD＝|D3-D3E|

the existence of the error delta D indicates that the low-order capacitor also needs to carry out bit-by-bit judgment, so that the estimated value is gradually close to the true value; if the input signal frequency is high and the oversampling rate is not high, if a first-order approximation is adopted, the error Δ D may be large, the number of high-order capacitors that can be skipped is reduced, a first-order slope approximation is adopted to obtain an estimated code value, and if the digital code values D1, D2 and D3 at the time points T1, T2 and T3 are known, and if the first-order slope approximation is adopted, the approximate value of the digital code at the time point T4 is expressed as:

D4E＝D1+3*(D3-D2)