CN108417522B - Circuit packaging method of three-layer board structure - Google Patents
Circuit packaging method of three-layer board structure Download PDFInfo
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- CN108417522B CN108417522B CN201810044883.4A CN201810044883A CN108417522B CN 108417522 B CN108417522 B CN 108417522B CN 201810044883 A CN201810044883 A CN 201810044883A CN 108417522 B CN108417522 B CN 108417522B
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- 238000000034 method Methods 0.000 title claims abstract description 94
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 86
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000005498 polishing Methods 0.000 claims abstract description 13
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 12
- 238000005520 cutting process Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 214
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000005476 soldering Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 230000005496 eutectics Effects 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000004080 punching Methods 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims 2
- 238000005219 brazing Methods 0.000 claims 1
- 238000003466 welding Methods 0.000 claims 1
- 238000009713 electroplating Methods 0.000 abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 7
- 239000010949 copper Substances 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 19
- 238000004519 manufacturing process Methods 0.000 description 16
- 239000000969 carrier Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000032798 delamination Effects 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 239000004831 Hot glue Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 210000003205 muscle Anatomy 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a circuit packaging method of a three-layer plate structure, which comprises the following steps: covering the connecting layer on the carrier plate; arranging a positioning mark on the connecting layer; arranging a carrier and a pin on the connecting layer according to the positioning identifier; mounting the chip on a carrier; bonding two ends of the lead with the chip and the lead respectively; plastically packaging the chip, the pins, the leads and the carrier; removing the connecting layer and the carrier plate; and polishing a first contact surface of the pin, wherein the first contact surface is the surface of the pin contacted with the connecting layer. The invention realizes a rapid circuit packaging method through a three-layer plate structure, pins and a carrier are supported by a carrier plate through a connecting layer, the layout of the pins and the carrier is flexible, and the multi-circle or array layout of the pins can be realized; meanwhile, the design of the structure without connecting ribs can not form higher residual stress due to the cutting of the copper connecting ribs; and when the connecting layer and the carrier plate are removed by heat, a part of the tin or tin alloy connecting layer can be naturally reserved to wrap the pins and the carrier, so that the solderability of the product is improved, and subsequent electroplating treatment is not needed.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a circuit packaging method with a three-layer plate structure.
Background
At present, in the related art, the traditional package is limited by a lead frame structure and a production process, each package needs to use a special lead frame, and each special lead frame needs to be manufactured by a special die of a lead frame supplier, so that the production period is long and the cost is high; the pins and the carrier are supported by connecting ribs, so that flexible layout is difficult to realize; meanwhile, due to the existence of the connecting rib structure, when a cutting process is carried out after plastic package is finished, the copper connecting rib is easy to form high residual stress during cutting; in addition, the pins need to be plated with tin by an electroplating process after the existing products are packaged and molded so as to improve the weldability, however, the electroplating process has great pollution to the environment and is not beneficial to environmental protection.
Disclosure of Invention
The present invention has been made to solve the above-mentioned problems occurring in the prior art or the related art.
Therefore, the invention provides a circuit packaging method with a three-layer plate structure.
The invention provides a circuit packaging method of a three-layer plate structure, which comprises the following steps: covering the connecting layer on the carrier plate; arranging a positioning mark on the connecting layer; arranging a carrier and a pin on the connecting layer according to the positioning identifier; mounting the chip on a carrier; bonding two ends of the lead with the chip and the lead respectively; plastically packaging the chip, the pins, the leads and the carrier; removing the connecting layer and the carrier plate; and polishing a first contact surface of the pin, wherein the first contact surface is the surface of the pin contacted with the connecting layer.
In the technical scheme, the pins and the carrier are supported by the carrier plate and the connecting layer of the three-layer plate structure, a copper connecting rib structure is not needed, and a special lead frame is not needed to be opened, so that the production period is shortened, and the production cost is reduced; the structure characteristic of no connecting rib ensures that the layout of the pin and the carrier is not limited by the connecting rib any more, and the layout is free and flexible; and when the cutting process is carried out after the plastic package is finished, higher residual stress cannot be formed due to the cutting of the copper connecting ribs, so that the packaging yield and the reliability of the product are improved; meanwhile, as the part of the tin/tin alloy connecting layer is still remained on the pin and the carrier after the tin/tin alloy connecting layer is thermally removed, electroplating treatment is not needed, the production procedures are reduced, the production cost is reduced, and the environment is protected.
In addition, the method for packaging a circuit with a three-layer board structure in the technical scheme provided by the invention can also have the following additional technical characteristics:
in the above technical solution, preferably, the step of setting the carrier and the pin on the connection layer according to the positioning identifier specifically includes: arranging a metal layer on the connecting layer; the metal layer is etched according to the positioning marks to form the carrier and the pins.
In the technical scheme, the metal layer arranged in the three-layer plate structure is etched through an etching process to form the carrier and the pins, the support of the pins and the carrier is improved by the carrier plate and the connecting layer, the carrier and the pins are arranged without connecting ribs, and the pins and the carrier are freely and flexibly arranged.
In any of the above technical solutions, preferably, the step of setting the carrier and the pins on the connection layer according to the positioning identifier specifically includes: cutting, etching or punching the metal plate to form pins and carriers of preset shapes; and installing the pins and the carrier on the connecting layer according to the positioning marks.
In the technical scheme, a metal plate is cut, etched or punched in advance, pins and carriers are manufactured and formed according to a preset shape, and the pins and the carriers are installed on a connecting layer according to positioning marks; the pin and carrier rib-free layout is also realized.
In any of the above technical solutions, preferably, the connection layer is a tin alloy layer, a tin layer, or a glue layer.
In the technical scheme, the connecting layer is a tin alloy layer, a tin layer or an adhesive layer, when the bonding layer is the tin layer or the tin alloy layer, after heat removal, a part of the tin/tin alloy layer can still be naturally reserved on the pin and the carrier, so that the weldability of the pin and the carrier is improved, the pin does not need to be subjected to electroplating treatment, the production procedures are reduced, the production cost is reduced, and the environment is protected.
In any of the above technical solutions, preferably, the carrier and the pins are disposed on the connection layer according to the positioning identifier, and the chip is mounted on the carrier, and the method for packaging a circuit with a three-layer board structure further includes: and silver plating, nickel-palladium-gold plating or gold plating is carried out on the surfaces of the pin and the carrier.
According to the technical scheme, the surfaces of the pin and the carrier are plated with silver, nickel, palladium and gold or gold, so that the oxidation resistance of the pin and the carrier is improved, the bonding strength of the pin and the carrier with the plastic package material is enhanced, and the bonding performance of the lead, the bonding performance of the chip and the bonding strength of the chip with the plastic package material are improved.
In any of the above technical solutions, preferably, the mounting the chip on the carrier specifically includes: bonding the chip and the carrier through film bonding; or soldering or eutectic soldering the chip and the carrier.
In the technical scheme, the chip is mounted on the carrier by using a method of bonding the adhesive sheet with the adhesive, and the mounting operation method is simple and mature; and the chip is arranged on the carrier by using a soldering or eutectic soldering method, so that the chip is more firmly and reliably arranged, the heat conductivity between the chip and the carrier can be improved, and the heat radiation performance is improved.
In any of the above technical solutions, preferably, the removing the connection layer and the carrier plate specifically includes: heating the connecting layer and the carrier plate; and/or ultraviolet irradiating the connecting layer and the carrier plate; and/or grinding the connecting layer and the carrier plate.
In the technical scheme, the method for removing the connecting layer and the carrier plate comprises the steps of heating the connecting layer and the carrier plate after the device is subjected to plastic packaging, wherein when the connecting layer is a hot melt adhesive layer or a tin alloy or tin layer, the connecting layer can be melted and lose viscosity by heating to a lower temperature, and the carrier plate and the connecting layer can be easily taken down; the method of irradiating the connecting layer and the carrier plate by ultraviolet rays can also be used for removing the viscosity of the adhesive layer of the connecting layer; meanwhile, the connecting layer and the carrier plate can be physically removed by a method of grinding the connecting layer and the carrier plate, so that the process is simpler and the requirement on an operator is lower.
In any of the above technical solutions, preferably, the connection layer is provided with a positioning mark, and the three-layer board structure circuit packaging method further includes: mounting a bonding pad on the connection layer; mounting a passive device on the pad; and bonding two ends of the lead with the bonding pad and the lead respectively and/or bonding the two ends of the lead with the bonding pad and the carrier respectively.
In the technical scheme, the integrated packaging of the passive device is realized by adding the bonding pads, and the packaging density is increased.
In any of the above technical solutions, preferably, the cross sections of the pins and the carrier are in an inverted trapezoid shape or an inverted "convex" shape, that is, the area of one surface of the pins and the carrier away from the carrier is larger than the area of one surface of the pins and the carrier close to the carrier.
In the technical scheme, the pin and the carrier are in an inverted trapezoid or inverted 'convex' shape in section, so that the bonding strength of the pin, the carrier and the plastic package body can be improved, delamination is prevented, and the packaging reliability is improved.
In any of the above technical solutions, preferably, the pins are distributed on two sides of the chip; or the pins are distributed around the chip; or the pins are arranged on the connecting layer in an array manner.
In the technical scheme, the pins are distributed on two sides or the periphery of the chip or are arrayed on the connecting layer, and the distribution positions of the pins are adjusted according to the use scene, so that the packaging requirements of various types can be met.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow chart of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 2 is a flow chart of a circuit packaging method with a three-layer structure according to another embodiment of the present invention;
FIG. 3 is a flow chart of a circuit packaging method with a three-layer structure according to another embodiment of the present invention;
FIG. 4 is a flow chart of a circuit packaging method with a three-layer structure according to another embodiment of the present invention;
FIG. 5 is a flow chart of a circuit packaging method with a three-layer structure according to another embodiment of the present invention;
FIG. 6 is a flow chart of a circuit packaging method with a three-layer structure according to another embodiment of the present invention;
FIG. 7 is a flowchart of a circuit packaging method with a three-layer structure according to another embodiment of the present invention;
FIG. 8 is a flowchart of a circuit packaging method with a three-layer structure according to another embodiment of the present invention;
FIG. 9 is a flowchart of a circuit packaging method with a three-layer structure according to another embodiment of the present invention;
FIG. 10 is a flowchart of a circuit packaging method with a three-layer structure according to another embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating steps of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 12 is a schematic view illustrating another step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 13 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 14 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 15 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 16 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 17 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 18 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 19 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 20 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 21 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 22 is a schematic view of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 23 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 24 is a schematic view of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 25 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 26 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 27 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 28 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 29 is a schematic view of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 30 is a schematic view of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 31 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 32 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 33 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 34 is a schematic view of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 35 is a schematic view of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 36 is a schematic view of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
FIG. 37 is a schematic diagram illustrating a further step of a circuit packaging method with a three-layer structure according to an embodiment of the present invention;
wherein, the correspondence between the reference numbers and the part names in fig. 11 to 37 is:
the chip comprises a carrier plate 1, a connecting layer 2, a metal layer 3, a pin 31, a carrier 32, a chip 4, a lead 5, a bonding pad 6 and a passive device 7.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.
A three-board structure circuit packaging method according to some embodiments of the present invention is described below with reference to fig. 1 to 37.
In one embodiment of the present invention, as shown in fig. 1, the present invention provides a three-layer board structure circuit packaging method, including: s101, covering a connecting layer on a carrier plate; s102, setting a positioning mark on the connecting layer; s103, arranging a carrier and a pin on the connecting layer according to the positioning identifier; s104, mounting the chip on a carrier; s105, bonding two ends of the lead with the chip and the pin respectively; s106, plastically packaging the chip, the pin, the lead and the carrier; s107, removing the connecting layer and the carrier plate; and S108, polishing the first contact surface of the pin, wherein the first contact surface is the surface of the pin, which is in contact with the connecting layer.
In this embodiment, a positioning mark is arranged on the connection layer 2, the connection layer 2 is covered on the carrier plate 1, the carrier 32 and the leads 31 are arranged on the connection layer 2 according to the positioning mark, and after the chip 4 is mounted on the carrier 32, the chip 4 and the leads 31 are bonded through the leads 5 without using a special lead frame, so that the production period is shortened and the production cost is reduced; support plate 1 is connected with carrier 32 through articulamentum 2, get rid of support plate 1 and articulamentum 2 after accomplishing the encapsulation, thereby make pin 31 and carrier 32 need not link the muscle to support when the encapsulation, when cutting process after the plastic envelope is accomplished, can not form higher residual stress because the cutting of copper links the muscle easily, make the encapsulation device damage, the yields of product production has been improved, and because articulamentum 2 can improve the solderability of device after the encapsulation, need not to do electroplating process to pin 31 again, reduce production processes, the environmental protection when lowering production cost.
The carrier plate 1 may be made of metal, silicon wafer, glass, ceramic or other organic materials, and may be in a strip shape or a circular shape according to process requirements, so as to provide support for the pins 31 and the carrier 32, the pins 31 may be set to be in a rectangular shape, a circular shape or any other shape according to actual requirements, and may be arranged in a circle, multiple circles or in an area array manner along the periphery of the carrier plate 1, and one or more carriers 32 may be provided. The carrier 32 and the leads 31 are preferably inverted trapezoidal in cross section, which can increase the bonding strength between the carrier 32 and the leads 31 and the plastic package body and prevent delamination. The bonding process of bonding the lead 5 with the chip 4 and the lead 31 can select gold wire bonding, copper wire bonding, alloy wire bonding, aluminum wire bonding or aluminum tape bonding as required.
In an embodiment of the present invention, preferably, as shown in fig. 2, the circuit packaging method with a three-layer board structure includes: s201, as shown in fig. 11 and 12, covering the carrier board 1 with the connection layer 2; s202, setting a positioning mark on the connection layer; s203, as shown in fig. 13, providing a metal layer 3 on the connection layer 2; s204, as shown in FIG. 14, etching the metal layer 3 according to the positioning marks to form the carrier 32 and the pins 31; s205, as shown in fig. 15, mounting the chip 4 on the carrier 32; s206, as shown in fig. 16, bonding the two ends of the lead 5 with the chip 4 and the lead 31, respectively; s207, as shown in fig. 17, the plastic package chip, the pins 31, the leads 5, and the carrier 32; s208, as shown in fig. 18, removing the connection layer 2 and the carrier board 1; s209, as shown in fig. 19, the first contact surface of the lead 31 is polished, and the first contact surface is a surface of the lead contacting the connection layer.
In this embodiment, the pins 31 and the carrier 32 (shown in fig. 14) are formed by etching a three-layer board structure (shown in fig. 13), the pins 31 and the carrier 32 are supported by the connection layer 2, copper tie bars are not required for supporting, the layout is flexible and free, and a special lead frame is not required, so that the production period is shortened, and the production cost is reduced; after the packaging is finished, the carrier plate 1 and the connecting layer 2 are removed, and when a cutting and separating process is carried out, high residual stress can not be easily formed due to copper connecting rib cutting, so that the packaged device is damaged, and the yield of product production is improved.
The carrier 32 and the leads 31 can be rectangular, circular or in any shape, the cross section of the carrier is preferably in an inverted trapezoid shape or an inverted convex shape, so that the bonding strength between the carrier 32 and the leads 31 and the plastic package body can be increased, and delamination is prevented; the number of the carriers 32 may be one or more, or the carriers 32 may not be provided, according to actual needs.
In an embodiment of the present invention, preferably, as shown in fig. 3, the circuit packaging method with a three-layer board structure includes: s301, as shown in fig. 11 and 12, covering the carrier board 1 with the connection layer 2; s302, setting a positioning mark on the connection layer; s303, cutting, etching or punching the metal plate to form pins and carriers with preset shapes; s304, as shown in fig. 20, the pin 31 is mounted on the connection layer 2 according to the positioning identifier; s305, as shown in fig. 21, mounting the carrier 32 on the connection layer 2 according to the positioning mark; s306, as shown in fig. 22, mounting the chip 4 on the carrier 32; s307, as shown in fig. 23, bonding the two ends of the lead 31 with the chip 4 and the lead 31, respectively; s308, as shown in fig. 24, the plastic package chip 4, the pins 31, the leads 5, and the carrier 32; s309, as shown in fig. 25, removing the connection layer 2 and the carrier board 1; and S310, polishing a first contact surface of the pin, wherein the first contact surface is the surface of the pin, which is in contact with the connecting layer.
In the technical scheme, a metal plate is cut or etched or punched in advance, the pins 31 and the carriers 32 are manufactured and formed according to a preset shape, and the pins 31 and the carriers 32 are installed on the connecting layer 2 according to the positioning marks, a series of pins 31 and carriers 32 with uniform standards are manufactured and formed in advance in the scheme, and the pins 31 and the carriers 32 are installed on site by directly using equipment such as a soldering machine or a die bonder and the like during packaging, so that a special lead frame is not required to be developed, and the product can be packaged quickly; the free layout of the pins 31 and the carrier 32 without connecting ribs is realized; after the carrier plate 1 and the connecting layer 2 are removed by heating, a part of the tin layer can be naturally reserved on the pins 31 and the carrier 32, so that the solderability is improved, electroplating is not needed, and the environmental protection is facilitated.
In an embodiment of the present invention, preferably, as shown in fig. 4, the circuit packaging method with a three-layer board structure includes: s401, covering a connecting layer on a carrier plate; s402, setting a positioning mark on the connection layer; s403, arranging a carrier and a pin on the connection layer according to the positioning identifier; s404, silver plating is carried out on the surfaces of the pins and the carrier; s405, mounting the chip on a carrier; s406, bonding two ends of the lead with the chip and the lead respectively; s407, plastic packaging the chip, the pins, the leads and the carrier; s408, removing the connecting layer and the carrier plate; and S409, polishing the first contact surface of the pin, wherein the first contact surface is the surface of the pin contacted with the connecting layer.
In this embodiment, silver is plated on the surfaces of the lead 31 and the carrier 32 to improve the oxidation resistance of the lead 31 and the carrier 32, improve the solderability, and improve the bonding strength with the plastic package.
In an embodiment of the present invention, preferably, as shown in fig. 5, the circuit packaging method with a three-layer board structure includes: s501, as shown in fig. 11 and 12, covering the carrier board 1 with the connection layer 2; s502, setting a positioning mark on the connecting layer; s503, as shown in fig. 26, setting the pins 31 on the connection layer 2 according to the positioning identifier; s504, as shown in fig. 27, directly mounting the chip 4 on the connection layer 2; s505, as shown in fig. 28, bonding the two ends of the lead 5 to the chip 4 and the lead 31, respectively; s506, as shown in fig. 29, the plastic package chip 4, the pins 31, the leads 5, and the carrier 32; s507, as shown in fig. 30, removing the connection layer 2 and the carrier board 1; and S508, polishing a first contact surface of the pin, wherein the first contact surface is the surface of the pin, which is in contact with the connecting layer.
In this embodiment, the chip 4 is directly mounted on the connection layer 2, the carrier 32 structure is omitted, the packaging structure design is simpler, and a thinner packaging appearance can be realized. Preferably, the mounting method of the chip 4 on the connection layer can be selected from bonding paste, soldering or eutectic soldering according to actual conditions.
In addition, as shown in fig. 6, the method for packaging a circuit with a three-layer board structure includes: s601, covering the connecting layer on the carrier plate; s602, setting a positioning mark on the connection layer; s603, arranging a carrier and a pin on the connecting layer according to the positioning identifier; s604, soldering the chip and the carrier; s605, bonding two ends of the lead with the chip and the pin respectively; s606, plastically packaging the chip, the pins, the leads and the carrier; s607, removing the connecting layer and the carrier plate; and S608, polishing a first contact surface of the pin, wherein the first contact surface is a surface of the pin, which is in contact with the connecting layer.
The chip 4 is mounted on the carrier 32 by soldering, so that the chip 4 is more firmly and reliably mounted, the heat conductivity between the chip 4 and the carrier can be improved, and the heat dissipation performance can be improved. The soldering process may be an electroplating process, a chemical plating process, a coating heating process, or other processes.
In an embodiment of the present invention, preferably, as shown in fig. 7, the circuit packaging method with a three-layer board structure includes: s701, covering a connecting layer on a carrier plate; s702, setting a positioning mark on the connection layer; s703, arranging a carrier and a pin on the connecting layer according to the positioning identifier; s704, mounting the chip on a carrier; s705, bonding two ends of the lead with the chip and the lead respectively; s706, plastically packaging the chip, the pins, the leads and the carrier; s707, heating to remove the connecting layer and the carrier plate; and S708, polishing a first contact surface of the pin, wherein the first contact surface is the surface of the pin, which is in contact with the connecting layer.
In this embodiment, the method for removing the connection layer 2 and the carrier plate 1 is heating, when the connection layer 2 is a hot-melt adhesive layer or a tin alloy or tin layer, the connection layer 2 can be melted and lose viscosity by heating to a certain temperature, and the carrier plate 1 and the connection layer 2 can be easily taken down, wherein when the connection layer 2 is a tin alloy or metallic tin, and the heating temperature is raised to be higher than the melting point of the tin alloy or metallic tin to remove the carrier plate 1, a part of the tin layer naturally remains on the pin and the carrier, so as to protect the pin and the carrier, increase the solderability, and avoid electroplating.
In addition, as shown in fig. 8, the method for packaging a circuit with a three-layer board structure includes: s801, covering a connecting layer on a carrier plate; s802, setting a positioning mark on the connection layer; s803, arranging a carrier and pins on the connection layer according to the positioning marks; s804, mounting the chip on a carrier; s805, bonding two ends of the lead with the chip and the lead respectively; s806, plastic packaging the chip, the pins, the leads and the carrier; s807, removing the connecting layer and the carrier plate by ultraviolet irradiation; and S808, polishing the first contact surface of the pin, wherein the first contact surface is the surface of the pin, which is in contact with the connecting layer.
In this embodiment, the adhesive property of the adhesive layer of the connection layer 2 is removed by irradiating the connection layer 2 and the carrier substrate 1 with ultraviolet rays, so that the carrier substrate 1 and the connection layer 2 can be easily removed. In this solution, the carrier plate 1 is made of an ultraviolet light permeable material, such as quartz glass; the connecting layer 2 is made of photosensitive bonding material, and the bonding strength of the connecting layer is greatly reduced after the connecting layer is irradiated by ultraviolet light. The implementation method is simple and quick in process and convenient for quick packaging.
As shown in fig. 9, the method for packaging a circuit with a three-layer board structure includes: s901, covering a connecting layer on a carrier plate; s902, setting a positioning mark on the connection layer; s903, arranging a carrier and a pin on the connecting layer according to the positioning identifier; s904, mounting the chip on a carrier; s905, bonding two ends of the lead with the chip and the pin respectively; s906, plastically packaging the chip, the pins, the leads and the carrier; s907, grinding the connecting layer and the carrier plate; and S908, polishing a first contact surface of the pin, wherein the first contact surface is a surface of the pin, which is in contact with the connecting layer.
In this embodiment, the connection layer 2 and the carrier 1 are physically removed by a method of removing the connection layer 2 and the carrier 1 by chemical mechanical polishing, and the process is simple.
In one embodiment of the present invention, preferably, as shown in fig. 10, the method for packaging a circuit with a three-layer board structure includes: s1001, as shown in fig. 11 and 12, covering the carrier board 1 with the connection layer 2; s1002, setting a positioning mark on the connecting layer; s1003, as shown in fig. 31, mounting the pad 6 and the carrier 32 on the connection layer 2; s1004, as shown in fig. 31, mounting the passive device 7 on the pad 6; s1005, bonding two ends of a lead with the pad and the lead respectively; s1006, as shown in fig. 32, setting the pin 31 on the connection layer 2 according to the positioning identifier; s1007, as shown in fig. 33, mounting the chip 4 on the carrier 1; s1008, as shown in fig. 34, bonding both ends of the lead 5 to the chip 4 and the lead 31, respectively; s1009, as shown in fig. 35, the plastic package chip 4, the pins 31, the leads 5, the carrier 1, the pads 6, and the passive devices 7; s1010, as shown in fig. 36, removing the connection layer 2 and the carrier board 1; s1011, as shown in fig. 37, polishing the first contact surface of the lead 31, the first contact surface being the surface of the lead contacting the connection layer.
In the embodiment, the bonding pad structure is added, so that the integrated passive device packaging can be realized, and the packaging integration level can be effectively improved.
In one embodiment of the present invention, preferably, the pins 31 are distributed on both sides of the chip 4 according to actual requirements; or the pins 31 are distributed around the chip 4; or the pins 31 are arranged in an array on the connection layer 2.
In the description of the present invention, the terms "plurality" or "a plurality" refer to two or more, and unless otherwise specifically limited, the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are merely for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention; the terms "connected," "mounted," "secured," and the like are to be construed broadly and include, for example, fixed connections, removable connections, or integral connections; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the description of the present invention, the description of the terms "one embodiment," "some embodiments," "specific embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In the present invention, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for packaging a circuit with a three-layer plate structure is characterized by comprising the following steps:
covering the connecting layer on the carrier plate;
arranging a positioning mark on the connecting layer;
arranging a carrier and a pin on the connecting layer according to the positioning identifier;
mounting a chip on the carrier;
bonding two ends of a lead with the chip and the lead respectively;
plastically packaging the chip, the pins, the leads and the carrier;
removing the connecting layer and the carrier plate;
polishing a first contact surface of the pin, wherein the first contact surface is the surface of the pin which is in contact with the connecting layer;
arranging a metal layer on the connecting layer;
etching the metal layer according to the positioning marks to form the carrier and the pins;
the connecting layer is a tin alloy layer, a tin layer or an adhesive layer.
2. The method for packaging a circuit with a three-layer board structure according to claim 1, wherein the step of arranging a carrier and a pin on the connection layer according to the positioning mark specifically comprises the steps of:
cutting, etching or punching a metal plate to form the pins and the carrier in a preset shape;
installing the pins and the carrier on the connecting layer according to the positioning identification;
the mounting method is one or combination of methods such as brazing, eutectic welding, gluing and the like.
3. The method of claim 1 wherein the leads and the carrier are surface treated with silver, nickel-palladium-gold, or gold.
4. The method for packaging a circuit with a three-layer board structure according to claim 1, wherein the mounting of the chip on the carrier comprises:
bonding the chip to the carrier by gluing; or
Bonding the chip to the carrier by soldering; or
Bonding the chip to the carrier by eutectic bonding.
5. The method of claim 1, wherein the removing the connection layer and the carrier is specifically:
heating to remove the connecting layer and the carrier plate; and/or
Removing the connecting layer and the carrier plate by ultraviolet irradiation; and/or
And grinding to remove the connecting layer and the carrier plate.
6. The method for packaging a circuit with a three-layer board structure according to claim 1, wherein the integrated package of the passive device can be realized by mounting pads, which are specifically as follows:
mounting a pad on the connection layer;
mounting a passive device on the pad;
and bonding two ends of a lead with the bonding pad and the lead respectively, and/or bonding with the bonding pad and the carrier respectively.
7. The method of claim 1 wherein the substrate is a substrate of a three-layer board structure,
the section of each pin is inverted trapezoid or inverted convex, so that the area of one surface of each pin, which is far away from the carrier plate, is larger than the area of one surface of each pin, which is close to the carrier plate;
the section of the carrier is inverted trapezoid or inverted convex, so that the area of one surface of the carrier, which is far away from the carrier plate, is larger than the area of one surface of the carrier, which is close to the carrier plate.
8. The method of packaging a circuit having a three-layer board structure according to any one of claims 1 to 7,
the pins are distributed on two sides of the chip; or
The pins are distributed around the chip; or
The pins are arranged on the connecting layer in an array mode.
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| CN110323141B (en) * | 2019-04-15 | 2021-10-12 | 矽力杰半导体技术(杭州)有限公司 | Lead frame structure, chip packaging structure and manufacturing method thereof |
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| CN102683230B (en) * | 2012-05-30 | 2015-06-17 | 天水华天科技股份有限公司 | Quad flat no-lead multi-circle-arranged integrated circuit (IC) chip packaging part and production method thereof |
| CN106206328B (en) * | 2016-07-27 | 2018-12-18 | 桂林电子科技大学 | A kind of production method being embedded to Chip package substrate |
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Application publication date: 20180817 Assignee: Guilin Xinyi Semiconductor Technology Co.,Ltd. Assignor: GUILIN University OF ELECTRONIC TECHNOLOGY Contract record no.: X2023980046246 Denomination of invention: Packaging methods for three-layer board structure circuits Granted publication date: 20210101 License type: Common License Record date: 20231108 |
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