CN108415331A - AI deep learnings board and its power source supply method - Google Patents
AI deep learnings board and its power source supply method Download PDFInfo
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- CN108415331A CN108415331A CN201810205677.7A CN201810205677A CN108415331A CN 108415331 A CN108415331 A CN 108415331A CN 201810205677 A CN201810205677 A CN 201810205677A CN 108415331 A CN108415331 A CN 108415331A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2615—Audio, video, tv, consumer electronics device
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2642—Domotique, domestic, home control, automation, smart house
Abstract
The embodiment of the invention discloses a kind of AI deep learnings board and its power source supply methods, the AI deep learnings board includes control system, one or more AI processing units, this method is respectively powered control system in deep learning board and AI processing units by independent PCIE power supplys and ATX power supplys respectively, and multiple power supply chips in respective power module are controlled using the electrifying timing sequence of two-stage, it is ensured that the power supply of deep learning board more stablizes, is reliable.
Description
Technical field
The present invention relates to the power supply power supply technical field of integrated circuit, more particularly to a kind of AI deep learnings board and its
Power source supply method.
Background technology
With the fast development of internet and information industry, various sound, image, video data are in the hair of blowout
Exhibition, big data processing gradually replaces traditional artificial data to handle, and the application of artificial intelligence (abbreviation AI) technology makes
Big data analysis processing capacity is leaped again.
Depth learning technology has caused the high speed development of artificial intelligence application, when the mankind being led to enter intelligent by the information age
Generation.Deep learning essence is a kind of machine learning techniques, needs powerful hardware computing capability, to complete complicated data processing
And operation.For so huge data processing and operation, in existing artificial intelligence solution, using dedicated AI processing
Chip executes deep learning operation.
For this AI processing systems for executing deep learning operation, stable supply voltage and correctly power on
Sequential is the primary condition of system worked well.In fact, due to power-supply system dead resistance, parasitic capacitance, parasitic inductance
In the presence of spurious impedance is not zero, and when electric current is flowed out from power supply, when reaching die terminals to be powered, meeting cause one in die terminals
Fixed direct current pressure drop and transient noise.Meanwhile die terminals also suffer from the interference of other signals, can also couple a part of noise.
In general, when the sum of direct current pressure drop and various noises are less than the fluctuating range of chip operating voltage, chip could work normally.
And determining that the fundamental of AI operation grades is the computing capability of AI processing systems, the arithmetic speed of high speed can guarantee stronger
Computing capability, when system executes supercomputing, direct current pressure drop and noise meeting bigger, the requirement to power supply is also with regard to higher.
Chinese invention patent application CN201210173880.3 proposes a kind of power-on time sequence control circuit of PCIE boards
And method, the circuit and method carry out delays time to control by a DC power supply to remaining DC power supply, ensure that chip needs
Each power supply complete to power in a certain order, and using the adaptive side of PCIE slots and external power supply dual power supply
Formula.But the centralized power power supply mode of this PCIE boards cannot be satisfied AI deep learning boards to the steady of power supply power supply
The demands such as qualitative, reliability.
Invention content
To solve the above-mentioned problems, according to an aspect of the present invention, a kind of AI deep learnings board, including FPGA are proposed
Control unit, one or more AI processing units and the FPGA power modules that power supply power supply is carried out to the control system
With one or more AI power modules to the corresponding progress power supply power supply of one or more of AI processing units；Wherein,
The external PCIE power supplys of FPGA power modules, the external ATX power supplys of AI power modules；
The FPGA power modules include multiple first power supply chips, multiple straight for being provided for the control system
Galvanic electricity pressure, the AI power modules include multiple second source chips, for providing multiple direct currents for the AI processing units
Pressure；
The FPGA power modules include power supply timing control unit, for controlling the multiple first power supply chip
Electric sequential, the control system include GPIO interface control unit, for controlling the multiple second source chip
Electric sequential.
In some embodiments, the power supply timing control unit includes multiple cascade power supply timing controllers,
The enable pin phase that the power supply timing controller passes through enable signal output pin and next level power supply timing controller
Even.
In some embodiments, the quantity of the cascade power supply timing controller depends on the first power supply core
The quantity of piece.
In some embodiments, the power supply timing controller by enable signal output pin to the multiple
The enable pin of one power supply chip exports enable signal, to control the electrifying timing sequence of the multiple first power supply chip.
In some embodiments, the GPIO interface control unit includes multiple GPIO interfaces, for respectively to described
The enable pin of multiple second source chips exports enable signal, to control when powering on of the multiple second source chip
Sequence.
In some embodiments, the control system includes PCIE interfaces and Serdes interfaces, and the PCIE connects
Mouth obtains the PCIE power supplys for connecting host, and from host, and the Serdes interfaces are for connecting AI processing units, with institute
It states AI processing units and carries out serial data communication.
In some embodiments, when one or more of AI processing units are multiple, multiple AI processing units are logical
It crosses Serdes interfaces and carries out serial communication connection.
In some embodiments, the control system and the AI processing units are connected altogether by Zero-ohm resistor
It connects.
According to another aspect of the present invention, propose that a kind of power source supply method of AI deep learnings board, the AI are deep
Degree study board includes control system, one or more AI processing units, the method includes：
By PCIE power supplys input supply voltage is provided for multiple first power supply chips；
By ATX power supplys input supply voltage is provided for multiple second source chips；
Multiple enable signals are exported by power supply timing control unit, control the upper of the multiple first power supply chip respectively
Electric sequential, to provide multiple DC voltages for the control system；
Multiple enable signals are exported by the GPIO interface control unit in the control system, respectively described in control
The electrifying timing sequence of multiple second source chips, to provide multiple direct currents respectively for one or more of AI processing units
Pressure.
In some embodiments, the power supply timing control unit includes multiple cascade power supply timing controllers,
The enable pin phase that the power supply timing controller passes through enable signal output pin and next level power supply timing controller
Even.
In some embodiments, the quantity of the cascade power supply timing controller depends on the first power supply core
The quantity of piece.
In some embodiments, the power supply timing controller by enable signal output pin to the multiple
The enable pin of one power supply chip exports enable signal, to control the electrifying timing sequence of the multiple first power supply chip.
In some embodiments, the GPIO interface control unit includes multiple GPIO interfaces, for respectively to described
The enable pin of multiple second source chips exports enable signal, to control when powering on of the multiple second source chip
Sequence.
In some embodiments, the control system includes PCIE interfaces and Serdes interfaces, and the PCIE connects
Mouth obtains the PCIE power supplys for connecting host, and from host, and the Serdes interfaces are for connecting AI processing units, with institute
It states AI processing units and carries out serial data communication.
In some embodiments, when one or more of AI processing units are multiple, multiple AI processing units are logical
It crosses Serdes interfaces and carries out serial communication connection.
In some embodiments, the control system and the AI processing units are connected altogether by Zero-ohm resistor
It connects.
The embodiment of the present invention does not use deep learning board the concentration supply power mode used in tradition PCIE boards, and
It is to use distributed power generation configuration, by independent PCIE power supplys and ATX power supplys respectively to control system in board
It is powered with AI processing units, and multiple power supply chips in respective power module is used with the electrifying timing sequence control of two-stage
System, it is ensured that the power supply of deep learning board more stablizes, is reliable.
Description of the drawings
Fig. 1 is the structural schematic diagram of AI deep learnings board according to an embodiment of the invention；
Fig. 2 is the structural schematic diagram of AI deep learnings board according to another embodiment of the present invention；
Fig. 3 is the sequential control circuit schematic diagram of FPGA power modules according to an embodiment of the invention；
Fig. 4 is the sequential control circuit schematic diagram of FPGA power modules according to another embodiment of the present invention；
Fig. 5 is the sequential control circuit schematic diagram of AI power modules according to an embodiment of the invention；
Fig. 6 is the flow diagram of the power source supply method of AI deep learnings board according to an embodiment of the invention.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
Fig. 1 is the structural schematic diagram of AI deep learnings board 10 according to an embodiment of the invention.As shown in Figure 1, described
AI deep learnings board 10 includes control system 1 and AI processing units 2, and carries out power supply confession to control system 1
The FPGA power modules 3 of electricity and the AI power modules 4 that power supply power supply is carried out to AI processing units 2, wherein outside FPGA power modules 3
Connect PCIE power supplys, 4 external ATX power supplys of AI power modules.PCIE power supplys be the 3.3V provided by host mainboard PCIE slots and
12V DC power supply, ATX power supplys are that 220V AC powers are converted to 3.3V, 5V, the 12V DC power supply that computer-internal uses.
For the AI processing units 2 for executing AI calculation process, the control system 1 passes through PCIE interfaces and host
Connection, and the PCIE power supplys are obtained from host, it is additionally operable to execute host PC IE interfaces to communication interface between AI processing units
Conversion, and control the power supply of AI power modules 4 and control the functions such as other peripheral hardwares.Control system 1 and AI processing
Using the serial/Serdes interfaces that unstring into row data communication between unit 2.
Control system 1 and 2 required supply voltage of AI processing units are related to multiple electricity such as core voltage, IO voltages
The range of voltage values of pressure value, wherein control system includes 0.95V~1.8V；The range of voltage values of AI processing units includes
0.975V~5V, and need the requirement for meeting large current load.In the embodiment of the present invention, FPGA power modules 3 and AI power supplys
Module 4 is all made of multiple independent power supply chips to generate corresponding voltage value, and FPGA power modules 3 include M power supply chip
5-1,5-2 ..., 5-M, AI power modules 4 include N number of power supply chip 6-1,6-2 ..., 6-N, M, N are the integer more than 1.
Multiple power supply chips in FPGA power modules 3 and AI power modules 4 need to meet electrifying timing sequence requirement, the present invention
Embodiment controls the electrifying timing sequence of each road power supply by controlling the enable pin of each power supply chip.Wherein, FPGA power modules 3
By power supply timing control unit 8 control the M power supply chip 5-1,5-2 ..., the electrifying timing sequence of 5-M, wait for that FPGA controls are single
After first powered stable, control system exports enabled letter by GPIO (general input/output port) interface control unit 7
Number, N number of power supply chip in AI power modules 4 is controlled respectively, to control when the powering on of plurality of voltages of AI power modules 4
Sequence.It, can be by Zero-ohm resistor common ground connection, in this way between control system 1 and AI processing units 2 in the embodiment of the present invention
The interference of AI processing units and control system power supply between the two can be reduced to the greatest extent.
In order to meet requirement of the AI processing units to power supply, the deep learning board of the embodiment of the present invention does not use tradition
Concentration supply power mode used in PCIE boards, but use distributed power generation configuration, by independent PCIE power supplys and
ATX power supplys are respectively powered control system in board and AI processing units, and to more in respective power module
A power supply chip is controlled using the electrifying timing sequence of two-stage, it is ensured that the power supply of deep learning board more stablizes, is reliable.
Fig. 2 is the structural schematic diagram of AI deep learnings board 20 according to another embodiment of the present invention.The AI depth
The quantity that board 20 extends AI processing units on the basis of Fig. 1 embodiments is practised, Fig. 2 is only symbolically presented at two AI
Manage the example of unit 2-1 and 2-2, can be calculated according to AI in practical application power demand configure AI processing units to it is concatenated more
It is a.
As shown in Fig. 2, AI deep learnings board 20 includes the AI processing units of control system 1 and multiple serial connections
2-1,2-2, and to control system 1 carry out power supply power supply FPGA power modules 3 and to AI processing units 2-1,2-2 into
Multiple AI power modules 4-1,4-2 of row power supply power supply, wherein 3 external PCIE power supplys of FPGA power modules, AI power modules 4-
1, the external ATX power supplys of 4-2.
The AI processing units 2-1 and 2-2 carries out serial data communication by Serdes interfaces.The FPGA power modules
3 include M power supply chip 5-1,5-2 ..., 5-M, AI the power modules 4-1 and 4-2 respectively include N number of power supply chip 6-1,
6-2 ..., 6-N, M, N are the integer more than 1.FPGA power modules 3 control the M electricity by power supply timing control unit 8
Source chip 5-1,5-2 ..., the electrifying timing sequence of 5-M, after control system powered stable, control system passes through GPIO
(general input/output port) interface control unit 7 exports enable signal, controls respectively N number of in AI power modules 4-1,4-2
Power supply chip, to control the electrifying timing sequence of plurality of voltages in multiple AI power modules 4-1,4-2.
In some embodiments, power supply timing control core may be used in power supply timing control unit in FPGA power modules
Piece is realized, such as the power supply timing controller realization of LM3881 may be used.FPGA power modules pass through power supply timing control
The enable signal output pin of chip controls the electrifying timing sequence of multiple power supply chips respectively.Fig. 3 is according to one embodiment of the invention
FPGA power modules sequential control circuit schematic diagram, Fig. 3 only symbolically presents tool there are three enable signal efferent duct
The power supply timing controller 8 of foot EN1, EN2, EN3 control the example of the electrifying timing sequence of three power supply chips respectively.
As shown in figure 3, power supply chip 5-1,5-2,5-3 include enable pin EN, three of power supply timing controller 8
Enable pin EN1-EN3 is separately connected the enable pin of power supply chip 5-1,5-2,5-3.When host mainboard after the power is turned on, when power supply
Sequence controls chip 8 after mainboard PCIE power supplys obtain supply voltage and enable signal, according to intervals to the power supply
Chip 5-1,5-2,5-3 export enable signal respectively, to control the electrifying timing sequence of three-way power chip.
When there are the source voltage requirements of more multichannel in control system, power supply timing controller can also be passed through
The electrifying timing sequence control of more power supply chips is realized in cascade.Fig. 4 is FPGA power modules according to another embodiment of the present invention
Sequential control circuit schematic diagram, Fig. 4 only symbolically present two power supply timing controller 8-1,8-2 pass through cascade point
Not Kong Zhi five power supply chips electrifying timing sequence example.As shown in figure 4, power supply timing controller 8-1 passes through one of them
Enable signal output pin EN3 connects the enable pin EN of another power supply timing controller 8-2, power supply timing controller 8-
EN1-EN3 points of the enable signal output pin of 1 enable signal output pin EN1, EN2 and power supply timing controller 8-2
Not Lian Jie power supply chip 5-1,5-2,5-3,5-4 and 5-5 enable pin, pass through grade to power supply sequence controller 8-1 and 8-2
Connection exports enable signal to five power supply chips respectively according to intervals, controls when powering on of five power supply chips
Sequence.
In the embodiment of the present invention, can according to control system to the actual demand of supply voltage come expansion of power supply chip
Quantity, and by the cascade quantity of expansion of power supply timing controller, realize the electrifying timing sequence control of power supply chip after extension.
Fig. 5 is the sequential control circuit schematic diagram of AI power modules according to an embodiment of the invention.Fig. 5 is only symbolically
Present the example of the electrifying timing sequence control of five power supply chips in AI power modules 4.As shown in figure 5, control system 1
GPIO interface control unit 7 includes multiple GPIO interface GPIO1-GPIO5, five electricity being separately connected in AI power modules 4
The enable pin of source chip 6-1,6-2,6-3,6-4 and 6-5.After 1 powered stable of control system, control system 1
By the GPIO interface GPIO1-GPIO5, make successively to described five power supply chips 6-1,6-2,6-3,6-4 and 6-5 output
Energy signal, to control 5 road voltage electrifying timing sequences of AI power modules 4.
Fig. 6 is the flow diagram of the power source supply method of AI deep learnings board according to an embodiment of the invention.Institute
It includes control system, one or more AI processing units to state AI deep learning boards, as shown in fig. 6, this method includes：
Step S1 provides input supply voltage by PCIE power supplys for multiple first power supply chips；
Step S2 provides input supply voltage by ATX power supplys for multiple second source chips；
Step S3 exports multiple enable signals by power supply timing control unit, controls the multiple first power supply respectively
The electrifying timing sequence of chip, to provide multiple DC voltages for the control system；
Step S4 exports multiple enable signals, respectively by the GPIO interface control unit in the control system
The electrifying timing sequence of the multiple second source chip is controlled, it is multiple to be provided respectively for one or more of AI processing units
DC voltage.
In some embodiments, the power supply timing control unit can be cascaded by multiple power supply timing controllers
Realize, and the cascade quantity of power supply timing controller can according to control system to the actual demand of supply voltage come
The electrifying timing sequence control of multiple first power supply chips after extension is realized in extension.The power supply timing controller passes through enabled letter
Number output pin exports enable signal to the enable pin of the multiple first power supply chip, to control the multiple first electricity
The electrifying timing sequence of source chip.
In some embodiments, the GPIO interface control unit in the control system includes that multiple GPIO connect
Mouthful, the enable signal of corresponding second source number of chips can be exported, to control the electrifying timing sequence of multiple second source chips.
The control system includes PCIE interfaces and Serdes interfaces, and the PCIE interfaces are obtained for connecting host from host
The PCIE power supplys are obtained, the Serdes interfaces carry out serial data for connecting AI processing units, with the AI processing units
Communication.When the AI deep learnings board includes multiple AI processing units, multiple AI processing units by Serdes interfaces into
Row serial communication connects.
The power source supply method of the deep learning board of the embodiment of the present invention uses distributed power supply power supply mode, leads to
Independent PCIE power supplys and ATX power supplys is crossed respectively to supply control system in deep learning board and AI processing units
Electricity, and multiple power supply chips in respective power module are controlled using the electrifying timing sequence of two-stage, it is ensured that deep learning plate
The power supply of card more stablizes, is reliable.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the present invention
Within the scope of shield.
Claims (16)
1. a kind of AI deep learnings board, which is characterized in that including control system, one or more AI processing units, with
And to the FPGA power modules of control system progress power supply power supply and to one or more of AI processing units pair
It should carry out one or more AI power modules of power supply power supply；Wherein,
The external PCIE power supplys of FPGA power modules, the external ATX power supplys of AI power modules；The FPGA power modules packet
Multiple first power supply chips are included, for providing multiple DC voltages for the control system, the AI power modules include
Multiple second source chips, for providing multiple DC voltages for the AI processing units；
The FPGA power modules include power supply timing control unit, for controlling when powering on of the multiple first power supply chip
Sequence, the control system include GPIO interface control unit, for controlling when powering on of the multiple second source chip
Sequence.
2. AI deep learnings board according to claim 1, which is characterized in that the power supply timing control unit includes more
A cascade power supply timing controller, the power supply timing controller pass through enable signal output pin and next level power supply
The enable pin of timing controller is connected.
3. AI deep learnings board according to claim 2, which is characterized in that the cascade power supply timing controller
Quantity depend on first power supply chip quantity.
4. AI deep learnings board according to claim 3, which is characterized in that the power supply timing controller is by making
Can signal output pin export enable signal to the enable pin of the multiple first power supply chip, to control the multiple the
The electrifying timing sequence of one power supply chip.
5. AI deep learnings board according to claim 1, which is characterized in that the GPIO interface control unit includes more
A GPIO interface, for exporting enable signal to the enable pin of the multiple second source chip respectively, described in control
The electrifying timing sequence of multiple second source chips.
6. AI deep learnings board according to claim 1, which is characterized in that the control system includes that PCIE connects
Mouth and Serdes interfaces, the PCIE interfaces obtain the PCIE power supplys for connecting host from host, and the Serdes connects
Mouth carries out serial data communication for connecting AI processing units, with the AI processing units.
7. AI deep learnings board according to claim 1, which is characterized in that when one or more of AI processing units
When being multiple, multiple AI processing units carry out serial communication connection by Serdes interfaces.
8. AI deep learnings board according to claim 1, which is characterized in that at the control system and the AI
Reason unit passes through Zero-ohm resistor common ground connection.
9. a kind of power source supply method of AI deep learnings board, the AI deep learnings board include control system, one
A or multiple AI processing units, which is characterized in that the method includes：
By PCIE power supplys input supply voltage is provided for multiple first power supply chips；
By ATX power supplys input supply voltage is provided for multiple second source chips；
Multiple enable signals are exported by power supply timing control unit, control when powering on of the multiple first power supply chip respectively
Sequence, to provide multiple DC voltages for the control system；
Multiple enable signals are exported by the GPIO interface control unit in the control system, are controlled respectively the multiple
The electrifying timing sequence of second source chip, to provide multiple DC voltages respectively for one or more of AI processing units.
10. power source supply method according to claim 9, which is characterized in that the power supply timing control unit includes more
A cascade power supply timing controller, the power supply timing controller pass through enable signal output pin and next level power supply
The enable pin of timing controller is connected.
11. power source supply method according to claim 10, which is characterized in that the cascade power supply timing controller
Quantity depend on first power supply chip quantity.
12. power source supply method according to claim 11, which is characterized in that the power supply timing controller is by making
Can signal output pin export enable signal to the enable pin of the multiple first power supply chip, to control the multiple the
The electrifying timing sequence of one power supply chip.
13. power source supply method according to claim 9, which is characterized in that the GPIO interface control unit includes more
A GPIO interface, for exporting enable signal to the enable pin of the multiple second source chip respectively, described in control
The electrifying timing sequence of multiple second source chips.
14. power source supply method according to claim 9, which is characterized in that the control system includes that PCIE connects
Mouth and Serdes interfaces, the PCIE interfaces obtain the PCIE power supplys for connecting host from host, and the Serdes connects
Mouth carries out serial data communication for connecting AI processing units, with the AI processing units.
15. power source supply method according to claim 9, which is characterized in that when one or more of AI processing units
When being multiple, multiple AI processing units carry out serial communication connection by Serdes interfaces.
16. power source supply method according to claim 9, which is characterized in that at the control system and the AI
Reason unit passes through Zero-ohm resistor common ground connection.
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| CN109871950A (en) * | 2019-02-01 | 2019-06-11 | 京微齐力(北京)科技有限公司 | Unit has the chip circuit and System on Chip/SoC of the artificial intelligence module of bypass functionality |
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