CN108401122A - A kind of high-precision DAC for cmos image sensor - Google Patents
A kind of high-precision DAC for cmos image sensor Download PDFInfo
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- CN108401122A CN108401122A CN201810267549.5A CN201810267549A CN108401122A CN 108401122 A CN108401122 A CN 108401122A CN 201810267549 A CN201810267549 A CN 201810267549A CN 108401122 A CN108401122 A CN 108401122A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- Transforming Light Signals Into Electric Signals (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The present invention provides a kind of high-precision DAC for cmos image sensor, including separately positioned M position high ordertransfers and (K M) position low level are converted, and high position high reference output buffering and high-order low reference output buffering；M high ordertransfer output ends provide 2KThe high reference output and low reference in a section export, each the high reference output in section and low reference output are coupled with the analog references end that low level is converted with high-order low reference output buffering by corresponding high position high reference output buffering and provide analog reference voltage, and transformed export of low level is final simulation output.The present invention realizes area and the power dissipation overhead optimization of multi-channel high-accuracy DAC, eliminate the voltage jump problem in high-low-position handoff procedure, solve the problems, such as that high-precision DAC's is non-monotonic, it is ensured that the uniformity of the black-level correction of cmos image sensor and the correction of row fixed pattern noise.
Description
Technical field
The present invention relates to cmos image sensor, specially a kind of high-precision DAC for cmos image sensor.
Background technology
In recent years, at low cost, speed is fast, can the processing of on piece integrated image with the continuous development of CMOS manufacturing process
The advantages that unit, Radiation hardness are strong, low in energy consumption gradually embodies, and image quality is also promoted steadily, in civil electronic consumption market,
Such as high-definition camera, slr camera, mobile phone field have been substituted CCD, in occupation of dominant position.Its application scenario also begin to by
Commercial market is extended to aerospace field, some domestic scientific research institutions have begun to attempt to use large area array cmos detector
Replace traditional line array CCD, the main detector as space exploration.
For to arrange the super large face array CMOS image sensor based on grade playback mode, due to correlated-double-sampling, programmable
All there is different offset voltages in the processing modules such as gain amplifier, row buffering, output buffering and A/D converter, cause most
The fixed pattern noise of whole picture signal.When technique is realized, since the factors such as inconsistent of size and doping make each column read
The offset voltage of outgoing link is different, for the imaging sensor of super large area array, since row read the distance of link spatially very
Far, inconsistent degree bigger, offset voltage is caused to differ bigger, the illumination for same intensity, pixel array generates image electricity
It presses signal identical, however, the voltage signal needs after reading link processing, reflects that the voltage signal of light intensity has incorporated reading
The superposition of link offset voltage.
It is that positive row read link for offset voltage, the image of respective column is brighter than actual, and for offset voltage
Link is read for negative row, the image of respective column is darker than actual.Human eye is to the very sensitive of column direction, studies have shown that row
Subjective visual effect caused by FPN is 5 times of same order pixel FPN.Therefore in order to improve the image quality of sensing system,
Row grade fixed pattern noise must be corrected.Configurable DAC technique generally may be used to realize, but in order to realize full figure
The black-level correction of element, the fixed pattern noise between interchannel and row grade correct, need to use multiple DAC, severe exacerbations face
Product and power dissipation overhead.
Invention content
For problems of the prior art, the present invention provides a kind of high-precision DAC for cmos image sensor,
Area is small, low in energy consumption, and voltage is steady, it can be ensured that the black-level correction of cmos image sensor is corrected with row fixed pattern noise
Uniformity.
The present invention is to be achieved through the following technical solutions：
A kind of high-precision DAC for cmos image sensor, including separately positioned M position high ordertransfers and the position (K-M)
Low level is converted, and high position high reference output buffering and high-order low reference output buffering；
M high ordertransfer output ends provide 2KThe high reference output and low reference in a section export, the senior staff officer in each section
Examine output and it is low with reference to output by corresponding high-order high reference output buffering and it is high-order it is low be coupled with reference to output buffering it is low
The analog references end of position conversion provides analog reference voltage, and the transformed output of low level is final simulation output.
Preferably, M high ordertransfers are located in the global unit of DAC, reading electricity of low level conversion in the position (K-M) positioned at DAC
In each channel on road.
Preferably, high-order high reference output buffering and the high-order low both ends with reference to output buffering respectively by switch switch and
M high ordertransfers and the conversion connection of the position (K-M) low level.
Preferably, switching switch includes eight switches；
The high reference output of M high ordertransfer output ends is successively through first switch, high-order high reference output buffering and the 5th
Switch is connected to the high pressure simulation reference edge of the position (K-M) low level conversion；
The high reference output of M high ordertransfer output ends is successively through third switch, high-order low reference output buffering and the 6th
Switch is connected to the high pressure simulation reference edge of the position (K-M) low level conversion；
M the low of high ordertransfer output end switch successively through the 4th with reference to output, are high-order low with reference to output buffering and the 8th
Switch is connected to the low-voltage simulation reference edge of the position (K-M) low level conversion；
M the low of high ordertransfer output end export buffering and the 8th through second switch, high-order high reference successively with reference to output
Switch is connected to the low-voltage simulation reference edge of the position (K-M) low level conversion.
Further, in first high-order section, the 4th switch and the 8th switch conduction, the low simulation that high ordertransfer is exported
Reference voltage send the low reference edge converted to low level, first switch and the 5th switch conduction, and high by high ordertransfer output is simulated
Reference voltage send the high reference end converted to low level；Second switch, the 6th switch, third switch and the 7th switch disconnect；
In second high-order section, second switch and the 7th switch conduction, by the low analog references electricity of high ordertransfer output
The low reference edge that force feed to low level is converted, third switch and the 6th switch conduction, by the high analog references electricity of high ordertransfer output
The high reference end that force feed to low level is converted, first switch, the 5th switch, the 4th switch and the 8th switch disconnect；
Identical as first high-order section in the high-order section of third, the 4th switch and the 8th switch conduction turn a high position
The low analog reference voltage for changing output send the low reference edge converted to low level, first switch and the 5th switch conduction, and a high position is turned
The high analog reference voltage for changing output send the high reference end converted to low level；Second switch, the 6th switch, third switch and the 7th
Switch disconnects；
In the 4th high-order section, identical as second high-order section, second switch and the 7th switch conduction turn a high position
The low analog reference voltage for changing output send the low reference edge converted to low level, third switch and the 6th switch conduction, and a high position is turned
The high analog reference voltage for changing output send the high reference end converted to low level, first switch, the 5th switch, the 4th switch and the 8th
Switch disconnects；
The conversion of entire DAC is completed in such repetitive operation, final to realize high-low-position seamless switching.
Preferably, M high ordertransfers are including the first decoder and by 2MThe positions the M conversion in series of a resistance, first translates
Code device is according to the M digit numeric codes D of input0、D1、……DMCorresponding reference interval is gated, each section corresponds to M conversions of a high position
A LSB；
Wherein, total analog quantization section is (VT-VB), then LSB=(V of high ordertransferT-VB)/2M, that is, the height that exports
Voltage is the upper and lower ends voltage of a certain resistance.
Preferably, the position (K-M) low level conversion includes the second decoder and by 2(K-M)A resistance position (K-M) in series turns
It changes, the second decoder is according to (K-M) the digit numeric code D of input(M-1)、D(M-2)、……DKCorresponding reference voltage output is gated, it is low
The LSB of position conversion is the LSB=(V of entire DACTL-VB)/2K。
Compared with prior art, the present invention has technique effect beneficial below：
A kind of high-precision DAC for cmos image sensor of the present invention is segmented DAC designing techniques by high-low-position, real
Area and the power dissipation overhead optimization of multi-channel high-accuracy DAC are showed；Pass through the synchronizing signal link switching in high-order handoff procedure
Technology eliminates the voltage jump problem in high-low-position handoff procedure, solves the problems, such as that high-precision DAC's is non-monotonic, it is ensured that
The uniformity of the black-level correction of cmos image sensor and the correction of row fixed pattern noise.
Description of the drawings
Fig. 1 is the high-precision DAC basic structures proposed by the present invention for large area array cmos image sensor.
Fig. 2 is the high-precision DAC concrete structures proposed by the present invention for large area array cmos image sensor.
Fig. 3 is the voltage jump schematic diagram in traditional DAC high-low-positions handoff procedure.
Fig. 4 is the high-precision DAC high-low-position seamless switching process schematics of the present invention.
Fig. 5 is a kind of realization example of the present invention.
Specific implementation mode
With reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
As shown in Figure 1, a kind of high-precision DAC for cmos image sensor of the present invention, including M high ordertransfers, (K-
M) low level is converted, high-order high reference output buffering, high-order low reference output buffering and switching switch；High ordertransfer output end carries
For 2KThe high reference output in a section and low reference export, and the high reference output and low reference in each section are exported by corresponding
Buffering is connected to the analog references end of low level conversion, and the transformed output of low level is final simulation output.
For K DAC, in order to reduce the area overhead of multichannel cmos image sensor, be divided into M high ordertransfers and
(K-M) low level is converted, and high ordertransfer is located in global unit, and low level conversion is in each channel of reading circuit.M high-order
It is converted to the conversion of (K-M) low level and analog reference voltage is provided.
For the parasitic and interference on large area array cmos image sensor signal path, the high reference of M high ordertransfers is defeated
Go out and is transmitted to low level converting unit using simulated cushioned with reference to output with low.
The high reference output of M high ordertransfers and low reference output switch control mode realization with simulated cushioned use,
During section switches, reference voltage realizes the switching mode of linkage with buffering.
Particular content is：
For the correcting scheme of multichannel parity column：Since the DAC numbers that multichannel parity column is related to are more, if using
Row grade layout type, area overhead can be very big, and power consumption is larger.The present invention uses high-low-position isolation technics, by high ordertransfer
It is positioned in global unit, only low level conversion is positioned in row grade reading circuit, area overhead can be greatly reduced in this way, again
Technological means is provided for optimised power consumption.Meanwhile in order to realize row grade correct, can each channel be arranged two DAC, one
For the correction of odd column, a correction for being used for even column.As shown in Fig. 2, 10 be high ordertransfer unit, 40 convert for low level
Unit.
For the improvement project of high-low-position switching：The 20 and 30 height analog reference voltage exported for high ordertransfer in Fig. 2
Buffer leads in each high-order switching that there are voltages due to imbalance inconsistency intrinsic on 20 and 30 equal signal paths
The problem of mutation, as shown in Figure 3.In order to solve this problem, the present invention proposes to pass through switching signal path so that electricity every time
When crush-cutting changes, signal path is constant, to reduce the inconsistent caused voltage jump of imbalance.Detailed process is：At first
High-order section, the 4th switch 70 and the 8th switch 110 are connected, and the low analog reference voltage that high ordertransfer exports is sent to low level and is turned
The low reference edge changed, first switch 50 and the 5th switch 90 are connected, and the high analog reference voltage that high ordertransfer exports is sent to low
The high reference end of position conversion；Second switch 60, the 6th switch 100, third switch 80 are disconnected with the 7th switch 120；Second
A high position section, second switch 60 and the 7th switch 120 are connected, (actually by the low analog reference voltage of high ordertransfer output
It is also the high reference voltage in first high-order section) send the low reference edge converted to low level, third switch 80 and the 6th switch 100
The high analog reference voltage that high ordertransfer exports is sent the high reference end converted to low level, first switch the 50, the 5th to switch by conducting
90, the 4th switch 70 is disconnected with the 8th switch 110；In the high-order section of third, identical as first high-order section, the 4th opens
Pass 70 and the 8th switch 110 are connected, and send the low analog reference voltage that high ordertransfer exports to the low reference edge converted to low level, the
One switch 50 and the 5th switch 90 are connected, and send the high analog reference voltage that high ordertransfer exports to the high reference converted to low level
End；Second switch 60, the 6th switch 100, third switch 80 are disconnected with the 7th switch 120；In the 4th high-order section, with the
Two high-order sections are identical, and second switch 60 and the 7th switch 120 are connected, the low analog reference voltage that high ordertransfer is exported
(actually and the high reference voltage in first high-order section) send the low reference edge converted to low level, third switch 80 and the 6th
Switch 100 is connected, and send the high analog reference voltage that high ordertransfer exports to the high reference end converted to low level, first switch 50,
5th switch 90, the 4th switch 70 are disconnected with the 8th switch 110；The conversion of entire DAC is completed in such repetitive operation.Finally
Realize high-low-position seamless switching as shown in Figure 4.
Based on the thinking of the present invention, Fig. 5 is a kind of concrete implementation example, and example is illustrated by taking single channel as an example, real
Multiple channels may be divided in border according to the scale of face battle array.In single channel design, the DAC of odd column and even column can be divided into
Correction is illustrated by taking the DAC of odd column designs as an example below, similar for the DAC designs of even column.
The conversion accuracy of DAC is K in example, wherein high-order is M, low level is the position (K-M).The high-order positions M conversion is logical
Cross 2MA resistance is in series, and low level is by 2(K-M)A resistance is in series, it is seen that this mode falls to resistance number by 2K
2M+2(K-M)A, if conversion accuracy is 12, a high position is 5, and low level is 7, then total resistance number can fall to 160 by 4096,
Greatly reduce area overhead.
First decoder 10 is according to the M digit numeric codes (D of input0、D1、……DM) the corresponding reference interval of gating, Mei Gequ
Between M LSB converted of corresponding high position, it is assumed that total analog quantization section is (VT-VB), then LSB=(V of high ordertransferT-
VB)/2M, that is, the high-low voltage exported is the upper and lower ends voltage of a certain resistance.
Low level conversion is similar with a high position, and the second decoder 40 is according to (K-M) digit numeric code (D of input(M-1)、
D(M-2)、……DK) the corresponding reference voltage output of gating, the LSB of low level conversion is the LSB=(V of entire DACTL-VB)/2K。
In example, the high reference voltage of high ordertransfer and low-voltage are joined by the first buffer 20 and the second buffer 30
It examines to send to low level and convert, since there are intrinsic imbalance problem of inconsistency for the first buffer 20 and the second buffer 30, use
Switching signal path mode realizes high-low-position seamless switching.Specific implementation process is：In first high-order section, the 4th
Switch 70 and the 8th switch 110 are connected, and send the low analog reference voltage that high ordertransfer exports to the low reference edge converted to low level,
First switch 50 and the 5th switch 90 are connected, and send the high analog reference voltage that high ordertransfer exports to the high reference converted to low level
End；Second switch 60, the 6th switch 100, third switch 80 are disconnected with the 7th switch 120；In second high-order section, second
Switch 60 and the 7th switch 120 are connected, (actually and first high-order area by the low analog reference voltage of high ordertransfer output
Between high reference voltage) send the low reference edge converted to low level, third switch 80 and the 6th switch 100 are connected, by high ordertransfer
The high analog reference voltage of output send high reference end convert to low level, first switch 50, the 5th switch 90, the 4th switch 70 and
8th switch 110 disconnects；It is identical as first high-order section in the high-order section of third, the 4th switch 70 and the 8th switch
110 conductings send the low analog reference voltage that high ordertransfer exports to the low reference edge converted to low level, first switch 50 and the 5th
Switch 90 is connected, and send the high analog reference voltage that high ordertransfer exports to the high reference end converted to low level；Second switch 60,
Six switches 100, third switch 80 and the 7th switch 120 disconnect；In the 4th high-order section, with second high-order section phase
Together, second switch 60 and the 7th switch 120 are connected, (actually and first by the low analog reference voltage of high ordertransfer output
The high reference voltage in a high position section) send the low reference edge converted to low level, third switch 80 and the 6th switch 100 to be connected, it will
The high analog reference voltage of high ordertransfer output send the high reference end converted to low level, first switch 50, the 5th switch the 90, the 4th
Switch 70 is disconnected with the 8th switch 110；The conversion of entire DAC is completed in such repetitive operation.
Claims (7)
1. a kind of high-precision DAC for cmos image sensor, which is characterized in that including the separately positioned positions M high ordertransfer
The position (K-M) low level conversion, and high position high reference output buffering and high-order low reference output buffering；
M high ordertransfer output ends provide 2KThe high reference output and low reference in a section export, the high reference output in each section
Low level conversion is coupled with by corresponding high position high reference output buffering and high-order low reference output buffering with reference to output with low
Analog references end provide analog reference voltage, low level it is transformed output be final simulation output.
2. a kind of high-precision DAC for cmos image sensor according to claim 1, which is characterized in that M high-order
Conversion is in the global unit of DAC, and low level conversion in the position (K-M) is in each channel of the reading circuit of DAC.
3. a kind of high-precision DAC for cmos image sensor according to claim 1, which is characterized in that high-order high
With reference to output buffering and the high-order low both ends with reference to output buffering respectively by switching switch and M high ordertransfers and the position (K-M)
Low level conversion connection.
4. a kind of high-precision DAC for cmos image sensor according to claim 1, which is characterized in that described
Switching switch includes eight switches；
The high reference output of M high ordertransfer output ends is successively through first switch (50), high-order high reference output buffering and the 5th
Switch (90) is connected to the high pressure simulation reference edge of the position (K-M) low level conversion；
The high reference output of M high ordertransfer output ends is successively through third switch (80), high-order low reference output buffering and the 6th
Switch (100) is connected to the high pressure simulation reference edge of the position (K-M) low level conversion；
M the low of high ordertransfer output end switch (70), high-order low reference output buffering and the 8th through the 4th successively with reference to output
Switch (110) is connected to the low-voltage simulation reference edge of the position (K-M) low level conversion；
M the low of high ordertransfer output end export buffering and the 8th through second switch (60), high-order high reference successively with reference to output
Switch (120) is connected to the low-voltage simulation reference edge of the position (K-M) low level conversion.
5. a kind of high-precision DAC for cmos image sensor according to claim 4, which is characterized in that first
It is a a high position section, the 4th switch (70) with the 8th switch (110) conducting, by high ordertransfer export low analog reference voltage send to
The low reference edge of low level conversion, first switch (50) is with the 5th switch (90) conducting, the high analog references that high ordertransfer is exported
Voltage send the high reference end converted to low level；Second switch (60), the 6th switch (100), third switch (80) and the 7th switch
(120) it disconnects；
In second high-order section, the low simulation of high ordertransfer output is joined in second switch (60) and the 7th switch (120) conducting
Examining voltage send the low reference edge converted to low level, third to switch (80) and the 6th switch (100) conducting, by high ordertransfer output
High analog reference voltage send the high reference end converted to low level, first switch (50), the 5th switch (90), the 4th switch (70) with
8th switch (110) disconnects；
Identical as first high-order section in the high-order section of third, the 4th switch (70) and the 8th switch (110) conducting will
The low analog reference voltage of high ordertransfer output send the low reference edge converted to low level, first switch (50) and the 5th switch (90)
Conducting send the high analog reference voltage that high ordertransfer exports to the high reference end converted to low level；Second switch (60), the 6th open
(100), third switch (80) and the 7th switch (120) is closed to disconnect；
Identical as second high-order section in the 4th high-order section, second switch (60) and the 7th switch (120) conducting will
The low analog reference voltage of high ordertransfer output send the low reference edge converted to low level, third to switch (80) and the 6th switch
(100) it is connected, send the high analog reference voltage that high ordertransfer exports to the high reference end converted to low level, first switch (50),
5th switch (90), the 4th switch (70) and the 8th switch (110) disconnect；
The conversion of entire DAC is completed in such repetitive operation, final to realize high-low-position seamless switching.
6. a kind of high-precision DAC for cmos image sensor according to claim 1, which is characterized in that M high-order
Conversion includes the first decoder (10) and by 2MThe positions the M conversion in series of a resistance, the first decoder (10) is according to the M of input
Digit numeric code D0、D1、……DMCorresponding reference interval is gated, each section corresponds to a LSB of M conversions of a high position；
Wherein, total analog quantization section is (VT-VB), then LSB=(V of high ordertransferT-VB)/2M, that is, the high-low voltage that exports
For the upper and lower ends voltage of a certain resistance.
7. a kind of high-precision DAC for cmos image sensor according to claim 1, which is characterized in that the position (K-M)
Low level conversion includes the second decoder (20) and by 2(K-M)A resistance position (K-M) conversion in series, the second decoder (40) root
According to (K-M) the digit numeric code D of input(M-1)、D(M-2)、……DKCorresponding reference voltage output is gated, the LSB of low level conversion is
LSB=(the V of entire DACTL-VB)/2K。
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