CN108389914A - A kind of passivation tunnel layer material preparation and its application in solar cell - Google Patents

A kind of passivation tunnel layer material preparation and its application in solar cell Download PDF

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Publication number
CN108389914A
CN108389914A CN201810195184.XA CN201810195184A CN108389914A CN 108389914 A CN108389914 A CN 108389914A CN 201810195184 A CN201810195184 A CN 201810195184A CN 108389914 A CN108389914 A CN 108389914A
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carrier
layer
passivation
tantalum
film
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廖明墩
叶继春
曾俞衡
闫宝杰
王丹
高平奇
童慧
全成
张志�
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Ningbo Institute of Material Technology and Engineering of CAS
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Ningbo Institute of Material Technology and Engineering of CAS
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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Abstract

The present invention relates to a kind of passivation tunnel layer material preparation and its in the application of solar cell, specifically, the invention discloses the purposes that a kind of carrier being used to prepare solar cell is passivated tunnelling film, the film contains tantalum pentoxide (Ta2O5).The present invention also provides a kind of carrier transport structures and preparation method thereof being used to prepare solar cell.Carrier passivation tunnelling film provided by the invention overcomes silica and is used as passivation tunnel layer the shortcomings that being passivated in terms of contact heterojunction battery applications.

Description

A kind of passivation tunnel layer material preparation and its application in solar cell
Technical field
The invention belongs to field of inorganic materials, in particular it relates to a kind of passivation tunnel layer material preparation and its The application of solar cell.
Background technology
In recent years, tunnelling oxygen passivation contact crystal silicon solar battery (English is also referred to as TOPCon or POLO batteries) has become state The hot spot of border photovoltaic art, the battery are a kind of by silica and DOPOS doped polycrystalline silicon realization gross area efficient passivation and carrier The battery device of collection, device structure is shown in Figure 1.
Compared with conventional crystal silicon solar battery, oxygen is mainly increased in tunnelling oxygen passivation contact crystal silicon solar battery structure SiClx is passivated two feature functionality layers of tunnel layer and polysilicon carrier-collecting layer, forms electronics or hole selectively transmission knot Structure.Moreover, high temperature preparation process may be used in two feature functionality layers of tunnelling oxygen passivation contact crystal silicon battery, with existing crystalline substance Silion cell manufacturing process is compatible with.Therefore, before tunnelling oxygen passivation contact crystal silicon battery is to have very much in terms of the commercial application Way.
However, silica still has the band rank formed between silicon excessive as passivation tunnel layer, thickness need to be less than 2nm etc. and lack It falls into and is difficult to overcome, to affect giving full play to for the structure battery potentiality.
Therefore, a kind of superior passivation tunnelling layer material of novel performance of exploitation is to improving tunnelling oxygen passivation contact crystal silicon Solar cell performance has great importance.
Invention content
The purpose of the present invention is to provide a kind of passivation tunnelling layer materials.
The present invention also aims to provide a kind of preparation method and application of passivation tunnelling layer material.
First aspect present invention provides a kind of purposes of carrier passivation tunnelling film, and the carrier passivation tunnelling is thin Film contains tantalum pentoxide (Ta2O5);The film is used to prepare solar cell.
In another preferred example, the solar cell is crystal silicon solar energy battery.
In another preferred example, the thickness of the carrier passivation tunnelling film is 0.5-5nm;Preferably, being 1- 2.5nm。
In another preferred example, the carrier is electronics or hole.
In another preferred example, the preparation method of the carrier passivation tunnelling film includes:Using magnetron sputtering (Sputter), plasma enhanced chemical vapor deposition (PECVD), thermal evaporation (Thermal Evaporator), electron beam steam (E-beam Evaporator), low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) method are sent out, is sunk on silicon chip Product tantalum pentoxide (Ta2O5), it is passivated tunnelling film to form the carrier.
In another preferred example, using atomic layer deposition (ALD) method deposition tantalum pentoxide (Ta2O5)。
In another preferred example, the preparation method uses atomic layer deposition (ALD), includes the following steps:
(a) in the vacuum cavity for being loaded with silicon chip, it is passed through the gas containing tantalum (Ta) precursor molecule;
(b) it is passed through inert gas;
(c) it is passed through the gas of oxygen-containing (O) precursor molecule;
(d) it is passed through inert gas;
It is passivated tunnelling film to form the carrier.
In another preferred example, the inert gas is selected from the group:Nitrogen, argon gas or combinations thereof.
In another preferred example, oxygen-containing (O) precursor molecule is selected from the group:H2O、O3Or combinations thereof.
In another preferred example, the silicon chip is N-shaped or p-type.
In another preferred example, the silicon chip is the monocrystalline silicon piece that resistivity is 0.5-10 Ω cm.
In another preferred example, in step (a), the pressure of vacuum cavity is less than 10-2Torr。
In another preferred example, in step (a), it is 0.5-5 seconds to be passed through the time;Preferably, being 1 second.
In another preferred example, in step (b), it is 10-60 seconds to be passed through the time;Preferably, being 20-35 seconds.
In another preferred example, in step (b), the flow of inert gas is 50-200sccm;Preferably, being 80- 120sccm。
In another preferred example, in step (c), it is 0.5-5 seconds to be passed through the time;Preferably, being 1 second.
In another preferred example, in step (d), it is 10-60 seconds to be passed through the time;Preferably, being 20-35 seconds.
In another preferred example, in step (d), the flow of inert gas is 50-200sccm;Preferably, being 80- 120sccm。
In another preferred example, step (a)-(d) is carried out at 50-500 DEG C.
In another preferred example, step (a)-(d) is carried out at 150-250 DEG C.
In another preferred example, it is repeated in step (a)-(d) 1-200 times.
In another preferred example, it is repeated in step (a)-(d) 1-100 times.
In another preferred example, the precursor molecule containing Ta is selected from the group:Methanol tantalum, ethanol tantalum, propyl alcohol tantalum, isopropanol Tantalum, butanol tantalum, tetraethoxy acetylacetone,2,4-pentanedione tantalum, trifluoroethanol tantalum, tantalic chloride, iodate tantalum, or combinations thereof.
Second aspect of the present invention provides a kind of carrier transport structure, and the carrier transport structure includes or by following Composition:Carrier is passivated tunnel layer and doped polysilicon layer;Wherein, the carrier passivation tunnel layer contains tantalum pentoxide (Ta2O5);The carrier passivation tunnel layer is coated on the surface of silicon chip;The doped polysilicon layer is coated on the load Stream passivation tunnelling layer surface.
In another preferred example, the thickness of the carrier passivation tunnel layer is 0.5-5nm;Preferably, being 1-2.5nm.
In another preferred example, the carrier is electronics or hole.
In another preferred example, the doped polysilicon layer is B-doped Polycrystalline Silicon film or phosphorous doped polysilicon film.
In another preferred example, the thickness of the doped polysilicon layer is 20-100nm;Preferably, being 30-50nm.
In another preferred example, the doped polysilicon layer is phosphorous doped polysilicon film, then the carrier transport structure Selectivity transmission electronics.
In another preferred example, the doped polysilicon layer is B-doped Polycrystalline Silicon film, then the carrier transport structure Selective transporting holes.
Third aspect present invention provides the preparation method of the carrier transport structure described in second aspect of the present invention, described Method includes step:
(a1) it uses PECVD methods to deposit doped amorphous silicon layer in the carrier passivation tunnelling layer surface, then carries out Annealing, to form the carrier transport structure.
In another preferred example, the carrier is passivated the preparation method of tunnel layer as described above.
In another preferred example, the preparation method of the carrier transport structure includes the following steps:Described in being loaded with Carrier is passivated in the vacuum cavity of tunnel layer, is passed through the gas of siliceous precursor molecule and the precursor molecule containing doped chemical Body, to form the amorphous silicon layer containing doped chemical;Amorphous silicon layer containing doped chemical is made annealing treatment, to shape At the carrier transport structure.
In another preferred example, the siliceous precursor molecule is SiH4
In another preferred example, the precursor molecule containing doped chemical is PH3Or B2H6
In another preferred example, the temperature of the annealing is 400-900 DEG C.
In another preferred example, the time of the annealing is 10-40min.
Fourth aspect present invention provides the purposes of the carrier transport structure described in second aspect of the present invention, is used to prepare Solar cell.
In another preferred example, the solar cell is crystal silicon solar energy battery.
Fifth aspect present invention provides a kind of solar cell, and the solar cell includes with lower part:Carrier It is passivated tunnel layer, doped polysilicon layer and electrode layer;Wherein, the carrier passivation tunnel layer contains tantalum pentoxide (Ta2O5);The carrier passivation tunnel layer is coated on the surface of silicon chip;The doped polysilicon layer is coated on the load Stream passivation tunnelling layer surface;The electrode layer is coated on the surface of the doped polysilicon layer.
In another preferred example, the electrode layer segment or it is coated on the surface of the doped polysilicon layer comprehensively.
Sixth aspect present invention provides the preparation method of the solar cell described in fifth aspect present invention, the method Including step:
(a) it uses PECVD methods to deposit doped amorphous silicon layer in the carrier passivation tunnelling layer surface, is then moved back Fire processing, to form the carrier transport structure;With
(b) the carrier transport structure surface depositing electrode layer obtained in step (a), to form the solar-electricity Pond.
In another preferred example, the carrier is passivated the preparation method of tunnel layer as described above.
In another preferred example, further include the load obtained in step (a) before depositing electrode layer in the step (b) It flows and deposits the second passivation layer on the silicon chip front surface emitter of sub- transmission structure.
In another preferred example, the front surface is another surface relative to the silicon chip of passivation tunnel layer.
In another preferred example, second passivation layer is selected from the group:Silicon nitride layer, alumina layer, or combinations thereof.
In another preferred example, when silicon chip front surface emits extremely n+When type, second passivation layer is silicon nitride layer.
In another preferred example, when silicon chip front surface emits extremely p+When type, second passivation layer be silicon nitride layer and Alumina layer.
The present invention also provides the purposes of solar cell of the present invention, are used for photovoltaic generation.
It should be understood that within the scope of the present invention, above-mentioned each technical characteristic of the invention and have in below (eg embodiment) It can be combined with each other between each technical characteristic of body description, to form a new or preferred technical solution.As space is limited, exist This no longer tires out one by one states.
Description of the drawings
Fig. 1 shows TOPCon battery structure schematic diagrames.
Specific implementation mode
The present inventor's in-depth study by extensive by, is surprised to find that for the first time using tantalum pentoxide material as passivation Tunnel layer can overcome for silica as passivation tunnel layer the shortcomings that being passivated in terms of contact heterojunction battery applications. The present invention is completed on the basis of this.
Carrier is passivated tunnelling film
The present invention provides a kind of carriers to be passivated tunnelling film, and the carrier passivation tunnelling film contains five oxidations two Tantalum (Ta2O5);The film is used to prepare the carrier transport structure of solar cell or the present invention.
The solar cell can be crystal silicon solar energy battery.
The thickness of the carrier passivation tunnelling film can be 0.5-5nm;Preferably, being 1-2.5nm.
The carrier can be electronics or hole.
The preparation method of the carrier passivation tunnelling film may include step:Using magnetron sputtering (Sputter), etc. from Daughter enhances chemical vapor deposition (PECVD), thermal evaporation (Thermal Evaporator), electron beam evaporation (E-beam Evaporator), low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) method deposit five oxidations two on silicon chip Tantalum (Ta2O5), it is passivated tunnelling film to form the carrier.
The preparation method of the carrier passivation tunnelling film may include following steps:
(a) in the vacuum cavity for being loaded with silicon chip, the pressure of vacuum cavity is less than 10-2Torr is passed through containing tantalum (Ta) forerunner The gas of body molecule;Wherein, it is 0.5-5 seconds to be passed through the time;Preferably, being 1 second;
(b) it is passed through inert gas;Wherein, it is 10-60 seconds to be passed through the time;Preferably, being 20-35 seconds;The stream of inert gas Amount is 50-200sccm;Preferably, being 80-120sccm;
(c) it is passed through the gas of oxygen-containing (O) precursor molecule;Wherein, it is 0.5-5 seconds to be passed through the time;Preferably, being 1 second;
(d) it is passed through inert gas;Wherein, it is 10-60 seconds to be passed through the time;Preferably, being 20-35 seconds;The stream of inert gas Amount is 50-200sccm;Preferably, being 80-120sccm;
It is passivated tunnelling film to form the carrier.
The inert gas can be selected from the following group:Nitrogen, argon gas or combinations thereof.
Oxygen-containing (O) precursor molecule can be selected from the following group:H2O、O3Or combinations thereof.
The silicon chip is N-shaped or p-type.
The silicon chip is the monocrystalline silicon piece that resistivity is 0.5-10 Ω cm.
Step (a)-(d) is carried out at 50-500 DEG C;Preferably, being carried out at 150-250 DEG C.
Step (a)-(d) 1-200 times can be repeated in;It is repeated in step (a)-(d) 1-100 times.
The precursor molecule containing Ta can be selected from the following group:Methanol tantalum, ethanol tantalum, propyl alcohol tantalum, isopropanol tantalum, butanol tantalum, four Ethoxyacetyl acetone tantalum, trifluoroethanol tantalum, tantalic chloride, iodate tantalum, or combinations thereof.
Carrier transport structure
The present invention provides a kind of carrier transport structure, the carrier transport structure includes or is made up of:It carries Stream passivation tunnel layer and doped polysilicon layer;Wherein, the carrier passivation tunnelling film contains tantalum pentoxide (Ta2O5); The carrier passivation tunnel layer is coated on the surface of silicon chip;The doped polysilicon layer is coated on the carrier passivation Tunnelling layer surface.
The doped polysilicon layer can be B-doped Polycrystalline Silicon film or phosphorous doped polysilicon film.
The thickness of the doped polysilicon layer can be 20-100nm;Preferably, being 30-50nm.
When the doped polysilicon layer is phosphorous doped polysilicon film, then the carrier transport structure selectively transmission is electric Son.
When the doped polysilicon layer is B-doped Polycrystalline Silicon film, then the carrier transport structure selectively transmission is empty Cave.
The preparation method of the carrier transport structure includes step:
(a1) it uses PECVD methods to deposit doped amorphous silicon layer in the carrier passivation tunnelling layer surface, then carries out Annealing, to form the carrier transport structure.
The preparation method of the carrier passivation tunnel layer is as described above.
Specifically, the preparation method of the carrier transport structure may include following steps:It is being loaded with the carrier It is passivated in the vacuum cavity of tunnel layer, is passed through the gas of siliceous precursor molecule and the precursor molecule containing doped chemical, to Form the amorphous silicon layer containing doped chemical;Amorphous silicon layer containing doped chemical is made annealing treatment, described in being formed Carrier transport structure.
The siliceous precursor molecule can be SiH4
The precursor molecule containing doped chemical can be PH3Or B2H6
The temperature of the annealing can be 400-900 DEG C.
The time of the annealing can be 10-40min.
The carrier transport structure of the present invention can be used for preparing solar cell, for example, the solar cell is crystal Silicon solar cell.
Solar cell
The present invention provides a kind of solar cell, the solar cell includes with lower part:Carrier is passivated tunnelling Layer, doped polysilicon layer and electrode layer;Wherein, carrier passivation tunnel layer is coated on the surface of silicon chip;It is described to mix Miscellaneous polysilicon layer is coated on the carrier passivation tunnelling layer surface;The electrode layer is completely or partially coated on the doping The surface of polysilicon layer.
The preparation method of solar cell of the present invention includes step:
(a) it uses PECVD methods to deposit doped amorphous silicon layer in the carrier passivation tunnelling layer surface, is then moved back Fire processing, to form the carrier transport structure;With
(b) the carrier transport structure surface depositing electrode layer obtained in step (a), to form the solar-electricity Pond.
Further include the carrier transport structure obtained in step (a) before depositing electrode layer in the step (b) The second passivation layer is deposited on silicon chip front surface emitter.
Second passivation layer is selected from the group:Silicon nitride layer, alumina layer, or combinations thereof.
When silicon chip front surface emits extremely n+When type, second passivation layer is silicon nitride layer.
When silicon chip front surface emits extremely p+When type, second passivation layer is silicon nitride layer and alumina layer.
The purposes of solar cell of the present invention is used for photovoltaic generation.
Main advantages of the present invention are:
1. tantalum pentoxide has excellent surface inactivating performance as silicon face passivation layer;
2. the conduction band band rank very little between tantalum pentoxide and silicon, when as electron tunneling material, the contact between silicon Potential barrier is very low, has excellent electron tunneling effect.
3. the Valence-band Offsets between tantalum pentoxide and silicon are smaller, when as tunneled holes material, there is relatively low connect Potential barrier is touched, can also realize good tunneled holes effect.
It, completely can be with 4. tantalum pentoxide has an excellent high-temperature stability, compatible existing crystal silicon manufacturing process Silica is substituted as passivation tunneling material.
5. as passivation tunnel layer, for five oxidation two tantalum film than silicon oxide film thickness, film is finer and close, special to impurity Being foreign atom in the polysilicon layers such as B, P has stronger blocking capability, can obtain more preferably passivation effect.
6. five oxidation two tantalum film carries 1012cm-2The fixed negative charge of magnitude is highly suitable as the blunt of p-type crystalline silicon Change tunnel layer.
Present invention will be further explained below with reference to specific examples.It should be understood that these embodiments are merely to illustrate the present invention Rather than it limits the scope of the invention.In the following examples, the experimental methods for specific conditions are not specified, usually according to conventional strip Part, or according to the normal condition proposed by manufacturer.Unless otherwise stated, otherwise percentage and number are weight percent and weight Number.
Experiment material used in following embodiment and reagent can obtain unless otherwise instructed from commercially available channel.
Embodiment 1:
Step (1):Using the p-type monocrystalline silicon piece that resistivity is 2.0 Ω cm as substrate, using atomic layer deposition (ALD) side Method deposits Ta in silicon chip tow sides2O5Film.Specific method:The silicon chip cleaned up with RCA standard technologies is placed into ALD In cavity, chamber pressure is evacuated to 10-2Torr by cavity hereinafter, be heated to 200 DEG C simultaneously.It is first using ethanol tantalum and water as presoma It is first passed through ethanol tantalum steam 1 second, then passes to the nitrogen 30 seconds that flow is 100sccm, be then passed through water vapour 1 second, It is finally passed through the nitrogen 30 seconds that flow is 100sccm, this is a cycle.The processing recycled by 60, you can in silicon Piece surface obtains the Ta of 1.8 ± 0.2nm2O5Film.
Step (2):Using alumina particles as evaporation source, Ta is being made2O5It is steamed with specific mask plate pattern on the surface of film Aluminium electrode is plated, the thickness of aluminium electrode is 1 μm.In sample without Ta2O5Comprehensive aluminium electrode is deposited on the surface of film, aluminium electrode Thickness is 1 μm.
Sample obtained carries out CV tests using Semiconductor Parameter Analyzer, as a result shows Ta2O5Film carries fixed negative electricity Lotus, charge density are -1.2 × 1012cm-2;Ta2O5Interface state density is 8.5 × 10 between silicon9cm-2/eV。
Comparative example 1:
Step (1):Using the p-type monocrystalline silicon piece that resistivity is 2.0 Ω cm as substrate, using hot nitric acid oxidation method (NAOS) SiO is grown in silicon chip tow sides2Film.Specific method:The silicon chip cleaned up with RCA standard technologies is immersed in boiling In concentrated nitric acid (68wt.%), by about 10 minutes, you can obtain the SiO of about 1.8 ± 0.2nm in silicon chip surface2Film.
Step (2):Wherein one side SiO is removed with HF acid vapors2Film.Using alumina particles as evaporation source, SiO is being remained with2It is thin With specific mask plate pattern AM aluminum metallization electrode on the surface of film, the thickness of aluminium electrode is 1 μm.In sample without SiO2Film Comprehensive aluminium electrode is deposited on surface, the thickness of aluminium electrode is 1 μm.
Sample obtained carries out CV tests using Semiconductor Parameter Analyzer, as a result shows SiO2Film carries a small amount of fixed Positive charge, charge density are 5.4 × 1010cm-2;SiO2Interface state density is 8.9 × 10 between silicon10cm-2/eV。
Embodiment 2:
Step (1):Using the p-type monocrystalline silicon piece that resistivity is 2.0 Ω cm as substrate, using atomic layer deposition (ALD) side Method deposits Ta in silicon chip tow sides2O5Film.Specific method is the same as 1 step of embodiment (1)
Step (2):Followed by PECVD methods in double-sided deposition Ta2O5Double-sided deposition boron mixing non-crystal silicon on the sample of film Film.Specific method is:By double-sided deposition Ta2O5The sample of film is transferred in PECVD cavitys, and chamber pressure is evacuated to 10- 5Torr hereinafter, heat the sample to 150 DEG C simultaneously.It is passed through 10sccm high purity silanes (SiH4) and 10sccm diluted in hydrogen second boron Alkane (3%B2H6), radio-frequency power 10W, process pressure 0.4Torr, time 10min, you can to obtain about 40nm on sample surfaces Boron mixing non-crystal silicon thin film.
Step (3):Again by two-sided Ta made above2O5The sample of film and boron mixing non-crystal silicon thin film lamination, is transferred to annealing In stove, in N2Or N2With H2Under the atmosphere of (content 5-30%) gaseous mixture, through 850 DEG C of annealing 30min, make boron mixing non-crystal silicon thin film Crystallization, it is 5 × 10 to form doping concentration19cm-3B-doped Polycrystalline Silicon film.
Sample obtained is tested using Sinton WCT-120 quasi-steady state photoconduction minority carrier lifetime testers, and fitting result is aobvious Presentation surface saturation current density J0For 40~60fA/cm2
Comparative example 2:
Step (1):Using the p-type monocrystalline silicon piece that resistivity is 2.0 Ω cm as substrate, using hot nitric acid oxidation method (NAOS) SiO is grown in silicon chip tow sides2Film.Specific method is the same as 1 step of comparative example (1).
Step (2):Followed by PECVD methods in double-sided deposition SiO2Double-sided deposition boron mixing non-crystal silicon on the sample of film Film.Specific method is the same as 2 step of embodiment (2).
Step (3):Two-sided SiO2The sample of film and boron mixing non-crystal silicon thin film lamination is more forming boron-doping through high annealing Polycrystal silicon film.Specific method is the same as 2 step of embodiment (3).
Sample obtained is tested using Sinton WCT-120 quasi-steady state photoconduction minority carrier lifetime testers, and fitting result is aobvious Presentation surface saturation current density J0For 60~90fA/cm2
Compared to comparative example 2, the sample of embodiment 2, there is lower surface saturation current density, illustrate Ta2O5Film pair P-type crystal silicon has more preferably surface passivation effect.
Embodiment 3:
Step (1):Using the N-shaped monocrystalline silicon piece that resistivity is 1.0 Ω cm as substrate, using atomic layer deposition (ALD) side Method deposits Ta in silicon chip tow sides2O5Film.Specific method is the same as 1 step of embodiment (1).
Step (2):Followed by PECVD methods in double-sided deposition Ta2O5The phosphorus-doped amorphous silicon of double-sided deposition on the sample of film Film.Specific method is:By double-sided deposition Ta2O5The sample of film is transferred in PECVD cavitys, and chamber pressure is evacuated to 10- 5Torr hereinafter, heat the sample to 150 DEG C simultaneously.It is passed through 10sccm high purity silanes (SiH4) and 10sccm diluted in hydrogen phosphine (5%PH3), radio-frequency power 10W, process pressure 0.4Torr, time 10min, you can to obtain about 40nm's on sample surfaces P-doped a-Si: H thin films.
Step (3):Again by two-sided Ta made above2O5The sample of film and P-doped a-Si: H thin films lamination is transferred to annealing In stove, in N2Or N2With H2Under the atmosphere of (content 5-30%) gaseous mixture, through 850 DEG C of annealing 30min, make P-doped a-Si: H thin films Crystallization, it is 2.3 × 10 to form doping concentration20cm-3Phosphorous doped polysilicon film.
Sample obtained is tested using Sinton WCT-120 quasi-steady state photoconduction minority carrier lifetime testers, and fitting result is aobvious Presentation surface saturation current density J0For 10~30fA/cm2
Comparative example 3:
Step (1):Using the N-shaped monocrystalline silicon piece that resistivity is 1.0 Ω cm as substrate, using hot nitric acid oxidation method (NAOS) SiO is grown in silicon chip tow sides2Film.Specific method is the same as 1 step of comparative example (1).
Step (2):The further phosphorus-doped amorphous silicon of double-sided deposition on sample, and anneal and form phosphorous doped polysilicon.Specific side Method is the same as 3 step of embodiment (2) and step (3).
Sample obtained is tested using Sinton WCT-120 quasi-steady state photoconduction minority carrier lifetime testers, and fitting result is aobvious Presentation surface saturation current density J0For 20~40fA/cm2
Compared to comparative example 3, the sample of embodiment 3, there is lower surface saturation current density, illustrate Ta2O5Film pair N-type crystalline silicon has more preferably surface passivation effect.
Embodiment 4:
Step (1):With<100>The p-type solar level monocrystalline silicon piece that crystal orientation, resistivity are 2.0 Ω cm is substrate, through 80 DEG C or so 1-3%KOH solution corrosions 15 minutes, remove surface damage layer, and form random pyramid texture matte.Sample turns The Quartz stove tube for moving to 800 DEG C or so, with the N of 250sccm2It is carrier gas by POCl3Liquid source steam is brought into Quartz stove tube, together When be passed through the O of 100sccm2, through 20 minutes high-temperature process, n is formed in sample surfaces+Type emitter layer.It is removed with 5%HF solution Surface phosphorosilicate glass layer, with HNO3With HF acid mixed solution erosion removal back surfaces n+Type layer.
Step (2):The Ta of 1.8nm or so is deposited by ALD methods in sample back surface2O5Film, specific method is the same as implementation 1 step of example (1).
Step (3):Then, boron mixing non-crystal silicon thin film is deposited in sample back surface using PECVD methods, and through high annealing B-doped Polycrystalline Silicon film is formed, specific method is the same as 2 step of embodiment (2) and step (3).
Step (4):Sample is transferred in PECVD cavitys again, with silane (SiH4) and ammonia (NH3) it is presoma, in sample Product front surface deposited silicon nitride (SiNx:H) film, the thickness and refractive index of film are respectively 80nm and 2.05.
Step (5):Using Argent grain as evaporation source, silver electrode layer is deposited at the sample back side, the thickness of silver electrode layer is 300nm.In sample front surface, with the halftone of electronic silver paste and special pattern, it is respectively 35 μm and 1.0mm thin to print out width Grid silver electrode and main grid silver electrode.Then, sample is sintered about 1.5 minutes in 300-900 DEG C of chain-type sintering furnace, that is, completes The preparation of battery sample.
For last battery sample by solar simulator I-V testers, it is as follows that test obtains electric property:
Open-circuit voltage Short-circuit current density Fill factor Efficiency
660mV 38.9mA/cm2 79.8% 20.5%
Comparative example 4:
Step (1):With<100>The p-type solar level monocrystalline silicon piece that crystal orientation, resistivity are 2.0 Ω cm is substrate, by real It applies 4 step of example (1) same procedure and carries out pyramid matte and n+The preparation of type emitter layer.
Step (2):By the method for hot nitric acid oxidation, the SiO of about 1.8nm is grown in sample surfaces2Film, specific method With 1 step of comparative example (1).
Step (3):Then, boron mixing non-crystal silicon thin film is deposited in sample back surface using PECVD methods, and through high annealing B-doped Polycrystalline Silicon film is formed, specific method is the same as 2 step of embodiment (2) and step (3).
Step (4):Battery sample is completed by subsequent step to prepare, specifically with 4 step of embodiment (4) and step (5).
For last battery sample by solar simulator I-V testers, it is as follows that test obtains electric property:
Open-circuit voltage Short-circuit current density Fill factor Efficiency
636mV 38.6mA/cm2 79.5% 19.5%
Embodiment 5:
Step (1):With<100>The N-shaped solar level monocrystalline silicon piece that crystal orientation, resistivity are 1.0 Ω cm is substrate, through 80 DEG C or so 1-3%KOH solution corrosions 15 minutes, remove surface damage layer, and form random pyramid texture matte.Sample turns The Quartz stove tube for moving to 900 DEG C or so, with the N of 100sccm2It is carrier gas by BBr3Liquid source steam is brought into Quartz stove tube, simultaneously It is passed through the O of 50sccm2, through 30 minutes high-temperature process, p is formed in sample surfaces+Type emitter layer.Surface is removed with 5%HF solution Pyrex layer, with HNO3With HF acid mixed solution erosion removal back surfaces p+Type layer.
Step (2):The Ta of 1.8nm or so is deposited by ALD methods in sample back surface2O5Film, specific method is the same as implementation 1 step of example (1).
Step (3):Then, P-doped a-Si: H thin films are deposited in sample back surface using PECVD methods, and through high annealing Phosphorous doped polysilicon film is formed, specific method is the same as 3 step of embodiment (2) and step (3).
Step (4):Later, sample is placed into ald chamber body, using trimethyl aluminium and water vapour as precursor source, 200 Under DEG C heating temperature, the aluminium oxide (Al of 10nm is deposited in sample front surface2O3) film.
Step (5):Sample is transferred in PECVD cavitys again, with silane (SiH4) and ammonia (NH3) it is presoma, in sample Product front surface deposited silicon nitride (SiNx:H) film, the thickness and refractive index of film are respectively 70nm and 2.05.
Step (6):Battery sample is completed by subsequent step to prepare, specifically with 4 step of embodiment (5).
For last battery sample by solar simulator I-V testers, it is as follows that test obtains electric property:
Open-circuit voltage Short-circuit current density Fill factor Efficiency
672mV 39.2mA/cm2 80.7% 21.3%
Comparative example 5:
Step (1):With<100>The N-shaped solar level monocrystalline silicon piece that crystal orientation, resistivity are 1.0 Ω cm is substrate, by real It applies 5 step of example (1) same procedure and carries out pyramid matte and p+The preparation of type emitter layer.
Step (2):By the method for hot nitric acid oxidation, the SiO of about 1.8nm is grown in sample surfaces2Film, specific method With 1 step of comparative example (1).
Step (3):Then, P-doped a-Si: H thin films are deposited in sample back surface using PECVD methods, and through high annealing Phosphorous doped polysilicon film is formed, specific method is the same as 3 step of embodiment (2) and step (3).
Step (4):Battery sample is completed by subsequent step to prepare, specifically with 5 step of embodiment (4), step (5) and step Suddenly (6).
For last battery sample by solar simulator I-V testers, it is as follows that test obtains electric property:
Open-circuit voltage Short-circuit current density Fill factor Efficiency
661mV 39.1mA/cm2 80.3% 20.8%
From testing above:
1. the interface state density between tantalum pentoxide and silicon is less than 1010cm-2/ eV, and the interface between silica and silicon The density of states is close to 1011cm-2/ eV illustrates there is better surface passivation performance using tantalum pentoxide;
2. the conduction band band rank between tantalum pentoxide and silicon is 0.8eV, it means that when tantalum pentoxide is as electronics tunnel When wearing material, the contact berrier between silicon is very low.By measuring and calculating, the thickness of five oxidation two tantalum film, which need to only arrive, is as thin as 5nm, just It can realize good electron tunneling effect.
3. the Valence-band Offsets between tantalum pentoxide and silicon are 2.3eV, hence it is evident that less than the valence of 4.8eV between silica and silicon Band band rank.When tantalum pentoxide is as tunneled holes material, there is lower contact berrier.By measuring and calculating, when five oxidations two The thickness of tantalum films is down to 2nm, you can realizes good tunneled holes effect.
4. tantalum pentoxide has excellent high-temperature stability, silica can be substituted completely as passivation tunneling material.
5. as passivation tunnel layer, for five oxidation two tantalum film than silicon oxide film thickness, film is finer and close, special to impurity Being foreign atom in the polysilicon layers such as B, P has stronger blocking capability, can obtain more preferably passivation effect.
6. five oxidation two tantalum film carries 1012cm-2The fixed negative charge of magnitude, the passivation tunnel layer as p-type crystalline silicon Superior inactivating performance can be obtained.
In conclusion tantalum pentoxide has many characteristics and advantages, it is that further promoted is passivated the contact heterojunction sun The desired passivation tunneling material of battery efficiency.
All references mentioned in the present invention is incorporated herein by reference, independent just as each document It is incorporated as with reference to such.In addition, it should also be understood that, after reading the above teachings of the present invention, those skilled in the art can To be made various changes or modifications to the present invention, such equivalent forms equally fall within model defined by the application the appended claims It encloses.

Claims (10)

1. a kind of purposes of carrier passivation tunnelling film, which is characterized in that the carrier passivation tunnelling film contains five oxygen Change two tantalum (Ta2O5);The film is used to prepare solar cell.
2. purposes as described in claim 1, which is characterized in that the preparation method of carrier passivation tunnelling film includes: Using magnetron sputtering (Sputter), plasma enhanced chemical vapor deposition (PECVD), thermal evaporation (Thermal Evaporator), electron beam evaporation (E-beam Evaporator), low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) method deposits tantalum pentoxide (Ta on silicon chip2O5), it is passivated tunnelling film to form the carrier.
3. purposes as claimed in claim 2, which is characterized in that the preparation method uses atomic layer deposition (ALD), including such as Lower step:
(a) in the vacuum cavity for being loaded with silicon chip, it is passed through the gas containing tantalum (Ta) precursor molecule;
(b) it is passed through inert gas;
(c) it is passed through the gas of oxygen-containing (O) precursor molecule;
(d) it is passed through inert gas;
It is passivated tunnelling film to form the carrier.
4. purposes as claimed in claim 3, which is characterized in that oxygen-containing (O) precursor molecule is selected from the group:H2O、O3Or A combination thereof.
5. purposes as claimed in claim 3, which is characterized in that the precursor molecule containing Ta is selected from the group:Methanol tantalum, ethyl alcohol Tantalum, propyl alcohol tantalum, isopropanol tantalum, butanol tantalum, tetraethoxy acetylacetone,2,4-pentanedione tantalum, trifluoroethanol tantalum, tantalic chloride, iodate tantalum or its group It closes.
6. a kind of carrier transport structure, which is characterized in that the carrier transport structure includes or is made up of:Carrier It is passivated tunnel layer and doped polysilicon layer;Wherein, the carrier passivation tunnel layer contains tantalum pentoxide (Ta2O5);Described Carrier passivation tunnel layer is coated on the surface of silicon chip;The doped polysilicon layer is coated on the carrier passivation tunnel layer Surface.
7. the preparation method of carrier transport structure as claimed in claim 6, which is characterized in that the method includes the steps:
(a1) it uses PECVD methods to deposit doped amorphous silicon layer in the carrier passivation tunnelling layer surface, then anneals Processing, to form the carrier transport structure.
8. the purposes of carrier transport structure as claimed in claim 6, which is characterized in that be used to prepare solar cell.
9. a kind of solar cell, which is characterized in that the solar cell includes with lower part:Carrier passivation tunnel layer, Doped polysilicon layer and electrode layer;Wherein, the carrier passivation tunnel layer contains tantalum pentoxide (Ta2O5);The load Stream passivation tunnel layer is coated on the surface of silicon chip;The doped polysilicon layer is coated on the carrier passivation tunnel layer table Face;The electrode layer is coated on the surface of the doped polysilicon layer.
10. the preparation method of solar cell as claimed in claim 9, which is characterized in that the method includes the steps:
(a) it uses PECVD methods to deposit doped amorphous silicon layer in the carrier passivation tunnelling layer surface, then carries out at annealing Reason, to form the carrier transport structure;With
(b) the carrier transport structure surface depositing electrode layer obtained in step (a), to form the solar cell.
CN201810195184.XA 2018-03-09 2018-03-09 A kind of passivation tunnel layer material preparation and its application in solar cell Pending CN108389914A (en)

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