CN108389782A - A method of forming ultra low k dielectric layer - Google Patents
A method of forming ultra low k dielectric layer Download PDFInfo
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- CN108389782A CN108389782A CN201810181080.3A CN201810181080A CN108389782A CN 108389782 A CN108389782 A CN 108389782A CN 201810181080 A CN201810181080 A CN 201810181080A CN 108389782 A CN108389782 A CN 108389782A
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- silicon oxycarbide
- layer
- ultra low
- oxycarbide layer
- hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of methods forming ultra low k dielectric layer.Include the following steps：1）Silicon oxycarbide layer is formed by chemical vapour deposition technique on a silicon substrate；2）Photoresist is deposited on the silicon oxycarbide layer, and photoetching agent pattern is formed by photoetching or electron beam exposure；3）The injection of He ions is carried out by the photoetching agent pattern；4）Remove photoetching agent pattern；5）Silicon oxycarbide layer Jing Guo He ion implantings is heat-treated；6）Form the silicon oxycarbide layer with hole；7）Make to have the silicon oxycarbide layer of hole that there is smooth upper surface by chemically mechanical polishing；The present invention does not use the pore-foaming agent of organic matter, reduces organics removal complicated technology；Smaller microcellular structure is formed using ion implanting；It is capable of the distribution of control hole using the cavernous structure of the lattice-like of rule, carries out the distribution of the distribution and hole of control injection ion, further control the dielectric constant of material and improve the quality of ultra low k dielectric layer.
Description
Technical field
The invention belongs to field of semiconductor manufacture, and in particular to a method of forming ultra low k dielectric layer.
Background technology
With the development of semiconductor technology, the concentration degree of integrated circuit increases, for reduce capacitance resistance delay effect, two
Dielectric layer between layer metal interconnection structure requires have lower dielectric constant,
In the prior art, the silica that dielectric substance is 4 or so from dielectric constant, it is 3.7 or so to be transitioned into dielectric constant
Fluorine silica glass, then the silicon oxide carbide that dielectric constant is 3 or so is arrived, then arrive the ultra low k dielectric material with certain hole.At present
Ultra low k dielectric material is formed, on a semiconductor substrate deposit dielectric barrier layer and the low dielectric layer containing pore-foaming agent,
Then with the pore-foaming agent of removal low-dielectric constant layer, the low-dielectric constant layer of micropore is formed.Control pore-foaming agent is uniformly distributed, and is used
The technics comparing that ultraviolet light irradiates pore-foaming agent is complicated, meanwhile, known from experience using oxygen plasma and forms one layer of cause on silicon oxide carbide surface
Close silicon oxide layer is unfavorable for the discharge of pore-foaming agent.
Invention content
Based on solving the above problems, the present invention provides a kind of methods forming ultra low k dielectric layer.Including walking as follows
Suddenly：1）Silicon oxycarbide layer is formed by chemical vapour deposition technique on a silicon substrate；2）Photoetching is deposited on the silicon oxycarbide layer
Glue forms photoetching agent pattern by photoetching or electron beam exposure；3）The injection of He ions is carried out by the photoetching agent pattern；4）
Remove photoetching agent pattern；5）Silicon oxycarbide layer Jing Guo He ion implantings is heat-treated；6）Form the carbon oxygen with hole
SiClx layer；7）Make to have the silicon oxycarbide layer of hole that there is smooth upper surface by chemically mechanical polishing.
The present invention also provides another methods for forming ultra low k dielectric layer.Include the following steps：1）On a silicon substrate
Silicon oxycarbide layer is formed by chemical vapour deposition technique；2）Photoresist is deposited on the silicon oxycarbide layer passes through photoetching or electronics
Beam exposes to form photoetching agent pattern；3）H is carried out by the photoetching agent pattern+With the injection of He ions；4）Remove photoresist figure
Case；5）Silicon oxycarbide layer Jing Guo He ion implantings is heat-treated；6）Form the silicon oxycarbide layer with hole；7）Pass through
Chemically mechanical polishing makes to have the silicon oxycarbide layer of hole to have smooth upper surface.
According to an embodiment of the invention, the step 1）Described in formed silicon oxycarbide layer unstrpped gas be CH4、O2With
SiH4；It is formed in silicon oxycarbide layer, the ratio of carbon and oxygen element is 1:1~2:Between 1.
According to an embodiment of the invention, the step 2）The middle pattern for forming photoresist is the poroid knot of the lattice-like of rule
Structure, thickness are more than 1.5 μm.
According to an embodiment of the invention, the step 3）The energy of middle He ion implantings is 20 ~ 150KeV, the dosage of injection
More than 5 × 1016。
According to an embodiment of the invention, the step 5）The temperature of middle heat treatment is 400-600 DEG C, and the time of heat treatment is
0.5 ~ 1.5 hour.
According to an embodiment of the invention, the also described step 6）The dielectric constant for forming ultra low k dielectric layer later is less than
2.5。
According to an embodiment of the invention, the also described step 6）The dielectric constant for forming ultra low k dielectric layer later is less than
2.3。
Advantages of the present invention is as follows：
（1）Without using the pore-foaming agent of organic matter, organics removal complicated technology is reduced；
（2）Smaller microcellular structure is formed using ion implanting；
（3）It is capable of the distribution of control hole using the cavernous structure of the lattice-like of rule, carries out distribution and the hole of control injection ion
Distribution.
Description of the drawings
Fig. 1 is the method and process figure to form ultra low k dielectric layer.
1：Silicon substrate；2：Silicon oxycarbide layer；3：Photoetching agent pattern；4：Hole；5：Inject ion, H+Ion, He ions, H+From
Son and He ions；6：Injection zone；7：Porous silicon oxide carbide.
Specific implementation mode
First embodiment
Referring to Fig. 1, the method for forming ultra low k dielectric layer.Include the following steps：In Fig. 1（a）It is shown, step 1）It is served as a contrast in silicon
Silicon oxycarbide layer 2 is formed by chemical vapour deposition technique on bottom 1；Unstrpped gas at silicon oxycarbide layer is CH4、O2And SiH4；Shape
At in silicon oxycarbide layer 2, the ratio of carbon and oxygen element is 1:1~2:Between 1；In Fig. 1（b）It is shown, step 2）Described
Photoresist is deposited on silicon oxycarbide layer 2, and photoetching agent pattern 3 is formed by photoetching or electron beam exposure；Form the pattern 3 of photoresist
Thickness for the cavernous structure of the lattice-like of rule, photoetching agent pattern is more than 1.5 μm；The poroid knot of the lattice-like of the rule
Structure, the size in the dot matrix hole 4 is between 2-5 μm；The 30%- of the gross area described in the area point photoetching agent pattern in the dot matrix hole 4
Between 50%；In Fig. 1（c）It is shown, step 3）The injection of He ions 5 is carried out by the photoetching agent pattern；He ions 5 inject
Energy be 20 ~ 150KeV, the dosage of injection is more than 5 × 1016, form injection region 6；In Fig. 1（d）It is shown, step 4）Removal
Wet etching removal or Oxygen plasma ashing may be used in photoetching agent pattern 3, the method for removing photoetching agent pattern；In Fig. 1
（e）It is shown, step 5）Silicon oxycarbide layer Jing Guo He ion implantings is heat-treated；The temperature of heat treatment is 400-600 DEG C,
The time of heat treatment is 0.5 ~ 1.5 hour；Step 6）Form the silicon oxycarbide layer 7 with hole；7）Pass through chemically mechanical polishing
Make to have the silicon oxycarbide layer of hole that there is smooth upper surface.By the step 7）Ultra low k dielectric layer is formed later
Dielectric constant is less than 2.5.
Second embodiment
Referring to Fig. 1, the method for forming ultra low k dielectric layer.Include the following steps：In Fig. 1（a）It is shown, step 1）It is served as a contrast in silicon
Silicon oxycarbide layer 2 is formed by chemical vapour deposition technique on bottom 1；Unstrpped gas at silicon oxycarbide layer is CH4、O2And SiH4；Shape
At in silicon oxycarbide layer 2, the ratio of carbon and oxygen element is 1:1~2:Between 1；In Fig. 1（b）It is shown, step 2）Described
Photoresist is deposited on silicon oxycarbide layer 2, and photoetching agent pattern 3 is formed by photoetching or electron beam exposure；Form the pattern 3 of photoresist
Thickness for the cavernous structure of the lattice-like of rule, photoetching agent pattern is more than 1.5 μm；The poroid knot of the lattice-like of the rule
Structure, the size in the dot matrix hole 4 is between 2-5 μm；The 30%- of the gross area described in the area point photoetching agent pattern in the dot matrix hole
Between 50%；In Fig. 1（c）It is shown, step 3）H is carried out by the photoetching agent pattern+With the injection of He ions 5；H+With He from
The energy of 5 injection of son is 20 ~ 150KeV, and the dosage of injection is more than 5 × 1016, H can be injected simultaneously+With He ions, or first inject
H+He ions are reinjected after ion, and H is reinjected after preferably first injecting He ions+Ion forms injection region 6；In Fig. 1（d）Institute
Show, step 4）Photoetching agent pattern 3 is removed, wet etching removal or oxygen plasma may be used in the method for removing photoetching agent pattern
Body is ashed；In Fig. 1（e）It is shown, step 5）To passing through H+It is heat-treated with the silicon oxycarbide layer of He ion implantings；Heat treatment
Temperature be 400-600 DEG C, time of heat treatment is 0.5 ~ 1.5 hour；Step 6）Form the silicon oxycarbide layer 7 with hole；
7）Make to have the silicon oxycarbide layer of hole that there is smooth upper surface by chemically mechanical polishing.By the step 7）Shape later
It is less than 2.3 at the dielectric constant of ultra low k dielectric layer.
3rd embodiment
Ultra low k dielectric layer is formed according to the method for implementing one or two ultra low k dielectric layer of embodiment, and uses Cu as metal
Layer forms the interconnection architecture and dielectric layer of chip or integrated circuit.Compared to traditional Cu, silica system, response is improved
Speed.Compared to using pore-foaming agent to prepare ultra low k dielectric layer process, reduce organics removal complicated technology, using He and/
Or H+Ion is assembled to form stomata, can generate smaller and microcellular structure, and stomata is controlled by controlling the size of injection rate
Quantity is capable of the distribution of control hole using the cavernous structure of the lattice-like of rule, carries out controlling the distribution and hole for injecting ion
Distribution further controls the dielectric constant of material and improves the quality of ultra low k dielectric layer.
Finally it should be noted that：Obviously, the above embodiment is merely an example for clearly illustrating the present invention, and simultaneously
The non-restriction to embodiment.For those of ordinary skill in the art, it can also do on the basis of the above description
Go out other various forms of variations or variation.There is no necessity and possibility to exhaust all the enbodiments.And thus drawn
The obvious changes or variations that Shen goes out are still in the protection scope of this invention.
Claims (7)
1. a kind of method forming ultra low k dielectric layer, which is characterized in that include the following steps：1）Passing through on a silicon substrate
It learns vapour deposition process and forms silicon oxycarbide layer；2）Photoresist is deposited on the silicon oxycarbide layer passes through photoetching or electron beam exposure
Form photoetching agent pattern；3）The injection of He ions is carried out by the photoetching agent pattern；4）Remove photoetching agent pattern；5）To passing through
The silicon oxycarbide layer of He ion implantings is heat-treated；6）Form the silicon oxycarbide layer with hole；7）It is thrown by chemical machinery
Light makes to have the silicon oxycarbide layer of hole to have smooth upper surface；
Wherein, the step 1）Described in formed silicon oxycarbide layer unstrpped gas be CH4、O2And SiH4；Form silicon oxycarbide layer
In, the ratio of carbon and oxygen element is 1:1~2:Between 1；The step 2）The middle pattern for forming photoresist is the dot matrix of rule
The cavernous structure of shape, thickness are more than 1.5 μm；The step 3）The energy of middle He ion implantings is 20 ~ 150KeV, the agent of injection
Amount is more than 5 × 1016；The step 5）The temperature of middle heat treatment is 400-600 DEG C, and the time of heat treatment is 0.5 ~ 1.5 hour；Through
Cross the step 7）The dielectric constant for forming ultra low k dielectric layer later is less than 2.5.
2. the method according to claim 1 for forming ultra low k dielectric layer, the cavernous structure of the lattice-like of the rule,
The size in the dot matrix hole is between 2-5 μm.
3. the method according to claim 1 for forming ultra low k dielectric layer, the cavernous structure of the lattice-like of the rule,
Between the 30%-50% of the gross area described in the area point photoetching agent pattern in the dot matrix hole.
4. a kind of method forming ultra low k dielectric layer, which is characterized in that include the following steps：1）Passing through on a silicon substrate
It learns vapour deposition process and forms silicon oxycarbide layer；2）Photoresist is deposited on the silicon oxycarbide layer passes through photoetching or electron beam exposure
Form photoetching agent pattern；3）H is carried out by the photoetching agent pattern+With the injection of He ions；4）Remove photoetching agent pattern；5）It is right
Silicon oxycarbide layer by He ion implantings is heat-treated；6）Form the silicon oxycarbide layer with hole；7）Pass through chemical machine
Tool polishing makes to have the silicon oxycarbide layer of hole to have smooth upper surface；
Wherein, the step 1）Described in formed silicon oxycarbide layer unstrpped gas be CH4、O2And SiH4；Form silicon oxycarbide layer
In, the ratio of carbon and oxygen element is 1:1~2:Between 1；The step 2）The middle pattern for forming photoresist is the dot matrix of rule
The cavernous structure of shape, thickness are more than 1.5 μm；The step 3）Middle H+Energy with He ion implantings is 20 ~ 150KeV, injection
Dosage be more than 5 × 1016；The step 5）The temperature of middle heat treatment is 400-600 DEG C, and the time of heat treatment is 0.5 ~ 1.5 small
When；By the step 7）The dielectric constant for forming ultra low k dielectric layer later is less than 2.3.
5. the method according to claim 4 for forming ultra low k dielectric layer, wherein reinject H after first injecting He ions+From
Son.
6. the method according to claim 4 for forming ultra low k dielectric layer, the cavernous structure of the lattice-like of the rule,
The size in the dot matrix hole is between 2-5 μm.
7. the method according to claim 4 for forming ultra low k dielectric layer, the cavernous structure of the lattice-like of the rule,
Between the 30%-50% of the gross area described in the area point photoetching agent pattern in the dot matrix hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810181080.3A CN108389782B (en) | 2018-03-06 | 2018-03-06 | Method for forming ultra-low K dielectric layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810181080.3A CN108389782B (en) | 2018-03-06 | 2018-03-06 | Method for forming ultra-low K dielectric layer |
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| CN108389782A true CN108389782A (en) | 2018-08-10 |
| CN108389782B CN108389782B (en) | 2020-02-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112670176A (en) * | 2019-10-16 | 2021-04-16 | 菏泽学院 | Preparation method of nano porous carbon silicon oxide film and film |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437226A (en) * | 2002-02-05 | 2003-08-20 | 台湾积体电路制造股份有限公司 | Manufacture of carbon-containing dielectric layer |
| CN1454394A (en) * | 2000-08-02 | 2003-11-05 | 国际商业机器公司 | Multiphase low dielectric constant material and method of deposition |
| CN1697176A (en) * | 2004-05-11 | 2005-11-16 | 中芯国际集成电路制造(上海)有限公司 | Thin film in low dielectric constant and fabricating method |
| CN1754252A (en) * | 2003-02-26 | 2006-03-29 | 陶氏康宁公司 | Method for producing hydrogenated silicon oxycarbide films |
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2018
- 2018-03-06 CN CN201810181080.3A patent/CN108389782B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1454394A (en) * | 2000-08-02 | 2003-11-05 | 国际商业机器公司 | Multiphase low dielectric constant material and method of deposition |
| CN1437226A (en) * | 2002-02-05 | 2003-08-20 | 台湾积体电路制造股份有限公司 | Manufacture of carbon-containing dielectric layer |
| CN1754252A (en) * | 2003-02-26 | 2006-03-29 | 陶氏康宁公司 | Method for producing hydrogenated silicon oxycarbide films |
| CN1697176A (en) * | 2004-05-11 | 2005-11-16 | 中芯国际集成电路制造(上海)有限公司 | Thin film in low dielectric constant and fabricating method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112670176A (en) * | 2019-10-16 | 2021-04-16 | 菏泽学院 | Preparation method of nano porous carbon silicon oxide film and film |
| CN112670176B (en) * | 2019-10-16 | 2022-10-21 | 菏泽学院 | Preparation method of nano porous carbon silicon oxide film and film |
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