CN108376677B - Opposite side cascade semiconductor chip device and cascade method - Google Patents
Opposite side cascade semiconductor chip device and cascade method Download PDFInfo
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- CN108376677B CN108376677B CN201810201679.9A CN201810201679A CN108376677B CN 108376677 B CN108376677 B CN 108376677B CN 201810201679 A CN201810201679 A CN 201810201679A CN 108376677 B CN108376677 B CN 108376677B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
Abstract
The invention discloses a device and a method for cascading semiconductor chips in opposite sides, wherein the device comprises: the insulating substrate is provided with a first through hole; the first semiconductor chip and the second semiconductor chip are respectively assembled on two sides of the insulating substrate; the first semiconductor chip is provided with a second through hole, the second semiconductor chip is provided with a third through hole, and the first through hole, the second through hole and the third through hole form a complete through hole after the assembly is finished; the first through hole, the second through hole and the third through hole are provided with metalized side walls; and filling the whole through hole and sintering the formed conductive filler. According to the invention, a semiconductor process is adopted, the metalized side wall is processed and the corresponding position is assembled, and the conductive filler is filled in the through hole, so that the two chips are cascaded on two sides of the same substrate, the packaging space is effectively saved, and the risk of introducing a bond wire is effectively avoided.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a device and a method for cascading opposite side cascaded semiconductor chips.
Background
With the continuous progress of science and technology, the demand of people is increasingly raised, and the requirements on semiconductor chips are higher and higher. Meanwhile, as the demand of people is increased, although a single chip is more and more complex in structure, function and integration level, the chip is limited by factors such as material and basic physical theory, and a plurality of chips with different types and different functions are often required to be cascaded, for example, a radio frequency front end chip which is widely used at present needs a plurality of chips such as a switch chip, a power amplification chip and a low noise chip to be cascaded from the viewpoint of architecture.
At present, the microwave radio frequency chip adopts the mode of metal bond line (bonding line) to cascade more, has a great deal of drawback:
(1) bond line reliability is at risk: for automatic machine bond line at present, because the bond line is mostly unsettled, in-service use, there are contact such as bond line and encapsulation material, lead to signal leakage and the cracked risk of bond line.
(2) The bond wire approach introduces some insertion loss, affecting high frequency performance: generally, a bond wire contains resistance and inductance in a microwave equivalent circuit, and influences high-frequency characteristics, particularly a millimeter wave frequency band.
Therefore, a new device and method for cascade connection at opposite sides are needed to avoid the risk of introducing the bond line, so that the chip cascade connection effect is better.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a device for cascading semiconductor chips on the opposite side and a cascading method, and solves the problem of leading in a bond wire in the prior art.
The purpose of the invention is realized by the following technical scheme: a pair of side-cascade semiconductor chip devices, comprising:
the insulating substrate is provided with a first through hole;
the first semiconductor chip and the second semiconductor chip are respectively assembled on two sides of the insulating substrate; the first semiconductor chip is provided with a second through hole, the second semiconductor chip is provided with a third through hole, and the first through hole, the second through hole and the third through hole form a complete through hole after the assembly is finished; the first through hole, the second through hole and the third through hole are provided with metalized side walls;
and filling the whole through hole and sintering the formed conductive filler.
Further, before being assembled to the insulating substrate, the surfaces of the first semiconductor chip and the second semiconductor chip are coated with photoresist, a pattern to be etched is formed by adopting a photoetching process, exposure and development are completed, and through hole position definition is realized; etching a second through hole on the first semiconductor chip and etching a third through hole on the second semiconductor chip by adopting an etching process; and after the conductive filler is filled and sintered and molded, removing the photoresist.
Further, the conductive filler is nano silver paste.
Further, the sintering temperature of the nano silver paste is less than or equal to 130 ℃.
Further, before the insulating substrate is assembled, a first through hole is formed in the insulating substrate by means of dry etching or laser drilling.
Furthermore, the size of the first through hole is larger than that of the second through hole and that of the third through hole.
Further, the material of the metalized sidewall comprises Au, Cu, Ti, Pt and a combination thereof.
The invention also provides a method for cascading opposite side cascaded semiconductor chips, which comprises the following steps:
s01: respectively forming metalized side walls for the first through hole of the insulating substrate, the second through hole of the first semiconductor chip and the third through hole of the second semiconductor chip by adopting a sputtering process;
s02: respectively assembling the first semiconductor chip and the second semiconductor chip on two sides of the insulating substrate at positions corresponding to the through holes, wherein the three assembled through holes form a complete through hole;
s03: and filling a conductive filler in the complete through hole, and sintering and molding.
Further, the method also comprises a through hole manufacturing step of the insulating substrate, a through hole manufacturing step of the semiconductor chip and a photoresist removing step; wherein the through-hole manufacturing step of the insulating substrate and the through-hole manufacturing step of the semiconductor chip are performed before step S01, and the photoresist removing step is performed after step S03;
the manufacturing steps of the insulating substrate through hole comprise: manufacturing a first through hole on the insulating substrate by adopting a dry etching or laser drilling mode;
the manufacturing step of the semiconductor chip through hole comprises the following substeps:
s001: respectively coating photoresist on the surfaces of a first semiconductor chip and a second semiconductor chip to be cascaded, forming a pattern to be etched by adopting a photoetching process, completing exposure and development, and defining the positions of a second through hole and a third through hole;
s002: manufacturing a second through hole on the first semiconductor chip to be cascaded and manufacturing a third through hole on the second semiconductor chip to be cascaded by adopting an etching process;
the photoresist removing step comprises: and removing the photoresist.
Furthermore, the conductive filler is nano silver paste, and the photoresist is not damaged by the sintering molding temperature.
The invention has the beneficial effects that:
(1) according to the invention, a semiconductor process is adopted, the metalized side wall is processed and the corresponding position is assembled, and the conductive filler is filled in the through hole, so that the two chips are cascaded on two sides of the same substrate, the packaging space is effectively saved, and the risk of introducing a bond wire is effectively avoided.
(2) The invention also provides a manufacturing method of the semiconductor chip through hole and the insulating substrate through hole, which comprises the steps of manufacturing a new through hole for the semiconductor chip without the through hole and the insulating substrate, manufacturing a new through hole for the semiconductor chip with the existing through hole and the insulating substrate, processing the through hole by adopting semiconductor processes such as photoetching, ICP-RIE and the like, has the advantages of high precision, good repeatability and the like, and is particularly suitable for high-frequency and mass production.
(3) According to the invention, the nano silver paste is used as a conductive filler, when the material reaches a nano level, the material has very high surface activity and surface energy, the sintering temperature is far lower than that of a block material, and the material formed after solidification has physical and electrical properties similar to those of the block. Because the metal silver has good heat conductivity, electric conductivity and corrosion resistance, the nano silver paste can be sintered at low temperature and can be used at high temperature, so that the temperature in the manufacturing process is not high, the requirement on processing when photoresist is arranged on a semiconductor chip is met, and the photoresist cannot be damaged. Meanwhile, the photoresist is removed at last, which is beneficial to preventing the surface of the semiconductor chip from being polluted by the nano silver paste.
Drawings
FIG. 1 is a schematic side view of the apparatus of the present invention;
FIG. 2 is a schematic top view of the apparatus of the present invention;
FIG. 3 is a flow chart of the method of the present invention;
fig. 4 is a schematic view illustrating the insulating substrate is fabricated with a first via in step S00;
FIG. 5 is a schematic illustration of a semiconductor chip prior to processing;
fig. 6 is a schematic diagram illustrating the definition of the second through hole and the third through hole in step S001;
fig. 7 is a schematic view of the completion of the second through-hole and the three pupils in step S002;
fig. 8 is an assembled side view in step S02;
fig. 9 is a top view of the assembled state in step S02;
in the figure, 1-an insulating substrate, 2-a first semiconductor chip, 3-a second semiconductor chip, 4-a conductive filler, 5-a first via, 6-a photoresist, 7-a second via, 8-a third via, 9-a complete via.
Detailed Description
The technical scheme of the invention is further described in detail by combining the attached drawings:
as shown in fig. 1 and 2, a pair of side-cascade semiconductor chip apparatus includes:
the structure comprises an insulating substrate 1, wherein a first through hole 5 is formed in the insulating substrate 1;
a first semiconductor chip 2 and a second semiconductor chip 3 respectively assembled on both sides of the insulating substrate 1; the first semiconductor chip 2 is provided with a second through hole 7, the second semiconductor chip 3 is provided with a third through hole 8, and the first through hole 5, the second through hole 7 and the third through hole 8 form a complete through hole 9 after assembly; the first through hole 5, the second through hole 7 and the third through hole 8 are provided with metalized side walls;
filling the complete through hole 9 and sintering the molded conductive filler 4.
In this embodiment, the semiconductor chip may be any one or more of a switch chip, a power amplifier chip, and a low noise chip, and is selected according to an actual input-output relationship.
Preferably, in this embodiment, before being assembled to the insulating substrate 1, the surfaces of the first semiconductor chip 2 and the second semiconductor chip 3 are coated with the photoresist 6, and a pattern to be etched is formed by a photolithography process, and exposure and development are completed to define the position of the through hole; then, etching a second through hole 7 on the first semiconductor chip 2 and a third through hole 8 on the second semiconductor chip 3 by adopting an etching process; after the conductive filler 4 is filled and sintered to be molded, the photoresist 6 is removed. Preferably, the thickness of the photoresist 6 is more than or equal to 5 um.
If the photoresist 6 is taken out immediately after the second through hole 7 and the third through hole 8 are etched, and then the nano silver paste is filled (in a preferred embodiment described below), the nano silver paste is colloidal, so that the surface of the chip is polluted by the nano silver paste, and if a SiN passivation layer is not formed on the surface of the chip, the chip is directly failed. The step can not only realize the processing of the through hole, but also protect the surface of the semiconductor chip without a passivation layer, and the pollution of the nano silver paste to the surface of the semiconductor chip is avoided.
Preferably, in this embodiment, the conductive filler 4 is a nano silver paste. Among them, nano silver has been widely used in chip fabrication due to its excellent electrical characteristics. The scientific research of the material shows that when the material reaches the nanometer level, the material has very high surface activity and surface energy, the sintering temperature is far lower than that of a block material, and the material formed after solidification has physical and electrical properties similar to those of the block. Because the metal silver has good thermal conductivity, electrical conductivity and corrosion resistance, the nano silver paste is consistently the hotter material to be researched. The nano silver paste is mainly characterized by low-temperature sintering and high-temperature service.
More preferably, in this embodiment, the sintering temperature of the nano silver paste is less than or equal to 130 ℃, and the temperature is such that the photoresist 6 is not damaged.
More preferably, in the present embodiment, the first through hole 5 is formed in the insulating substrate 1 by dry etching or laser drilling before the insulating substrate 1 is assembled.
Preferably, in the present embodiment, the size of the first through hole 5 is larger than that of the second through hole 7 and the third through hole 8, so as to facilitate the subsequent alignment assembly.
Meanwhile, preferably, the shape of the first through hole 5 is the same as the second through hole 7 and the third through hole 8, the size of the second through hole 7 is the same as the size of the third through hole 8, the size of the first through hole 5 is at least 200um larger than the second through hole 7 and the third through hole 8, the single-side size of the second through hole 7 and the third through hole 8 is larger than 200um, and the shape is not limited.
Preferably, in the present embodiment, the material of the metalized sidewall includes Au, Cu, Ti, Pt, and a combination thereof. Specifically, the metalized side wall can solve the problems of adhesion and adhesiveness, (1) the problem of adhesion exists due to different structures of metal and semiconductor crystal types, namely if the nano silver paste is directly filled into a through hole without the metalized side wall, the adhesion is not enough due to the fact that the structure of the semiconductor and the nano silver paste of the metal is different outside the outer surface of the through hole, and the filled nano silver paste is in a falling risk after being cured; when a layer of metalized side wall is attached, the metalized side wall and the nano silver paste are both metal after being solidified, have the same structure and are easy to attach (the metal and the metal are tightly adhered at high temperature). (2) Meanwhile, the metalized side wall of the present application is preferably sputtered to the through hole, because the sputtering energy is large and the adhesion is good.
As shown in fig. 3, the present invention further provides a method for cascading opposite side cascaded semiconductor chips, comprising the following steps:
s00: manufacturing a through hole of an insulating substrate 1 and a through hole of a semiconductor chip;
the steps of manufacturing the through hole of the insulating substrate 1 comprise: manufacturing a first through hole 5 on the insulating substrate 1 by adopting a dry etching or laser drilling mode, as shown in fig. 4;
the steps of manufacturing the semiconductor chip through hole comprise: s001: respectively coating photoresist 6 on the surfaces of a first semiconductor chip 2 and a second semiconductor chip 3 (shown in fig. 5) to be cascaded, forming a pattern to be etched by adopting a photoetching process, and completing exposure and development to define the positions of a second through hole 7 and a third through hole 8, as shown in fig. 6; s002: by means of an etching process, a second via 7 is produced in the first semiconductor chip 2 to be cascaded and a third via 8 is produced in the second semiconductor chip 3 to be cascaded, as shown in fig. 7.
In the embodiment, the thickness of the photoresist 6 is more than or equal to 5 um; the shape of first through-hole 5 all is the same with second through-hole 7 and third through-hole 8, and the size of second through-hole 7 is the same with third through-hole 8, and the size of first through-hole 5 is bigger than second through-hole 7 and third through-hole 8 by at least 200um (be convenient for follow-up alignment assembly), and the unilateral size of second through-hole 7 and third through-hole 8 is greater than 200um to do not limit the shape.
S01: by adopting a sputtering process, metalized side walls are respectively formed on the first through hole 5 of the insulating substrate 1, the second through hole 7 of the first semiconductor chip 2 and the third through hole 8 of the second semiconductor chip 3, so that the conductive filler 4 (in the embodiment, nano silver paste) can be filled conveniently; among these, metals include, but are not limited to, Au, Cu, Ti, Pt, and combinations thereof.
S02: the first semiconductor chip 2 and the second semiconductor chip 3 are assembled on both sides of the insulating substrate 1 at positions corresponding to through holes, respectively, wherein the three through holes completed in the assembly form one complete through hole 9, as shown in fig. 8 and 9.
S03: filling a conductive filler 4 in the complete through hole 9, and sintering and molding; in this embodiment, the conductive filler 4 is a nano silver paste, and the photoresist 6 is not damaged by the sintering temperature (less than or equal to 130 ℃).
S04: and removing the photoresist 6 to obtain a first semiconductor chip 2 and a second semiconductor chip 3, and realizing cascade connection on two sides of the insulating substrate 1, as shown in fig. 1 and 2.
Among them, steps S00 and S04 are preferable steps for making new through holes for the semiconductor chip and the insulating substrate 1 (including making new through holes for the semiconductor chip and the insulating substrate 1 without through holes, and making new through holes for the semiconductor chip and the insulating substrate 1 with existing through holes).
While the present invention has been described by way of examples, and not by way of limitation, other variations of the disclosed embodiments, as would be readily apparent to one of skill in the art, are intended to be within the scope of the present invention, as defined by the claims.
Claims (9)
1. An opposite side cascade semiconductor chip device, characterized in that: the method comprises the following steps:
the insulating substrate is provided with a first through hole;
the first semiconductor chip and the second semiconductor chip are respectively assembled on two sides of the insulating substrate; the first semiconductor chip is provided with a second through hole, the second semiconductor chip is provided with a third through hole, and the first through hole, the second through hole and the third through hole form a complete through hole after the assembly is finished; the first through hole, the second through hole and the third through hole are provided with metalized side walls;
the conductive filler is filled into the complete through hole and is sintered and molded;
the conductive filler is nano silver paste.
2. A pair of side-by-side cascaded semiconductor chip devices according to claim 1, wherein: before the first semiconductor chip and the second semiconductor chip are assembled to the insulating substrate, photoresist is coated on the surfaces of the first semiconductor chip and the second semiconductor chip, a pattern to be etched is formed by adopting a photoetching process, exposure and development are completed, and through hole position definition is realized; etching a second through hole on the first semiconductor chip and etching a third through hole on the second semiconductor chip by adopting an etching process; and after the conductive filler is filled and sintered and molded, removing the photoresist.
3. A pair of side-by-side cascaded semiconductor chip devices according to claim 1, wherein: the sintering temperature of the nano silver paste is less than or equal to 130 ℃.
4. A pair of side-by-side cascaded semiconductor chip devices according to claim 1, wherein: before the insulating substrate is assembled, a first through hole is manufactured on the insulating substrate in a dry etching or laser drilling mode.
5. A pair of side-by-side cascaded semiconductor chip devices according to claim 1, wherein: the size of the first through hole is larger than that of the second through hole and that of the third through hole.
6. A pair of side-by-side cascaded semiconductor chip devices according to claim 1, wherein: the material of the metalized side wall comprises Au, Cu, Ti, Pt and a combination thereof.
7. A method for cascading opposite side cascaded semiconductor chips is characterized in that: the method comprises the following steps:
s01: respectively forming metalized side walls for the first through hole of the insulating substrate, the second through hole of the first semiconductor chip and the third through hole of the second semiconductor chip by adopting a sputtering process;
s02: respectively assembling the first semiconductor chip and the second semiconductor chip on two sides of the insulating substrate at positions corresponding to the through holes, wherein the three assembled through holes form a complete through hole;
s03: filling conductive filler in the complete through hole, and sintering and molding;
the conductive filler is nano silver paste.
8. The method of claim 7, wherein: the method also comprises a through hole manufacturing step of the insulating substrate, a through hole manufacturing step of the semiconductor chip and a photoresist removing step; wherein the through-hole manufacturing step of the insulating substrate and the through-hole manufacturing step of the semiconductor chip are performed before step S01, and the photoresist removing step is performed after step S03;
the manufacturing steps of the insulating substrate through hole comprise: manufacturing a first through hole on the insulating substrate by adopting a dry etching or laser drilling mode;
the manufacturing step of the semiconductor chip through hole comprises the following substeps:
s001: respectively coating photoresist on the surfaces of a first semiconductor chip and a second semiconductor chip to be cascaded, forming a pattern to be etched by adopting a photoetching process, completing exposure and development, and defining the positions of a second through hole and a third through hole;
s002: manufacturing a second through hole on the first semiconductor chip to be cascaded and manufacturing a third through hole on the second semiconductor chip to be cascaded by adopting an etching process;
the photoresist removing step comprises: and removing the photoresist.
9. The method of claim 8, wherein: the photoresist is not damaged by the sintering and forming temperature.
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| CN201810201679.9A CN108376677B (en) | 2018-03-12 | 2018-03-12 | Opposite side cascade semiconductor chip device and cascade method |
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| CN201810201679.9A CN108376677B (en) | 2018-03-12 | 2018-03-12 | Opposite side cascade semiconductor chip device and cascade method |
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| CN108376677B true CN108376677B (en) | 2020-04-21 |
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| CN1164765A (en) * | 1996-03-06 | 1997-11-12 | 现代电子产业株式会社 | Semiconductor package |
| CN102024782A (en) * | 2010-10-12 | 2011-04-20 | 北京大学 | Three-dimensional vertical interconnecting structure and manufacturing method thereof |
| CN106648210A (en) * | 2016-10-19 | 2017-05-10 | 合肥鑫晟光电科技有限公司 | Display panel and preparation method thereof, display device |
| US9773751B1 (en) * | 2016-06-29 | 2017-09-26 | International Business Machines Corporation | Via and trench filling using injection molded soldering |
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2018
- 2018-03-12 CN CN201810201679.9A patent/CN108376677B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1164765A (en) * | 1996-03-06 | 1997-11-12 | 现代电子产业株式会社 | Semiconductor package |
| CN102024782A (en) * | 2010-10-12 | 2011-04-20 | 北京大学 | Three-dimensional vertical interconnecting structure and manufacturing method thereof |
| US9773751B1 (en) * | 2016-06-29 | 2017-09-26 | International Business Machines Corporation | Via and trench filling using injection molded soldering |
| CN106648210A (en) * | 2016-10-19 | 2017-05-10 | 合肥鑫晟光电科技有限公司 | Display panel and preparation method thereof, display device |
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