CN108364858A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN108364858A CN108364858A CN201810111778.8A CN201810111778A CN108364858A CN 108364858 A CN108364858 A CN 108364858A CN 201810111778 A CN201810111778 A CN 201810111778A CN 108364858 A CN108364858 A CN 108364858A
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- pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Abstract
Present invention is disclosed a kind of semiconductor devices and preparation method thereof, including：A substrate is provided, the substrate has multiple first areas and multiple second areas；Multiple first patterns are formed over the substrate, and first pattern is located on the first area, and first pattern has a notch for appearing the second area；A first adjustment layer is formed over the substrate；A second adjustment layer is formed on the first adjustment layer, the second adjustment layer fills up the notch；The remaining second adjustment layer of the second adjustment layer above first pattern is removed to be collectively formed as multiple second patterns with the first adjustment layer below the second adjustment layer；The first adjustment layer between first pattern and second pattern is removed, forms gap between the first pattern and the second pattern, the width in the gap is less than the distance between described first pattern, is advantageously implemented the preparation of small size pattern.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor devices and preparation method thereof.
Background technology
With being constantly progressive for semiconductor technology, the process node of semiconductor devices just constantly reduces.However, due to by
The limitation of existing photoetching process precision, the mask pattern formed with existing photoetching process, which is difficult to meet semiconductor devices, to be continued
The demand for reducing characteristic size (Critical Dimension, abbreviation CD), especially when characteristic size is reduced to 30nm or less,
Existing photoetching process can not prepare fine pattern, contain the development of semiconductor technology.
Invention content
The object of the present invention is to provide a kind of preparation methods of semiconductor devices, can accurately prepare small feature ruler
Very little pattern.
In order to solve the above technical problems, the present invention provides a kind of preparation method of semiconductor devices, including：
There is provided a substrate, the substrate has multiple first areas and a multiple second areas, the first area and the
Two regions are alternatively arranged；
Multiple first patterns are formed over the substrate, and first pattern is located on the first area；
A first adjustment layer is formed over the substrate, and the first adjustment layer submissively covers the top of first pattern
The second area of wall, side wall and the substrate, the first adjustment layer have a covering second area and with described the
One pattern generates the notch of a difference in height；
A second adjustment layer is formed on the first adjustment layer, the second adjustment layer fills up the notch；
Remove the second adjustment layer above first pattern so that the second adjustment layer is retained in the second area
On partially patterned, the common shape of the first adjustment layer below the remaining second adjustment layer and the second adjustment layer
As multiple second patterns, first pattern and second figure is isolated in the first adjustment layer of first pattern sidewalls
Case, and the spacing between first pattern and second pattern is defined by the thickness of the first adjustment layer；With
And
Remove the first adjustment layer between first pattern and second pattern.
Further, in the preparation method of the semiconductor devices, the material of the first adjustment layer and described first
The material of pattern is different, also, the material of the first adjustment layer is different from the material of second adjustment layer, and described first adjusts
The etch rate of flood is more than the etch rate of first pattern, and the etch rate of the first adjustment layer is more than described second
The etch rate of adjustment layer.
Further, it in the preparation method of the semiconductor devices, removes in first pattern and second figure
After the first adjustment layer between case, a gap is formed between first pattern and second pattern.
Further, in the preparation method of the semiconductor devices, the preparation method further includes：In the gap
Form packing material.
Further, in the preparation method of the semiconductor devices, in removal in first pattern and described second
During the first adjustment layer between pattern, the thickness of the second adjustment layer is only smaller than the thickness of first pattern
In an atomic layer deposition thickness, to maintain the pattern of second pattern complete.
Another side according to the present invention also provides a kind of semiconductor devices, including：
One substrate, the substrate have multiple first areas and multiple second areas, the first area and the secondth area
Domain is alternatively arranged；
Multiple first patterns, are formed in over the substrate, and first pattern is located at a first area
On；
One the first adjustment layer, is formed in over the substrate, and the first adjustment pattern layers are located at the second area
On, the first adjustment layer has the covering second area and generates the notch of a difference in height with first pattern；With
And
One second adjustment layer is formed on the first adjustment layer, and the second adjustment layer fills up the notch, described
Second adjustment pattern layers are located on the second area, and it is more that the first adjustment layer is collectively formed with the second adjustment layer
A second pattern；
Wherein, a gap is formed between first pattern and second pattern, the width in the gap is to pass through
The thickness of the first adjustment layer defines.
Further, in the semiconductor devices, the material of the material of the first adjustment layer and first pattern
Difference, also, the material of the first adjustment layer is different from the material of second adjustment layer, the etching of the first adjustment layer
Rate is more than the etch rate of first pattern, and the etch rate of the first adjustment layer is more than the quarter of the second adjustment layer
Lose rate.
Further, further include the packing material being formed in the gap in the semiconductor devices.
Further, in the semiconductor devices, first pattern is same thickness with second pattern, described
Packing material is the upright circuit that thickness is more than width, corresponds to the two opposite sides side of the notch.
Further, in the semiconductor devices, the thickness of the second adjustment layer is only smaller than first pattern
Thickness is in an atomic layer deposition thickness, to maintain the pattern of second pattern complete.
Compared with prior art, semiconductor devices provided by the invention and preparation method thereof has the following advantages：
In semiconductor devices provided by the invention and preparation method thereof, the on the side wall for removing first pattern
After one adjustment layer, gap is formed between the first pattern and the second pattern, the width in the gap is less than first figure
The distance between case (characteristic size of the i.e. described second area), is advantageously implemented the preparation of small size pattern.
Description of the drawings
Fig. 1 is the flow chart of the preparation method of the semiconductor devices of one embodiment of the invention；
Fig. 2 to Fig. 9 is the structural schematic diagram of each step of preparation method of the semiconductor devices of one embodiment of the invention；
Figure 10 is the schematic diagram of semiconductor devices in one embodiment of the invention；And
Figure 11 is the structural schematic diagram of each step of preparation method of the semiconductor devices of another embodiment of the present invention.
Wherein, 1 is semiconductor devices；
100 be substrate；
10A is first area；
10B is second area；
120 be the first pattern layer；
121 be the first pattern film；
121 ' be the first pattern；
122 be the second pattern film；
123 be photoresist pattern；
124 be opening；
125 be gap；
126 be notch；
130 be the second pattern；
131 be the first adjustment layer；
132 be second adjustment layer；
140 be packing material.
Specific implementation mode
The method for forming figure in the semiconductor device of the present invention is retouched in more detail below in conjunction with schematic diagram
It states, which show the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can change described here hair
It is bright, and still realize the advantageous effects of the present invention.Therefore, following description should be understood as the wide of those skilled in the art
It is general to know, and it is not intended as limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, another embodiment is changed by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but it is only to those skilled in the art routine work.
The present invention is more specifically described by way of example with reference to attached drawing in the following passage.It is wanted according to following explanation and right
Ask book, advantages and features of the invention that will become apparent from.It should be noted that attached drawing is all made of very simplified form and uses non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Core of the invention thought is, provides a kind of method forming figure in the semiconductor device, as shown in Figure 1,
Including：
Step S11, provide a substrate, the substrate have multiple first areas and multiple second areas, described first
Region and second area are alternatively arranged；
Step S12, multiple first patterns are formed over the substrate, and first pattern is located on the first area；
Step S13, a first adjustment layer is formed over the substrate, and the first adjustment layer submissively covers described first
The roof of pattern, the second area of side wall and the substrate, the first adjustment layer have a covering second area simultaneously
The notch of a difference in height is generated with first pattern；
Step S14, a second adjustment layer is formed on the first adjustment layer, the second adjustment layer is filled up described and lacked
Mouthful；
Step S15, the second adjustment layer above first pattern is removed so that the second adjustment layer is retained in described
It is partially patterned on second area, the remaining second adjustment layer and the first adjustment below the second adjustment layer
Layer is collectively formed as multiple second patterns, the first adjustment layer isolation first pattern of first pattern sidewalls and institute
The second pattern is stated, and the spacing between first pattern and second pattern is the thickness by the first adjustment layer
Definition；And
Step S16, the first adjustment layer of the removal between first pattern and second pattern.
After the first adjustment layer on the side wall for removing first pattern, between the first pattern and the second pattern
Gap is formed, the width in the gap is less than the distance between first pattern (characteristic size of the i.e. described second area),
It is advantageously implemented the preparation of small size pattern.
Further, a kind of semiconductor devices is also provided, including：One substrate, the substrate have multiple first areas with
And multiple second areas, the first area and second area are alternatively arranged；Multiple first patterns, are formed in the substrate
On, first pattern is located on a first area；One the first adjustment layer, is formed in over the substrate, institute
The first adjustment pattern layers are stated to be located on the second area, the first adjustment layer have a covering second area and with
First pattern generates the notch of a difference in height；And a second adjustment layer, it is formed on the first adjustment layer, it is described
Second adjustment layer fills up the notch, and the second adjustment pattern layers are located on the second area, the first adjustment layer
It is collectively formed as multiple second patterns with the second adjustment layer；Wherein, shape between first pattern and second pattern
The gaps Cheng Youyi, the width in the gap are defined by the thickness of the first adjustment layer.
The preparation method of the semiconductor devices of the present invention is described in more detail below in conjunction with schematic diagram, wherein table
Showing the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still
Realize the advantageous effects of the present invention.Therefore, following description should be understood as the widely known of those skilled in the art, and
It is not intended as limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, another embodiment is changed by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but it is only to those skilled in the art routine work.
The present invention is more specifically described by way of example with reference to attached drawing in the following passage.It is wanted according to following explanation and right
Ask book, advantages and features of the invention that will become apparent from.It should be noted that attached drawing is all made of very simplified form and uses non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The preparation method that Fig. 2-Fig. 9 illustrates the semiconductor devices of one embodiment of the invention is please referred to below.
First, step S11 is carried out, as shown in Fig. 2, providing a substrate 100, the substrate 100 has multiple first areas
10A and second area 10B, the first area 10A and second area 10B are alternatively arranged.In the present embodiment, the substrate
100 be substrate (substrate), specifically, the semiconductor that the material of the substrate can be silicon, germanium or silicon-on-insulator serves as a contrast
Bottom, when the substrate 100 is other functional layers, the substrate 100 is also an option that other materials, for example, the substrate 100
It can also be dielectric layer or metal layer etc..
Then, step S12 is carried out, forms multiple first patterns on the substrate 100, each first pattern difference
On a first area 10A.Specifically, in the present embodiment, the step S12 includes sub-step S121~sub-step
Rapid S122：
Sub-step S121, as shown in figure 3, forming one first pattern layer 120 on the substrate 100.First pattern
Layer 120 may include a tunic layer or multilayer laminated film layer, and in figure 3, first pattern layer 120 includes layer from bottom to top
Folded the first pattern film 121 and the second pattern film 122, wherein first pattern film, 121 and second pattern film
122 etching selection ratio is more than or equal to 5, for example, the material of first pattern film 121 is silica, second pattern
The material of film layer 122 is organic polymer.In other embodiments, first pattern layer 120 includes the multiple of stacked spaced apart
First pattern film 121 and multiple second pattern films 122；
Sub-step S122 forms a photoresist pattern 123 with continued reference to Fig. 3 in first pattern layer 120.With described
Photoresist pattern 123 is mask, is performed etching to first pattern layer 120, in etching process, second pattern film
122 can be consumed, as shown in figure 4, first pattern film 121 is patterned into multiple first patterns 121 ', Mei Gesuo
It states the first pattern 121 to be located on a first area 10A, one is spaced between adjacent first pattern 121 '
The second area 10B, first pattern 121 ' have an opening 124 for appearing the second area 10B.
Due to being influenced by photoetching process accuracy, the spacing K1 of the adjacent photoresist pattern 123 is (as shown in Figure 3) minimum
It can accomplish 30nm or so, can not accomplish again small.After being performed etching to first pattern layer 120, the photoresist pattern 123
Pattern is transferred in first pattern layer 120, forms the first pattern 121, the spacing of adjacent first pattern 121 '
It is K1, the spacing of adjacent first pattern 121 ' can not further decrease, and restrict the lasting reduction of dimensions of semiconductor devices.
In order to reduce the spacing in semiconductor devices between pattern, step S13 is carried out, as shown in figure 5, in the substrate
A first adjustment layer 131 is formed on 100, the first adjustment layer 131 submissively covers the roof of first pattern 121 ', side
The second area 10B of wall and the substrate 100, the first adjustment layer 131 have a covering second area 10B and with
First pattern 121 ' generates the notch 126 of a difference in height, wherein first pattern 121 ' is higher than the second area
The first adjustment layer 131 on 10B.Preferably, as shown in figure 5, the thickness H1 of the first adjustment layer 131 is less than first figure
The thickness H2 of case 121 ', the first adjustment layer 131 can not fill the opening 124, only the side wall of covering opening 124 and bottom
Wall, it is ensured that the second pattern is formed in subsequent technique.The thickness H1 of the first adjustment layer 131 be preferably 5nm~
30nm can be adjusted by adjusting the thickness of the first adjustment layer 131 for example, 8nm, 10nm, 15nm, 20nm or 25nm etc.
Save the spacing of second pattern.The material of the first adjustment layer 131 generally can be silica, silicon nitride or silicon oxynitride
Etc., atomic deposition (Atomic Layer Deposition) technique may be used in the first adjustment layer 131 or plasma steams
Gas deposits the depositing operations such as (Chemical Vapor Deposition) technique and prepares.The thickness H1 of the first adjustment layer 131
It can accomplish very thin, the thickness H1 of the first adjustment layer 131 can accomplish an atomic layer deposition thickness, i.e., using deposition work
Most thin thickness (thickness of film when only depositing an atomic layer) prepared by skill.
Later, step S14 is carried out, as shown in fig. 6, a second adjustment layer 132 is formed on the first adjustment layer 131,
The second adjustment layer 132 fills up the notch 126.Specifically, the second adjustment layer 132 covers the entire the first adjustment
Layer 131.The material of the second adjustment layer 132 generally can be silica, silicon nitride or silicon oxynitride etc..
Then, step S15 is carried out, as shown in fig. 7, the second adjustment layer 132 above removal first pattern 121 ', makes
It obtains the second adjustment layer 132 and is retained in partially patterned on the second area 10B, the remaining second adjustment layer
132 are collectively formed with the first adjustment layer 131 of the lower section of the second adjustment layer 132 as multiple second patterns 130, and described the
First pattern 121 ' and second pattern 130, and institute is isolated in the first adjustment layer 131 of one pattern, 121 ' side wall
Stating the spacing between the first pattern 121 ' and second pattern 130 is defined by the thickness of the first adjustment layer 131.It can
To remove first pattern, 121 ' top using planarization (such as chemical mechanical grinding) technique or etching (such as returning quarter) technique
Second adjustment layer 132.
Later, carry out step S16, as shown in figure 8, removal first pattern 121 ' and second pattern 132 it
Between the first adjustment layer 131.Since the first adjustment layer 131 on the top and side wall of first pattern 121 ' is exposed
Out, so, in the step S15, the first adjustment layer 131 on the top and side wall of first pattern 121 ' all can be by
It gets rid of, only the remaining the first adjustment layer 131 positioned at 132 lower section of the second adjustment layer.The technique removal of etching may be used
The first adjustment layer 131 on the side wall of first pattern 121 '.Preferably, the material of the first adjustment layer 131 with it is described
The material of first pattern 121 ' is different, also, the material of the material of the first adjustment layer 131 and the second adjustment layer 132
Difference, the etch rate of the first adjustment layer 131 are more than the etch rate of first pattern 121 ', the first adjustment layer
131 etch rate is more than the etch rate of the second adjustment layer 132, is adjusted to avoid to first pattern 121 ' and second
Flood 132 it is excessive.
That is, while etching the first adjustment layer 131, in second pattern 130 can be also etched
Two adjustment layer 132, partly to remove the second adjustment layer 132, so as to reduce the thickness of the second pattern 130 after etching,
The top surface of the second adjustment layer 132 after etching is set to be not higher than the top surface of first pattern 121 '.
That is, while etching the first adjustment layer 131 using etching technics, the etching technics can also be to second
Second adjustment layer 132 in pattern 130 performs etching, to control the height for the second pattern 130 being ultimately formed simultaneously.So
One, it on the one hand need not additionally increase the step of being adjusted together to the height of the second pattern 130 again (for example, additionally applying
The etch step added)；On the other hand, since 130 top surface of the second pattern being ultimately formed is not higher than the first pattern 121 '
Top surface, therefore ought subsequently need packing material in the gap between the second pattern 130 and the first pattern 121 ' after etching
When, filling difficulty is advantageously reduced, to further increase the quality of the filled layer of filling in the gap.
For example, when the top surface of the second pattern 130 after the etching is flushed with the 121 ' top surface of the first pattern,
, can be directly with second pattern, 130 and first pattern 121 ' for polish stop layer then in packing material, and utilize and grind
Grinding process is filled in the gap between the first pattern 121 ' and the second pattern 130 with enabling packing material autoregistration.
Specifically, the etching selection ratio of the first adjustment layer 131 and the second adjustment layer 132 is more than or equal to 4, example
Such as, when the material of the first adjustment layer 131 is silica, the material of the second adjustment layer 132 is silicon nitride.It is etching
In the process, the etch rate of the first adjustment layer 131 is more than to the etch rate of the second adjustment layer 132, described the
The first adjustment layer 131 on the top and side wall of one pattern 121 ' can be all removed, and be left the second adjustment layer 132.Position
The first adjustment layer 131 in 132 lower section of the second adjustment layer is blocked by the second adjustment layer 132, is located at described second and is adjusted
The first adjustment layer 131 of 132 lower section of flood is left.Preferably, removing first pattern 121 ' using dry etch process
Side wall on the first adjustment layer 131, dry etch process have anisotropy, can be to avoid positioned at the second adjustment layer
The first adjustment layer 131 of 132 lower sections is etched by transition.In the process, the second adjustment layer 132 may be by partly or complete
Portion removes.Preferably, the thickness H3 of the second adjustment layer 132 is only smaller than the thickness H2 of first pattern 121 ' in an original
Sublayer deposition thickness is (when the thickness H1 of the first adjustment layer 131 is an atomic layer deposition thickness, the second adjustment layer
The sum of 132 thickness H3 and the thickness H1 of the first adjustment layer 131 are the thickness H2 of first pattern 121 '), described in maintenance
The pattern of second pattern 130 is complete.
The spacing K2 of first pattern 121 ' and the second pattern 130 can pass through the thickness of the first adjustment layer 131
H1 is defined, in general, the thickness H1 of the first adjustment layer 131 is thicker, adjacent first pattern 121 ' and the second pattern
130 spacing K2 is bigger.The spacing K2 of first pattern 121 ' and the second pattern 130 is less than adjacent first pattern
The spacing K2 of 121 spacing K1, first pattern 121 ' and the second pattern 130 can be less than the minimum feature of photoetching process.
Then, as shown in figure 8, removing described first between first pattern 121 ' and second pattern 130
After adjustment layer 131, a gap 125 is formed between first pattern and second pattern.As shown in figure 9, in this reality
It applies in example, packing material 140 can also be formed in the gap 125, the width of the packing material 140 is K2, Ke Yi little
It can reach an atomic layer deposition thickness in the width minimum of the minimum feature of photoetching process, the packing material 140.It is described
The material of packing material 140 can be metal, such as metallic copper or metallic aluminium etc., be used to form metal wire and for example interconnect metal
Line realizes nano metal line.
Preferably, first pattern 121 ' is same thickness, i.e., described first pattern 121 ' with second pattern 130
With the upper surface flush of second pattern 130, the packing material 140 is the upright circuit that thickness is more than width, is corresponded to
The two opposite sides side of the notch 126.As noted previously, as the upper table of first pattern 121 ' and second pattern 130
Face flushes, to be filled in the gap 125 with can realizing 140 autoregistration of packing material.
It should be appreciated that in practical application after forming first pattern 121 ' and the second pattern 130, it can basis
Different demands continues to execute subsequent related process.For example, the first pattern 121 ' described in the present embodiment and the second pattern 130
For defining gap 125, so as to realize that packing material 140 is right on the basis of the first pattern 121 ' and the second pattern 130
It is filled in accurately in gap 125.Therefore, the first pattern 121 ' and the second pattern 130 can constitute follow-up be formed by partly accordingly
A part for conductor structure, because of this, the thickness of the second pattern 130 is also further controlled in the present embodiment, so as to carve
The top surface of the second pattern 130 after erosion is not higher than the top surface of first pattern 121 '.
Specifically, (being located at corresponding to two packing materials 140 of two parallel sides of a notch 126
Two packing materials 140 in the same second area 10B), the packing material 140 be more specifically parallel to it is straight
Vertical circuit, it is according to the present invention above-mentioned to retouch to pass through same active area and being presented that microwire is wide and increased two parallel wordlines of thickness
State, parallel line and two parallel wordlines be it will be understood by those skilled in the art that, details are not described herein.
As shown in Figure 10, it is a kind of semiconductor devices 1 provided by the present invention, in the present embodiment, the semiconductor device
Part 1 uses Fig. 2 to Fig. 9 to be prepared for the preparation method of the semiconductor devices of one embodiment of the invention, the semiconductor devices 1
Including：Substrate 100, multiple first patterns 121 ', the first adjustment layer 131 and second adjustment layer 132, the substrate 100 have
Multiple first area 10A and multiple second area 10B, the first area 10A and second area 10B are alternatively arranged；It is multiple
First pattern 121 ' is formed on the substrate 100, and first pattern 121 ' is located at firstth area
On the 10A of domain；The first adjustment layer 131 is formed on the substrate 100, and the patterning of the first adjustment layer 131 is located at institute
State on second area 10B, the first adjustment layer 131 have a covering second area 10B and with first pattern
121 ' generate the notch 126 of a difference in height；The second adjustment layer 132 is formed on the first adjustment layer 131, and described
Two adjustment layer 132 fill up the notch 126, and the patterning of second adjustment layer 132 is located on the second area 10B, described
The first adjustment layer 131 and the second adjustment layer 132 are collectively formed as multiple second patterns 130, and second pattern 130
Thickness reduce so that the second adjustment layer 132 top surface be not higher than first pattern 121 ' top surface.
Wherein, a gap 125, the gap 125 are formed between first pattern 121 ' and second pattern 130
Width be to be defined by the thickness of the first adjustment layer 131, the thickness H3 of the second adjustment layer 132 is only smaller than described the
The thickness H2 of one pattern 121 ' is in an atomic layer deposition thickness (when the thickness H1 of the first adjustment layer 131 is an atom
Layer deposition thickness, the sum of the thickness H3 of the second adjustment layer 132 and the thickness H1 of the first adjustment layer 131 are first pattern
121 ' thickness H2).
In the present embodiment, the gap 125 is also formed with packing material 140, and the width of the packing material 140 is
K2, can be less than the minimum feature of photoetching process, and the width minimum of the packing material 140 can reach an atomic layer deposition
Thickness.The material of the packing material 140 can be metal, such as metallic copper or metallic aluminium etc., be used to form metal wire for example
Interconnection metallization lines realize nano metal line.
In another embodiment, in step s 16, removal first pattern 121 ' and second pattern 130 it
Between the first adjustment layer 131 when, to the first adjustment layer 131 carry out high selectivity etching, i.e., to the first adjustment
The etch rate of layer 131 is much larger than the etch rate to first pattern 121 ' and the second adjustment layer 132, is tied in etching
Shu Shi, as shown in figure 11 so that the second adjustment layer 132 that first pattern 121 ' can slightly below leave.In follow-up step
In, after forming packing material 140 in the gap 125, it can be planarized by techniques such as masks so that in difference
Packing material 140 in the gap 125 is isolated from each other.
In the above embodiment of the present invention, first pattern 121 ' and the second pattern 130 are dielectric layer, described
Packing material 140 is metal, and to form metal wire in the dielectric layer, in other embodiments, the preparation method is also
Can be used for preparing the pattern in other film layers, specific implementation step is similar to thinking and the above embodiment of the present invention,
Under the enlightenment of the embodiment of the present invention, the extension of this application is that should be readily appreciated that and realize for those of ordinary skill in the art
, details are not described herein.
To sum up, the present invention provides a kind of preparation method of semiconductor devices and includes：A substrate is provided, the substrate has more
A first area and multiple second areas, the first area and second area are alternatively arranged；It is formed over the substrate more
A first pattern, first pattern are located on the first area；Form a first adjustment layer over the substrate, described
One adjustment layer submissively covers the second area of the roof of first pattern, side wall and the substrate, the first adjustment
Layer has the covering second area and generates the notch of a difference in height with first pattern；On the first adjustment layer
A second adjustment layer is formed, the second adjustment layer fills up the notch；The second adjustment layer above first pattern is removed,
So that the second adjustment layer be retained in it is partially patterned on the second area, the remaining second adjustment layer with it is described
The first adjustment layer below second adjustment layer is collectively formed as multiple second patterns, and described the of first pattern sidewalls
One adjustment layer is isolated first pattern and second pattern, and between first pattern and second pattern between
Away from being defined by the thickness of the first adjustment layer；Removal between first pattern and second pattern described the
One adjustment layer.
After the first adjustment layer on the side wall for removing first pattern, between the first pattern and the second pattern
Gap is formed, the width in the gap is less than the distance between first pattern (characteristic size of the i.e. described second area),
It is advantageously implemented the preparation of small size pattern.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of preparation method of semiconductor devices, which is characterized in that including：
A substrate is provided, the substrate has multiple first areas and multiple second areas, the first area and the secondth area
Domain is alternatively arranged；
Multiple first patterns are formed over the substrate, and first pattern is located on the first area；
Form a first adjustment layer over the substrate, the first adjustment layer submissively cover first pattern roof,
The second area of side wall and the substrate, the first adjustment layer have a covering second area and with first figure
Case generates the notch of a difference in height；
A second adjustment layer is formed on the first adjustment layer, the second adjustment layer fills up the notch；
Remove the second adjustment layer above first pattern so that the second adjustment layer is retained on the second area
It is partially patterned, the first adjustment layer below the remaining second adjustment layer and the second adjustment layer be collectively formed for
First pattern and second pattern is isolated in the first adjustment layer of multiple second patterns, first pattern sidewalls,
And the spacing between first pattern and second pattern is defined by the thickness of the first adjustment layer；And
Etching technics is executed, the part for covering the first pattern roof in the first adjustment layer and first tune are removed
Part in flood between first pattern and second pattern, while part removes the second adjustment layer, with
Reduce the thickness of second pattern, so that the top surface of the second adjustment layer after etching is not higher than first pattern
Top surface.
2. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the material of the first adjustment layer with
The material of first pattern is different, also, the material of the first adjustment layer is different from the material of second adjustment layer, institute
The etch rate for stating the first adjustment layer is more than the etch rate of first pattern, and the etch rate of the first adjustment layer is more than
The etch rate of the second adjustment layer.
3. the preparation method of semiconductor devices as described in claim 1, which is characterized in that removal is in first pattern and institute
After stating the first adjustment layer between the second pattern, formed between one between first pattern and second pattern
Gap.
4. the preparation method of semiconductor devices as claimed in claim 3, which is characterized in that the preparation method further includes：
Packing material is formed in the gap.
5. such as the preparation method of Claims 1-4 any one of them semiconductor devices, which is characterized in that in removal described
During the first adjustment layer between first pattern and second pattern, the thickness of the second adjustment layer is only smaller than
The thickness of first pattern is in an atomic layer deposition thickness, to maintain the pattern of second pattern complete.
6. a kind of semiconductor devices, which is characterized in that including：
One substrate, the substrate has multiple first areas and multiple second areas, between the first area and second area
Every arrangement；
Multiple first patterns, are formed in over the substrate, and first pattern is located on a first area；
One the first adjustment layer, is formed in over the substrate, and the first adjustment pattern layers are located on the second area, institute
State the notch that the first adjustment layer generates a difference in height with the covering second area and with first pattern；And
One second adjustment layer is formed on the first adjustment layer, and the second adjustment layer fills up the notch, and described second
Adjustment pattern layers are located on the second area, and it is multiple that the first adjustment layer and the second adjustment layer, which are collectively formed,
Two patterns, and the thickness reduction of second pattern makes the top surface of the second adjustment layer be not higher than first pattern top
Surface；
Wherein, a gap is formed between first pattern and second pattern, the width in the gap is by described
The thickness of the first adjustment layer defines.
7. semiconductor devices as claimed in claim 6, which is characterized in that the material of the first adjustment layer and first figure
The material of case is different, also, the material of the first adjustment layer is different from the material of second adjustment layer, the first adjustment
The etch rate of layer is more than the etch rate of first pattern, and the etch rate of the first adjustment layer is more than described second and adjusts
The etch rate of flood.
8. semiconductor devices as claimed in claim 6, which is characterized in that further include the filling material being formed in the gap
Material.
9. semiconductor devices as claimed in claim 8, which is characterized in that first pattern is identical with second pattern
Thickness, the packing material are the upright circuit that thickness is more than width, correspond to the two opposite sides side of the notch.
10. such as claim 6 to 9 any one of them semiconductor devices, which is characterized in that the thickness of the second adjustment layer is only
Less than first pattern thickness in an atomic layer deposition thickness, to maintain the pattern of second pattern complete.
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| US20090176376A1 (en) * | 2008-01-07 | 2009-07-09 | Shi-Yong Yi | Method of fine patterning semiconductor device |
| US20130175629A1 (en) * | 2012-01-05 | 2013-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device and methods for forming partially self-aligned trenches |
| US8946078B2 (en) * | 2012-03-22 | 2015-02-03 | United Microelectronics Corp. | Method of forming trench in semiconductor substrate |
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| TWI274397B (en) * | 2003-11-20 | 2007-02-21 | Winbond Electronics Corp | Method for forming narrow trench structure and method for forming gate structure with narrow spacing |
| KR20090076743A (en) * | 2008-01-07 | 2009-07-13 | 삼성전자주식회사 | Method of forming fine patterns of semiconductor device |
| US8796155B2 (en) * | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
| CN103794475B (en) * | 2012-10-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | The triple graphic method of autoregistration |
| US9269606B2 (en) * | 2014-02-19 | 2016-02-23 | Microchip Technology Incorporated | Spacer enabled active isolation for an integrated circuit device |
| US9972702B2 (en) * | 2014-05-22 | 2018-05-15 | Taiwan Semiconductor Manufacturing Company | Method for non-resist nanolithography |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20090176376A1 (en) * | 2008-01-07 | 2009-07-09 | Shi-Yong Yi | Method of fine patterning semiconductor device |
| US20130175629A1 (en) * | 2012-01-05 | 2013-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device and methods for forming partially self-aligned trenches |
| US8946078B2 (en) * | 2012-03-22 | 2015-02-03 | United Microelectronics Corp. | Method of forming trench in semiconductor substrate |
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| CN107068548B (en) | 2018-10-16 |
| CN108364858B (en) | 2019-03-26 |
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