CN108351820B - 在跨存储器链路传送纠正数据时保护ecc位置 - Google Patents
在跨存储器链路传送纠正数据时保护ecc位置 Download PDFInfo
- Publication number
- CN108351820B CN108351820B CN201680067395.4A CN201680067395A CN108351820B CN 108351820 B CN108351820 B CN 108351820B CN 201680067395 A CN201680067395 A CN 201680067395A CN 108351820 B CN108351820 B CN 108351820B
- Authority
- CN
- China
- Prior art keywords
- data
- mask
- ecc
- parity bits
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Quality & Reliability (AREA)
- Computer Security & Cryptography (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
- Dram (AREA)
- Memory System (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562258155P | 2015-11-20 | 2015-11-20 | |
| US62/258,155 | 2015-11-20 | ||
| US15/081,460 | 2016-03-25 | ||
| US15/081,460 US10140175B2 (en) | 2015-11-20 | 2016-03-25 | Protecting an ECC location when transmitting correction data across a memory link |
| PCT/US2016/054162 WO2017087075A1 (en) | 2015-11-20 | 2016-09-28 | Protecting an ecc location when transmitting correction data across a memory link |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108351820A CN108351820A (zh) | 2018-07-31 |
| CN108351820B true CN108351820B (zh) | 2021-06-29 |
Family
ID=57133425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680067395.4A Active CN108351820B (zh) | 2015-11-20 | 2016-09-28 | 在跨存储器链路传送纠正数据时保护ecc位置 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US10140175B2 (https=) |
| EP (1) | EP3377975A1 (https=) |
| JP (1) | JP2018535494A (https=) |
| KR (1) | KR20180083864A (https=) |
| CN (1) | CN108351820B (https=) |
| AU (1) | AU2016355459A1 (https=) |
| WO (1) | WO2017087075A1 (https=) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9965352B2 (en) | 2015-11-20 | 2018-05-08 | Qualcomm Incorporated | Separate link and array error correction in a memory system |
| US10503435B2 (en) | 2016-12-01 | 2019-12-10 | Qualcomm Incorporated | Providing extended dynamic random access memory (DRAM) burst lengths in processor-based systems |
| CN107039086B (zh) * | 2017-05-17 | 2024-08-30 | 西安紫光国芯半导体有限公司 | 具有兼容不同数据长度的纠错功能的存储器和纠错方法 |
| KR102688423B1 (ko) * | 2017-07-05 | 2024-07-26 | 에스케이하이닉스 주식회사 | 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 시스템의 동작 방법 |
| US10387242B2 (en) | 2017-08-21 | 2019-08-20 | Qualcomm Incorporated | Dynamic link error protection in memory systems |
| US10949278B2 (en) * | 2018-06-26 | 2021-03-16 | Qualcomm Incorporated | Early detection of execution errors |
| US10901839B2 (en) | 2018-09-26 | 2021-01-26 | International Business Machines Corporation | Common high and low random bit error correction logic |
| TWI714277B (zh) * | 2018-09-28 | 2020-12-21 | 台灣積體電路製造股份有限公司 | 記憶體錯誤偵測及校正 |
| US11204826B2 (en) | 2018-09-28 | 2021-12-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory error detection and correction |
| CN111984457B (zh) * | 2019-05-23 | 2022-09-02 | 华为技术有限公司 | 对存储信息更新的方法和装置 |
| US11403172B2 (en) * | 2019-08-05 | 2022-08-02 | Cypress Semiconductor Corporation | Methods for error detection and correction and corresponding systems and devices for the same |
| US11372717B2 (en) * | 2019-08-30 | 2022-06-28 | Qualcomm Incorporated | Memory with system ECC |
| US11037647B1 (en) * | 2020-02-19 | 2021-06-15 | Semiconductor Components Industries, Llc | Systems and methods for updating memory circuitry |
| KR102713429B1 (ko) * | 2020-03-17 | 2024-10-04 | 에스케이하이닉스 주식회사 | 반도체장치 |
| WO2022053157A1 (en) * | 2020-09-14 | 2022-03-17 | Huawei Technologies Co., Ltd. | Fault resistant verification |
| US11327836B1 (en) * | 2020-09-29 | 2022-05-10 | Xilinx, Inc. | Protection of data on a data path in a memory system |
| CN115019862B (zh) * | 2021-03-04 | 2026-01-13 | 瑞昱半导体股份有限公司 | 静态随机存取存储器的纠错电路的验证方法 |
| KR20230052346A (ko) * | 2021-10-12 | 2023-04-20 | 삼성전자주식회사 | 메모리 모듈, 메모리 시스템, 및 메모리 컨트롤러의 동작 방법 |
| US11886295B2 (en) | 2022-01-31 | 2024-01-30 | Pure Storage, Inc. | Intra-block error correction |
| US12235757B2 (en) * | 2022-05-18 | 2025-02-25 | Samsung Electronics Co., Ltd. | Memory systems and controllers for generating a command address and methods of operating same |
| CN115291816B (zh) * | 2022-10-10 | 2022-12-09 | 新云滕(云南)科技有限公司 | 一种用于基于三维可视化的配电管理系统的存储器系统 |
| US12159033B2 (en) * | 2022-10-18 | 2024-12-03 | Qualcomm Incorporated | Metadata registers for a memory device |
| CN118335167A (zh) * | 2023-01-03 | 2024-07-12 | 长鑫存储技术有限公司 | 存储器及其测试方法 |
| KR20240115671A (ko) * | 2023-01-19 | 2024-07-26 | 삼성전자주식회사 | 인코딩 데이터를 전송하는 전자 장치, 및 이의 동작하는 방법 |
| CN116594924B (zh) * | 2023-05-19 | 2023-10-24 | 无锡众星微系统技术有限公司 | 一种片上ecc存储器的访问方法和装置 |
| KR20250127636A (ko) * | 2024-02-19 | 2025-08-26 | 삼성전자주식회사 | 메모리 장치 및 메모리 장치를 포함하는 컴퓨팅 시스템 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991801A (zh) * | 2005-11-30 | 2007-07-04 | 株式会社东芝 | 访问控制设备、方法和存储器访问控制设备、方法 |
| CN101647004A (zh) * | 2007-02-12 | 2010-02-10 | 美光科技公司 | 存储器阵列错误校正设备、系统和方法 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6904498B2 (en) * | 2002-10-08 | 2005-06-07 | Netcell Corp. | Raid controller disk write mask |
| US6876594B2 (en) * | 2002-12-26 | 2005-04-05 | Texas Instruments Incorporated | Integrated circuit with programmable fuse array |
| US7464241B2 (en) * | 2004-11-22 | 2008-12-09 | Intel Corporation | Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding |
| US7774684B2 (en) | 2006-06-30 | 2010-08-10 | Intel Corporation | Reliability, availability, and serviceability in a memory device |
| US8209587B1 (en) * | 2007-04-12 | 2012-06-26 | Netapp, Inc. | System and method for eliminating zeroing of disk drives in RAID arrays |
| US7987229B1 (en) * | 2007-06-28 | 2011-07-26 | Emc Corporation | Data storage system having plural data pipes |
| US8082482B2 (en) * | 2007-08-31 | 2011-12-20 | International Business Machines Corporation | System for performing error correction operations in a memory hub device of a memory module |
| US8006033B2 (en) * | 2008-09-09 | 2011-08-23 | Intel Corporation | Systems, methods, and apparatuses for in-band data mask bit transmission |
| US8417987B1 (en) * | 2009-12-01 | 2013-04-09 | Netapp, Inc. | Mechanism for correcting errors beyond the fault tolerant level of a raid array in a storage system |
| JP5490062B2 (ja) | 2011-07-19 | 2014-05-14 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| US8959417B2 (en) | 2011-11-23 | 2015-02-17 | Marvell World Trade Ltd. | Providing low-latency error correcting code capability for memory |
| JP5908375B2 (ja) | 2012-08-30 | 2016-04-26 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| US9064606B2 (en) * | 2012-12-20 | 2015-06-23 | Advanced Micro Devices, Inc. | Memory interface supporting both ECC and per-byte data masking |
| US9588840B2 (en) | 2013-04-18 | 2017-03-07 | Samsung Electronics Co., Ltd. | Memory devices that perform masked write operations and methods of operating the same |
| WO2014205590A1 (en) * | 2013-06-24 | 2014-12-31 | Micron Technology, Inc. | Circuits, apparatuses, and methods for correcting data errors |
| US10176038B2 (en) * | 2015-09-01 | 2019-01-08 | International Business Machines Corporation | Partial ECC mechanism for a byte-write capable register |
-
2016
- 2016-03-25 US US15/081,460 patent/US10140175B2/en active Active
- 2016-09-28 WO PCT/US2016/054162 patent/WO2017087075A1/en not_active Ceased
- 2016-09-28 CN CN201680067395.4A patent/CN108351820B/zh active Active
- 2016-09-28 EP EP16781612.3A patent/EP3377975A1/en not_active Withdrawn
- 2016-09-28 KR KR1020187014079A patent/KR20180083864A/ko not_active Withdrawn
- 2016-09-28 AU AU2016355459A patent/AU2016355459A1/en not_active Abandoned
- 2016-09-28 JP JP2018524791A patent/JP2018535494A/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991801A (zh) * | 2005-11-30 | 2007-07-04 | 株式会社东芝 | 访问控制设备、方法和存储器访问控制设备、方法 |
| CN101647004A (zh) * | 2007-02-12 | 2010-02-10 | 美光科技公司 | 存储器阵列错误校正设备、系统和方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20170147431A1 (en) | 2017-05-25 |
| EP3377975A1 (en) | 2018-09-26 |
| BR112018010187A2 (pt) | 2018-11-21 |
| JP2018535494A (ja) | 2018-11-29 |
| WO2017087075A1 (en) | 2017-05-26 |
| KR20180083864A (ko) | 2018-07-23 |
| CN108351820A (zh) | 2018-07-31 |
| US10140175B2 (en) | 2018-11-27 |
| AU2016355459A1 (en) | 2018-05-10 |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |