CN108346668B - Display substrate, manufacturing method thereof and display device - Google Patents
Display substrate, manufacturing method thereof and display device Download PDFInfo
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- CN108346668B CN108346668B CN201810054626.9A CN201810054626A CN108346668B CN 108346668 B CN108346668 B CN 108346668B CN 201810054626 A CN201810054626 A CN 201810054626A CN 108346668 B CN108346668 B CN 108346668B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The invention provides a display substrate, a manufacturing method thereof and a display device. The display substrate provided by the invention comprises a second conducting layer, wherein the second conducting layer comprises a polar plate region which is formed on the upper surface of at least one gate region and is electrically connected with the gate region. The positive projection of the polar plate region has an overlapping part with the conductive region of the semiconductor layer, and the conductive region is positioned below the edge of the polar plate region of the part and is not positioned at the interface of the channel region of the semiconductor layer and the conductive region. Meanwhile, the plate region is electrically connected with the gate region, so when a gate voltage is applied, the edge of the plate region is the edge of an electric field caused by the gate voltage. Therefore, the number of hot carriers generated at the interface of the strong electric field edge induced channel region of the grid voltage and the conductive region can be effectively reduced, the hot carrier effect is reduced, and the performance of the display device is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a manufacturing method of the display substrate and a display device.
Background
With the continuous development of display technology, various display devices are widely applied to the fields of mobile phones, computers, televisions and the like. The display substrate of the display device includes a semiconductor layer, a gate insulating layer, a gate electrode layer, and the like, which collectively form each thin film transistor of the driving circuit. In the manufacturing process of the display substrate, ion doping is carried out on part of the semiconductor layer to form a source region, a drain region and a conducting channel region. The conducting channel region is not subjected to ion doping, so that the conducting capacity is weak; the source region and the drain region are heavily doped, have strong conductive capability and belong to a conductive region. The interface of the conduction channel region with weak conductivity and the source/drain region with strong conductivity has a junction structure, where hot carriers are easily generated under the action of strong electric field.
In the prior art, a gate is usually used as a mask to perform ion doping on a semiconductor layer. Therefore, the gate edge of the conventional display substrate faces the interface of the conductive channel region and the source/drain region. When a gate voltage is applied, the edge of the electric field caused by the gate voltage is located at the edge of the gate, where the electric field is relatively high, and thus hot carriers are easily induced to be generated at the interface of the conductive channel region and the source/drain regions. High-energy hot carriers are injected into the gate insulating layer, and interface states and trapped charges are generated in the injection process, so that the gate insulating layer is damaged. As the degree of damage increases, the current-voltage characteristics of the display device change. When device parameters change beyond certain limits, the device will fail.
Disclosure of Invention
The present invention is directed to solving the above-mentioned problems and reducing the hot carrier effect, and provides a display substrate and a method for manufacturing the same.
The invention also provides a display device.
In order to achieve the purpose, the invention adopts the following technical scheme:
a display substrate, comprising:
a substrate;
the semiconductor layer is formed on the upper surface of the substrate and comprises a channel region and a conductive region;
the gate insulating layer is formed on the semiconductor layer and the upper surface of the substrate which is not covered by the semiconductor layer;
the first conducting layer is formed on the upper surface of the gate insulating layer and comprises a plurality of gate regions with overlapped parts of orthographic projections and the channel regions;
a second conductive layer comprising a plate region; the polar plate region is formed on the upper surface of at least one gate region and is electrically connected with the gate region, and the orthographic projection of the polar plate region has an overlapping part with the conductive region.
Further, the orthographic projection edge of the gate region is completely positioned inside the plate region on the upper surface of the gate region.
Furthermore, a first insulating layer is formed between the second conducting layer and the first conducting layer, a first through hole is formed in the first insulating layer, and the electrode plate region and the gate region are electrically connected through the first through hole.
Further, the first conducting layer, the gate insulating layer and the semiconductor layer form a plurality of thin film transistors, the thin film transistors comprise driving transistors, and the electrode plate region is formed on the upper surface of the gate region of the driving transistors.
Further, a second through hole is formed in the first insulating layer and the gate insulating layer, the plate region includes a capacitor region forming an effective storage capacitor and a non-capacitor region connected to the capacitor region, and the non-capacitor region is electrically connected to the conductive region through the second through hole.
Furthermore, the second conductive layer further comprises a non-polar plate region separated from the polar plate region, a third through hole is formed in the first insulating layer and the gate insulating layer, and the non-polar plate region is electrically connected with the conductive region through the third through hole.
Further, the first conductive layer is different from the second conductive layer in material, and the polar plate region is in direct contact with the gate region.
Further, the first conductive layer is made of metal, and the second conductive layer is made of indium tin oxide.
The manufacturing method of the display substrate comprises the following steps:
providing a substrate, and forming a semiconductor layer on the upper surface of the substrate;
forming a gate insulating layer on the semiconductor layer and the upper surface of the substrate which is not covered by the semiconductor layer, and forming a first conducting layer on the upper surface of the gate insulating layer, wherein the first conducting layer comprises a plurality of gate regions, and the orthographic projections of the gate regions and the semiconductor layer are provided with a plurality of overlapped parts;
doping the semiconductor layer by taking the first conductive layer as a mask to form a conductive region;
and forming a polar plate region which is electrically connected with the gate region and has an overlapped part with the conductive region in the orthographic projection on the upper surface of the at least one gate region.
A display device comprises a plurality of unit light-emitting devices and the display substrate, wherein the display substrate supplies power to each unit light-emitting device.
Compared with the prior art, the display substrate provided by the invention comprises the second conducting layer, wherein the second conducting layer comprises the polar plate region which is formed on the upper surface of at least one gate region and is electrically connected with the gate region. The positive projection of the polar plate region has an overlapping part with the conductive region of the semiconductor layer, and the conductive region is positioned below the edge of the polar plate region of the part and is not positioned at the interface of the channel region of the semiconductor layer and the conductive region. Meanwhile, the plate region is electrically connected with the gate region, so when a gate voltage is applied, the edge of the plate region is the edge of an electric field caused by the gate voltage. Therefore, the number of hot carriers generated at the interface of the strong electric field edge induced channel region of the grid voltage and the conductive region can be effectively reduced, the hot carrier effect is reduced, and the performance of the display device is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic plan view of a display substrate according to a first embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of the display substrate shown in FIG. 1 taken along the direction A-A';
FIG. 3 is a schematic cross-sectional view of the display substrate shown in FIG. 1 taken along the direction B-B';
FIGS. 4-10 are schematic plan views illustrating a manufacturing process of a display substrate according to a first embodiment of the present invention;
fig. 11 is a schematic plan view of a display substrate according to a second embodiment of the invention;
FIG. 12 is a cross-sectional view of the display substrate shown in FIG. 11 taken along the direction C-C'.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Directional phrases used in connection with the present invention, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. For understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily illustrated, but the present invention is not limited thereto.
It will be understood that when an element such as a layer, panel, or the like is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components.
The technical solutions provided by the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.
First embodiment
The present embodiment provides a display device including: a plurality of unit light emitting devices (not shown), and a display substrate for supplying power to the unit light emitting devices.
In one embodiment, the display device is configured as an organic light emitting display device, the unit light emitting device of which includes an anode, an organic layer, and a cathode. The organic layer comprises a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer and an electron injection layer which are sequentially stacked on the anode. The cathode is arranged on the upper surface of the electron injection layer. The anode and the cathode provide holes and electrons, respectively, to the organic layer. The electron hole pairs are combined in the organic light-emitting layer to generate excitons, and the excitons jump from an excited state to a ground state to release energy to emit light with corresponding colors. Of course, the display device of the present invention is not limited to this embodiment, and may be other forms of display devices.
As shown in fig. 1 and 3, in the present embodiment, the display substrate includes: the semiconductor device includes a substrate 100, a semiconductor layer 200, a gate insulating layer 300, a first conductive layer 400, a first insulating layer 510, a second conductive layer 600, a second insulating layer 520, a third conductive layer 700, a third insulating layer 530, a fourth insulating layer 540, a fourth conductive layer 800, and an insulating planarization layer 900.
The substrate 100 may be a silicon substrate, etc., and a buffer layer (not numbered) may be further formed on the substrate 100 to reduce the number of defects in the semiconductor layer 200 on the upper surface of the substrate 100 and improve the crystallization quality of the semiconductor layer 200.
The semiconductor layer 200 is formed on the upper surface of the substrate 100. In the present embodiment, the material of the semiconductor layer 200 is Low Temperature Polysilicon (LTPS). Since the arrangement of the molecular structure of polycrystalline silicon is orderly and directional, and the electrons can move at a high speed unlike the random arrangement of amorphous silicon, a transistor formed using low-temperature polycrystalline silicon as a semiconductor layer has a high speed. Of course, the semiconductor layer 200 of the present invention may be other types of semiconductors, and is not limited herein. Semiconductor layer 200 includes channel region 210, conductive region 220.
The gate insulating layer 300 is formed on the semiconductor layer 200 and the upper surface of the substrate 100 not covered by the semiconductor layer 200, and may be made of silicon nitride (SiN)x) Or silicon oxide (SiO)2) And the like.
The first conductive layer 400 is formed on the upper surface of the gate insulating layer 300.
In the embodiment shown in fig. 2, the first conductive layer 400, the gate insulating layer 300, and the semiconductor layer 200 form a plurality of thin film transistors including a driving transistor. The first conductive layer 400 includes a number of gate regions 410. Specifically, the gate region 410 is the first conductive layer 400 whose orthographic projection overlaps the channel region 200.
The first insulating layer 510 is formed on the first conductive layer 400 and the upper surface of the gate insulating layer 300 not covered by the first conductive layer 400. A first via a is formed in the first insulating layer 510. Meanwhile, second and third through holes b and c are formed in the first insulating layer 510 and the gate insulating layer 300, that is, the second and third through holes b and c penetrate through the first insulating layer 510 and the gate insulating layer 300. The first through hole a, the second through hole b and the third through hole c are used for realizing electrical connection.
Referring to fig. 1 and 7, a second conductive layer 600 is formed on the upper surface of the first insulating layer 510. The second conductive layer 600 includes a plate region 610 and a non-plate region 620 separated from the plate region 610. In the present embodiment, the plate region 610 is formed on the upper surface of the gate region 410 of the driving transistor and is electrically connected to the gate region 410 through the first through hole a. Of course, the invention is not limited thereto, and in other embodiments, the plate region 610 may also be formed on the upper surface of the gate region 410 of other thin film transistors and electrically connected to the corresponding gate region 410, or the plate region 610 may also be simultaneously formed on the upper surfaces of the gate regions 410 of a plurality of thin film transistors (including a driving transistor), which is not limited in the invention.
Referring to fig. 1, the front projection of the plate region 610 formed on the upper surface of the gate region 410 overlaps with the conductive region 220 of the semiconductor layer 200, i.e., the conductive region is located under the edge of the plate region 610 of the portion, which is not at the interface between the channel region 210 and the conductive region 220 of the semiconductor layer 200. Meanwhile, the plate region 610 is electrically connected to the gate region 410, so that when a gate voltage is applied, the edge of the plate region 610 is the edge of an electric field caused by the gate voltage. Therefore, the embodiment of the invention can effectively reduce the quantity of hot carriers generated at the interface of the strong electric field edge induced channel region of the grid voltage and the conductive region, reduce the hot carrier effect and improve the performance of the display device.
Referring to fig. 2 and 7, the orthographic projection of the gate region 410 of the driving transistor is completely covered by the orthographic projection of the pad region 610 on the upper surface of the gate region 410. Therefore, the range of the electric field caused by the gate voltage of the driving transistor is within the coverage of the plate region 610, and the lower semiconductor layer 200 corresponding to the edge of the plate region 610 is the conductive region 220, which is not at the interface between the channel region 210 of the semiconductor layer 200 and the conductive region 220. Therefore, the present embodiment can further reduce the number of hot carriers generated at the interface between the strong electric field edge induced channel region of the gate voltage and the conductive region, further reduce the hot carrier effect, and further improve the device performance.
Referring to fig. 2 and 7, the plate region 610 also serves as a first substrate of the storage capacitor. Since the first insulating layer 510 is disposed between the second conductive layer 600 and the first conductive layer 400, that is, the second conductive layer 600 and the first conductive layer 400 are formed at different layers, the distribution of the plate region 610 of the second conductive layer 600 is not affected by the traces of the first conductive layer 400. Meanwhile, in the embodiment, the first conductive layer 400 is used as a mask for doping the semiconductor layer 200 to form a conductive region, and the second conductive layer 600 is not used as a mask for doping, so that the distribution of the plate region 610 of the second conductive layer 600 may not be affected by the distribution of the semiconductor layer 200. Therefore, the area of the plate region 610 of the present embodiment can be set according to actual conditions, that is, the area of the storage capacitor can be effectively increased by increasing the area of the plate region 610, thereby improving the device performance.
Referring to fig. 1, 2, and 7, the plate region 610 includes a capacitive region 611 forming an effective storage capacitance and a non-capacitive region 612 connecting the capacitive region. Since the second conductive layer 600 is formed on a different layer from the first conductive layer 400, the non-capacitance region 612 may cross the first conductive layer 400 and be electrically connected to the conductive region 220 of the semiconductor layer 200 through the second via b. The plate region 610 is electrically connected to the gate region 410 and serves as a first substrate of the storage capacitor, and thus the second through hole b is a gate through hole, which is opened in the non-capacitor region 611, so as to effectively increase the area of the capacitor region 611 and further effectively increase the capacitance value of the storage capacitor, compared with the prior art. Meanwhile, in the present embodiment, the non-capacitance region 612 directly crosses over the first conductive layer 400 and is electrically connected to the conductive region 220 of the semiconductor layer 200 through the second via b. Compared with the prior art, the method has the advantages that the metal bridging (both sides needing to be connected are punched, and the punching is performed electrically and reversely) is adopted, so that the punching number is effectively reduced, the technological process is optimized, and the device performance is improved.
Referring to fig. 1, the non-plate region 620 and the plate region 610 belong to the second conductive layer 600, and the non-plate region 620 is electrically connected to the conductive region 220 of the semiconductor layer 200 through the third via c. Similar to the plate area 610, the non-plate area 620 is directly electrically connected to the conductive area 220 through the third through hole c, so that the number of holes is effectively reduced, the process is optimized, and the device performance is improved compared with a metal bridging mode. The non-plate area 620 provides a certain voltage to the plate area 610 through the conductive area 220, so that the storage capacitor has a certain capacitance value, and the gate voltage applied to the driving transistor is adjusted to meet different brightness requirements of the pixel unit.
Referring to fig. 2 and 3, a second insulating layer 520 is formed on the second conductive layer 600 and the upper surface of the first insulating layer 510 not covered by the second conductive layer 600. The second insulating layer 520 serves as an insulating dielectric of the storage capacitor, and its dielectric constant affects the capacitance value of the storage capacitor.
The third conductive layer 700 is located on the upper surface of the second insulating layer 520. The third conductive layer 700, the second insulating layer 520, and the plate region 610 form a storage capacitor. The third conductive layer 700 is a second substrate of the storage capacitor.
The third insulating layer 530 is formed on the third conductive layer 700 and the upper surface of the second insulating layer 520 not covered by the third conductive layer 700. The fourth insulating layer 540 is formed on the upper surface of the third insulating layer 530. The third insulating layer 530 and the fourth insulating layer 540 collectively perform an insulating passivation function. A hole is formed through the third insulating layer 530 and the fourth insulating layer 540 to form a conductive via for electrical connection.
The fourth conductive layer 800 is formed on the upper surface of the fourth insulating layer 540. The fourth conductive layer 900 is used to electrically connect to the underlying conductive layers through the conductive vias. For example, the fourth conductive layer 800 is electrically connected to the third conductive layer 700 serving as the second substrate of the storage capacitor through the conductive via d, so as to provide a fixed voltage to the upper substrate of the storage capacitor.
The insulating planarization layer 900 is formed on the fourth conductive layer 800 and the upper surface of the fourth insulating layer 540 not covered by the fourth conductive layer 800. A light emitting unit is prepared on the upper surface of the insulating planarization layer 900, such as an anode, a hole injection layer, a hole transport layer, a hole blocking layer, a light emitting material layer, an electron blocking layer, an electron transport layer, an electron injection layer, and a cathode, which may be stacked in this configuration on the upper surface of the insulating planarization layer 900. In other embodiments, the light emitting unit may be implemented in other forms such as an LCD light emitting unit, a QLED light emitting unit, etc., and then packaged to form the display device of the present embodiment.
Referring to fig. 4 to 10, the method for manufacturing a display substrate of the present embodiment includes the following steps:
step one, a substrate 100 is provided, and a semiconductor layer 200 is formed on the upper surface of the substrate 100, referring to fig. 4.
Step two, forming a gate insulating layer 300 on the semiconductor layer 200 and the upper surface of the substrate 100 not covered by the semiconductor layer 200, and forming a first conductive layer 400 on the upper surface of the gate insulating layer 300, wherein the first conductive layer 400 includes a plurality of gate regions 410, and the orthographic projections of the plurality of gate regions 410 have a plurality of overlapping portions with the semiconductor layer 200, refer to fig. 5.
The number of gate regions 410 includes the gate region 410 of the drive transistor.
Step three, doping the semiconductor layer 200 with the first conductive layer 400 as a mask to form the conductive region 220, referring to fig. 5.
The gate regions 410 overlap with the semiconductor layer 200 in the orthographic projection, so that when the semiconductor layer 200 is doped, the portion covered by the gate regions 410 of the first conductive layer 400 is not doped, and the channel region 210 is formed. While the portion not covered by the first conductive layer 400 is doped to form the conductive region 220.
And fourthly, forming an electrode plate region 610 which is electrically connected with the gate region 410 and has an overlapped part with the conductive region 220 in the orthographic projection on the upper surface of at least one gate region 410.
In this embodiment, a plate region 610 is formed on the upper surface of the gate region 410 of the driving transistor, and the specific process is as follows:
first, a first insulating layer 510 is formed on the first conductive layer 400 and the upper surface of the gate insulating layer 300 not covered by the first conductive layer 400;
then, holes are punched in the first insulating layer 510 to form first via holes a, and second via holes b and third via holes c penetrating the first insulating layer 510 and the gate insulating layer 300 are simultaneously formed in the first insulating layer 510 and the gate insulating layer 300, referring to fig. 6;
then, a conductive material is deposited to form a plate region 610 on the upper surface of the first insulating layer 510, and a non-plate region 620 separated from the plate region 610 is formed, wherein the plate region 610 and the non-plate region together form a second conductive layer 600. The plate region 610 includes a capacitive region 611 forming an effective storage capacitance and a non-capacitive region 612 connecting the capacitive region. The capacitor region 611 is electrically connected to the gate region 410 of the driving transistor through the first through hole a. The non-capacitor region 612 spans the first conductive layer 400 and is electrically connected to the conductive region 220 of the semiconductor layer 200 through the second via b. The non-electrode region 620 is electrically connected to the conductive region 220 of the semiconductor layer 200 through the third via c, referring to fig. 7.
Step five, forming a second insulating layer 520 on the second conductive layer 600 and the upper surface of the first insulating layer 510 not covered by the second conductive layer 600, and forming a third conductive layer 700 on the upper surface of the second insulating layer 520, refer to fig. 8.
The third conductive layer 700, the second insulating layer 520, and the plate region 610 form a storage capacitor.
Step six, a third insulating layer 530 is formed on the third conductive layer 700 and the upper surface of the second insulating layer 520 not covered by the third conductive layer 700. A fourth insulating layer 540 is formed on the upper surface of the third insulating layer 530, and a punching process is performed to form a conductive via penetrating to each conductive layer of the lower layer, referring to fig. 9.
The conductive vias include the conductive vias d mentioned above.
Step seven, forming a fourth conductive layer 800 on the upper surface of the fourth insulating layer 540, referring to fig. 10.
The fourth conductive layer 800 is electrically connected to the underlying conductive layers through the conductive vias, for example, the third conductive layer 700 serving as the second substrate of the storage capacitor through the conductive via d.
Step eight, forming an insulating planarization layer 900 on the fourth conductive layer 800 and the upper surface of the fourth insulating layer 540 not covered by the fourth conductive layer 800.
After the fourth conductive layer 800 is formed, the insulating planarization layer 900 is formed on the display substrate of the present invention, and the unit light emitting device is formed on the upper surface of the insulating planarization layer 900, thereby forming the display device of the present invention.
In this embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are all made of metal materials, but the invention is not limited thereto, and in other embodiments, the materials of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may also be made of other conductive materials such as alloy, nitride of metal material, oxide of metal material, and oxynitride of metal material, which is not limited in this respect.
Second embodiment
Referring to fig. 11 and 12, the present embodiment is similar to the first embodiment, except that:
the first conductive layer 400 is different from the second conductive layer 600 in material. No first insulating layer 510 is formed between the second conductive layer 600 and the first conductive layer 400, i.e. the plate region 610 is in direct contact with the gate region 410, thereby achieving electrical connection.
The first conductive layer 400 and the second conductive layer 600 are made of different materials, so that when no first insulating layer 510 is formed between the second conductive layer 600 and the first conductive layer 400, the first conductive layer 400 is prevented from being etched when the second conductive layer 600 is subjected to patterning etching, and further, the device performance is prevented from being affected. Specifically, in this embodiment, the material of the first conductive layer 400 is metal, and the material of the second conductive layer is Indium Tin Oxide (ITO). The ITO layer is wet etched by oxalic acid, the metal etching rate of the oxalic acid is low, and the first conducting layer 400 is prevented from being over etched.
In this embodiment, since no first insulating layer 510 is formed between the second conductive layer 600 and the first conductive layer 400, it is necessary to prevent the second conductive layer 600 from being shorted with the first conductive layer 400 outside the gate region 410 under the non-polar plate region 610, that is, the second conductive layer 600 and the first conductive layer 400 outside the gate region 410 under the non-polar plate region 610 need to keep a proper distance. However, the present embodiment is the same as the first embodiment, and the conductive region is formed by doping the semiconductor layer 200 using the first conductive layer 400 as a mask, and the second conductive layer 600 is not doped with the mask. Therefore, the distribution of the plate region 610 of the second conductive layer 600 may not be affected by the distribution of the semiconductor layer 200, so that the area of the plate region 610 may be set according to actual conditions, that is, the area of the storage capacitor may be effectively increased by increasing the area of the plate region 610, thereby improving device performance.
The second conductive layer 600 includes only the plate region 610, and the plate region 610 includes only the capacitor region.
Since the plate region 610 is in direct contact with the gate region 410, and the second conductive layer 600 only includes the plate region 610, and the plate region 610 only includes the capacitor region 611, the first through hole a, the second through hole b, and the third through hole c do not need to be formed in the manufacturing process of the plate region 610 which is electrically connected to the gate region 410 on the upper surface of the gate region 410 and has an overlapping portion with the conductive region 220 in the orthogonal projection. For the purpose of providing the voltage signal to the first substrate (i.e. the plate region 610, i.e. the second conductive layer 600) of the storage capacitor, the third conductive layer 700 of the embodiment includes a substrate region 710 (the third conductive layer 700 of the first embodiment of the invention is the substrate region 710), and further includes a non-substrate region 720 insulated and separated from the substrate region 710. The substrate region 710, the second insulating layer 520, and the plate region 610 form a storage capacitor. The substrate region 710 serves as a second substrate of the storage capacitor. Then, before forming the fourth metal layer 800, a punching process is performed to form conductive vias penetrating to the underlying conductive layers. The conductive vias include the conductive vias d mentioned above. And a gate via b 'formed on the upper surface of the plate region 610 (where the substrate region 710 on the upper surface of the plate region 610 is formed to reserve the gate via b'), and a first portion of the fourth metal layer electrically connects the plate region 610 and the conductive region 220 through the first via b ″ and the gate via b 'is formed on the upper surface of the conductive region 220 of the semiconductor layer 200 near the plate region 610 to form a first connection hole b'. Meanwhile, a second connection hole c 'is formed on the upper surface of the non-substrate region 720, a third connection hole c is formed in a conductive region of the semiconductor layer 200 near the non-substrate region 720, a second portion of the fourth metal layer, which is insulated and separated from the first portion, is electrically connected to the non-substrate region 720 and the conductive region 220 through the second connection hole c' and the third connection hole c ″, and then the non-substrate region 720 and the plate region 610 are electrically connected to provide a voltage signal to the plate region 610, so that the storage capacitor has a certain capacitance value, and the gate voltage applied to the driving transistor is adjusted to meet different brightness requirements of the pixel unit.
In summary, the display substrate provided by the present invention includes a second conductive layer, where the second conductive layer includes a plate region formed on the upper surface of at least one gate region and electrically connected to the gate region. The positive projection of the polar plate region has an overlapping part with the conductive region of the semiconductor layer, and the conductive region is positioned below the edge of the polar plate region of the part and is not positioned at the interface of the channel region of the semiconductor layer and the conductive region. Meanwhile, the plate region is electrically connected with the gate region, so when a gate voltage is applied, the edge of the plate region is the edge of an electric field caused by the gate voltage. Therefore, the number of hot carriers generated at the interface of the strong electric field edge induced channel region of the grid voltage and the conductive region can be effectively reduced, the hot carrier effect is reduced, and the performance of the display device is improved.
The above embodiments are intended to illustrate the objects, aspects and advantages of the present invention, and it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A display substrate, comprising:
a substrate;
the semiconductor layer is formed on the upper surface of the substrate and comprises a channel region and a conductive region;
the gate insulating layer is formed on the semiconductor layer and the upper surface of the substrate which is not covered by the semiconductor layer;
the first conducting layer is formed on the upper surface of the gate insulating layer and comprises a plurality of gate regions with overlapped parts of orthographic projections and the channel regions;
a second conductive layer comprising a plate region; the polar plate region is formed on the upper surface of at least one gate region and is electrically connected with the gate region, and the orthographic projection of the polar plate region has an overlapping part with the conductive region.
2. The display substrate of claim 1, wherein the gate region orthographic projection edge is located entirely within the plate region of the gate region upper surface.
3. The display substrate according to claim 1, wherein a first insulating layer is formed between the second conductive layer and the first conductive layer, a first through hole is formed in the first insulating layer, and the gate plate region and the gate region are electrically connected through the first through hole.
4. The display substrate of claim 3, wherein the first conductive layer, the gate insulating layer and the semiconductor layer form a plurality of thin film transistors, the plurality of thin film transistors comprise a driving transistor, and the plate region is formed on an upper surface of a gate region of the driving transistor.
5. The display substrate of claim 4, wherein a second via hole is formed in the first insulating layer and the gate insulating layer, the plate region comprises a capacitor region forming an effective storage capacitor and a non-capacitor region connected to the capacitor region, and the non-capacitor region is electrically connected to the conductive region through the second via hole.
6. The display substrate of claim 5, wherein the second conductive layer further comprises a non-polar plate region separated from the polar plate region, wherein a third via hole is formed in the first insulating layer and the gate insulating layer, and the non-polar plate region is electrically connected to the conductive region through the third via hole.
7. The display substrate of claim 1, wherein the first conductive layer is of a different material than the second conductive layer, and wherein the plate region is in direct contact with the gate region.
8. The display substrate of claim 7, wherein the first conductive layer is made of metal and the second conductive layer is made of indium tin oxide.
9. The method of manufacturing a display substrate according to any one of claims 1 to 8, comprising the steps of:
providing a substrate, and forming a semiconductor layer on the upper surface of the substrate;
forming a gate insulating layer on the semiconductor layer and the upper surface of the substrate which is not covered by the semiconductor layer, and forming a first conducting layer on the upper surface of the gate insulating layer, wherein the first conducting layer comprises a plurality of gate regions, and the orthographic projections of the gate regions and the semiconductor layer are provided with a plurality of overlapped parts;
doping the semiconductor layer by taking the first conductive layer as a mask to form a conductive region;
and forming a polar plate region which is electrically connected with the gate region and has an overlapped part with the conductive region in the orthographic projection on the upper surface of the at least one gate region.
10. A display device comprising a plurality of unit light emitting devices, further comprising the display substrate of any one of claims 1-8, the display substrate powering each unit light emitting device.
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