CN108346440A - The control circuit of bias generating circuit and memory - Google Patents
The control circuit of bias generating circuit and memory Download PDFInfo
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- CN108346440A CN108346440A CN201710060974.2A CN201710060974A CN108346440A CN 108346440 A CN108346440 A CN 108346440A CN 201710060974 A CN201710060974 A CN 201710060974A CN 108346440 A CN108346440 A CN 108346440A
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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Abstract
The present invention provides the control circuits of a kind of bias generating circuit and memory, including：First power-on sequence and the second power-on sequence.In first power-on sequence, first voltage signal is generated by the first electrification circuit, and charge pump generates pump bias when first voltage signal reaches the first predetermined voltage；In the second power-on sequence, second voltage signal is generated by second power-on sequence, and bias switch is opened when second voltage signal reaches the second predetermined voltage, the pump bias that the charge pump generates is exported via the bias switch to form output bias.Wherein, the time that the second voltage signal reaches the second predetermined voltage is later than the time that the first voltage signal reaches the first predetermined voltage.In bias generating circuit provided by the invention, by two power-on sequences, the purpose for faster forming stable output bias is realized.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to the control circuit of a kind of bias generating circuit and memory.
Background technology
Memory is when executing corresponding operation, such as read operation, erasing operation etc., need to be applied in its memory cell array
A bias, the bias is added to be provided generally by a bias generating circuit.
The bias generating circuit generates bias according to a voltage signal.That is, when voltage signal reaches its predetermined voltage,
Then bias generating circuit is connected, so as to generate bias.Wherein, the voltage value of generated voltage signal is not direct
Reach its scheduled voltage, that is to say, that when starting to generate voltage signal, voltage value is usually relatively low, and bias generates at this time
Circuit is not turned on；Over time, the voltage value of generated voltage signal gradually rises, and reaches its predetermined voltage
When, the bias generating circuit is connected and starts to provide bias.
However, the device for controlling bias generating circuit conducting, since it is influenced by each factor (for example, shape
At technique or environment temperature etc.), the conducting state of device and unstable in the initial state, to make bias generating circuit at it
The starting stage of conducting cannot provide the bias of a stabilization, if unstable bias is directly applied in memory cell array,
The phenomenon that easily leading to maloperation.
Invention content
The purpose of the present invention is to provide the control circuits of a kind of bias generating circuit and MTP devices, existing to solve
Bias generating circuit can not quickly lead to the problem of stable bias.
In order to solve the above technical problems, the present invention provides a kind of bias generating circuit, including：
First power-on sequence, first power-on sequence include the first electrification circuit and charge pump, and described first powers on electricity
Road generates first voltage signal, and when the first voltage signal reaches the first predetermined voltage, the charge pump generates pump bias；
Second power-on sequence, second power-on sequence include the second electrification circuit and bias switch, and described second powers on
Circuit generates second voltage signal, and when the second voltage signal reaches the second predetermined voltage, the bias switch is opened, institute
The pump bias for stating charge pump generation is exported via the bias switch to form output bias；
Wherein, the time that the second voltage signal reaches the second predetermined voltage is later than the first voltage signal and reaches
The time of one predetermined voltage.
Optionally, first power-on sequence further includes the first transistor, the grid of the first transistor and described the
The output end of one electrification circuit connects, and the source electrode of the first transistor is connect with the charge pump, the first transistor
Grounded drain.
Optionally, the first transistor is N-type transistor.
Optionally, second power-on sequence further includes second transistor, the grid of the second transistor and described the
The output end of two electrification circuits connects, and the source electrode of the second transistor is connect with the bias switch, the second transistor
Grounded drain.
Optionally, the second transistor is N-type transistor.
Optionally, first power-on sequence further includes the first phase inverter, and first phase inverter is connected to described first
Between electrification circuit and the charge pump.
Optionally, second power-on sequence further includes the second phase inverter, and second phase inverter is connected to described second
Between electrification circuit and the bias switch.
Optionally, first power-on sequence further includes clock generator, the output end of the clock generator with it is described
Charge pump connects, and when the first voltage signal reaches the first predetermined voltage, the clock generator generates clock signal, institute
It states charge pump and generates pump bias using the clock signal.
Optionally, the charge pump is negative charge pump or positive charge pump.
Optionally, the bias switch is that positively biased compresses switch or negative bias compresses switch.
It is a further object of the present invention to provide a kind of control circuits of memory, including bias as described above to generate
Circuit and memory cell array, the bias generating circuit generate bias and are applied to the memory cell array.
Optionally, the memory is MTP memories.
Optionally, the storage memory cell array is p-type memory cell array.
Optionally, when executing read operation, the bias generating circuit generates back bias voltage and is applied to the storage unit
In the selection grid of array.
Optionally, when executing erasing operation, the bias generating circuit generates positive bias and is applied to the storage list
In the selection grid of element array.
In bias generating circuit provided by the invention, there are two power-on sequence, the first voltages of the first electrification circuit to believe for tool
Number preferentially reach the first predetermined voltage (the first power-on reset signal), charge pump is made to start to generate pump bias；It can be produced in pump bias
After raw stable bias, the second voltage signal of the second electrification circuit reaches the second predetermined voltage (the second electrification reset letter
Number), control bias switch makes it open to export stable output bias.Also, it can be by the first predetermined voltage and second
The voltage value of predetermined voltage is configured, and the time of power up is executed to adjust the first power-on sequence and the second power-on sequence
Difference.And the voltage value by the way that the first power-on reset signal is arranged, the pump that starts to execute of charge pump earlier can also operated, into
And achieve the purpose that faster form stable output bias.The output generated due to the bias generating circuit in the present invention
Bias is therefore stable bias is applied in memory when by the bias generating circuit to realize the corresponding of memory
When operation, it can effectively avoid and the phenomenon that maloperation occur.
Description of the drawings
Fig. 1 is a kind of schematic diagram of the control circuit of memory；
Fig. 2 is the schematic diagram of the bias generating circuit in one embodiment of the invention；
Fig. 3 is bias sequence diagram of the existing bias generating circuit when generating bias；
Fig. 4 is bias sequence diagram of the bias generating circuit when generating bias in the present invention；
Fig. 5 is the schematic diagram of the control circuit of the memory in one embodiment of the invention.
Specific implementation mode
As stated in the background art, existing bias generating circuit can not provide the inclined of a stabilization in the starting stage of its conducting
Pressure.To when unstable bias to be directly applied in memory cell array, then easily cause to occur the phenomenon that maloperation.
Fig. 1 is a kind of control circuit of memory, including bias generating circuit 10 and memory cell array 20, by described
Bias generating circuit 10 generates bias and is applied in the memory cell array 20, to be grasped accordingly to the memory
Make.Wherein, the bias generating circuit 10 includes：Electrification circuit (Power Up Circuit) 11, the electrification circuit 11 produce
A raw voltage signal Vpw, and when the voltage signal Vpw reaches predetermined voltage, the predetermined voltage Vpw forms electrification reset
Signal POR, so that the bias generating circuit 10 is connected；Charge pump (Charge Pump) 12, the charge pump 12 is according to powering on
The voltage signal that circuit 11 generates generates pump bias Vp.
When the bias generating circuit 10 is started to work, the electrification circuit 11 generates a voltage signal gradually increased
Vpw, when the voltage signal Vpw rises to predetermined voltage (power-on reset signal POR), charge pump 12 starts to execute pump operation
(Starting pump) and generate pump bias Vp.Wherein, it due to being influenced by its formation process or environment temperature, is used in
The conducting state of the device of control bias generating circuit conducting is simultaneously unstable, can not so as to cause power-on reset signal POR
Variation is even generated by control well, and then the conducting state of bias generating circuit 10 is impacted, causes to operate in pump
Starting stage caused by pump bias Vp it is unstable.Also, in bias generating circuit shown in FIG. 1, also need by longer
Time could generate stable bias.
For this purpose, the present invention provides a kind of bias generating circuit, including：
First power-on sequence, first power-on sequence include the first electrification circuit and charge pump, and described first powers on electricity
The output end on road is connect with the charge pump, and first electrification circuit generates first voltage signal, when the first voltage is believed
When number reaching the first predetermined voltage, the charge pump generates pump bias；
Second power-on sequence, second power-on sequence include the second electrification circuit and bias switch, and described second powers on
The output end of circuit is connect with the bias switch, and second electrification circuit generates second voltage signal, when second electricity
When pressure signal reaches the second predetermined voltage, the bias switch is opened, and the pump bias that the charge pump generates is via the bias
Switch output is to form output bias；
Wherein, the time that the second voltage signal reaches the second predetermined voltage is later than the first voltage signal and reaches
The time of one predetermined voltage.
In bias generating circuit provided by the invention, there are two power-on sequences for tool, and it is inclined to generate pump by the first power-on sequence
Pressure controls the output of bias to form output bias by the second power-on sequence.Wherein, the first voltage letter of the first electrification circuit
Number preferentially reach the first predetermined voltage (the first power-on reset signal), makes charge pump start to generate pump bias, and in charge pump
Unstable bias caused by the starting stage of pump operation is executed without output；As pump bias caused by charge pump tends to
Stablize, the second voltage signal of the second electrification circuit reaches the second predetermined voltage (the second power-on reset signal), and bias switch is beaten
It opens so that the pump bias stablized exports to form output voltage.That is, the present invention can exist to charge pump by using two power-on sequences
Unstable pump bias caused by its starting stage is filtered, it is ensured that output bias is the bias of stabilization.
Below in conjunction with the drawings and specific embodiments to the control circuit of bias generating circuit proposed by the present invention and memory
It is described in further detail.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted
That attached drawing is all made of very simplified form and uses non-accurate ratio, only to it is convenient, lucidly aid in illustrating this hair
The purpose of bright embodiment.
Fig. 2 is the schematic diagram of the bias generating circuit in one embodiment of the invention, as shown in Fig. 2, the bias generates electricity
Road 100 includes：
First power-on sequence 110, first power-on sequence 110 include the first electrification circuit 111 and charge pump 112, institute
The output end for stating the first electrification circuit 111 is connect with the charge pump 112, and first electrification circuit 111 generates first voltage
Signal Vpw1, when the first voltage signal Vpw1 reaches the first predetermined voltage, the charge pump 112 generates pump bias；That is,
When the first voltage signal Vpw1 reaches the first predetermined voltage, which is used as the first power-on reset signal
POR1, so that the first power-on sequence is connected；
Second power-on sequence 120, second power-on sequence 120 include the second electrification circuit 121 and bias switch 122,
The output end of second electrification circuit 121 is connect with the bias switch 122, and second electrification circuit 121 generates second
Voltage signal Vpw2, when the second voltage signal Vpw2 reaches the second predetermined voltage, the bias switch 122 is opened, institute
The pump bias Vp for stating the generation of charge pump 112 is exported via the bias switch 122 to form output bias Vout；That is, when described
When second voltage signal Vpw2 reaches the second predetermined voltage, which is used as the second power-on reset signal POR2,
So that the second power-on sequence is connected.
Wherein, the time that the second voltage signal Vpw2 reaches the second predetermined voltage is later than the first voltage signal
Vpw1 reaches the time of the first predetermined voltage, and therefore, the first power-on sequence 110 can be executed prior to the second power-on sequence 120
Electric process makes the unstable bias caused by the starting stage of its pump operation of charge pump 112 that can not export；With being applied to electricity
Voltage signal on lotus pump 112 is gradually stablized, and makes the pump charge 112 that can generate stable bias, second power-on sequence 120
Just start to execute power up, can ensure that the bias of output is stable bias at this time.
It can be seen that first electrification circuit 111 generate time of the first predetermined voltage Vpw1 earlier than described second on
Circuit 121 generates the time of the second predetermined voltage Vpw2, that is, forms the first power-on reset signal POR1 and formation second powers on
Reset signal POR2 existence times are poor, it is thus ensured that the bias of output is stable bias.Certainly, in actual application
In, it can be according to actual demand to forming the time of the first electrification reset model POR1 and forming the second power-on reset signal POR2's
Time is configured.For example, the first electrification circuit 111 and the second electrification circuit 121 generate positive voltage signal, power on first
The first voltage signal Vpw1 that circuit 111 generates gradually increases, and reaches the first predetermined voltage (the first power-on reset signal
POR1)；With the raising of voltage, the second voltage signal Vpw2 that the second electrification circuit 121 generates gradually increases, and reaches second
Predetermined voltage (the second power-on reset signal POR2).It therefore, can be by setting the first predetermined voltage Vpw1 and the second predetermined voltage
Vpw2, making the two, there are certain voltage differences, to make to be formed the time of the first power-on reset signal POR1 and be formed on second
The time of reset signal POR2 has differences, and realizes that two power-on sequences execute power up in the different time.Alternatively,
The voltage value that the first predetermined voltage Vpw1 can be reduced makes charge pump 112 more to generate the first power-on reset signal POR1 faster
Early starts to execute pump operation, and then can form stable bias in a relatively short period of time, realizes quickly to generate and stablizes bias
Purpose.
Shown in Fig. 2, first power-on sequence 110 further includes the first transistor 113, the first transistor
113 grid is connect with the output end of first electrification circuit 111, the source electrode of the first transistor 113 and the charge
112 connection of pump.That is, first electrification circuit 111, charge pump 112 and the first transistor 113 form a conducting circuit, into
And the power up of first power-on sequence 110 can be realized by controlling the conducting of the first transistor 113.Specifically
It says, when the first voltage signal Vpw1 being applied on the grid of the first transistor 113 reaches its threshold voltage, at this time
First voltage signal Vpw1 caused by one electrification circuit 110 reaches its first predetermined voltage, and the first transistor 113 is led
Logical, first power-on sequence 110 starts to execute power up.Further, the first transistor can be N-type crystal
Pipe.
Further, first power-on sequence 110 further includes the first phase inverter 114, and first phase inverter 114 connects
Between first electrification circuit 110 and the charge pump 112.Further, first power-on sequence 110 further includes
Clock generator 115.In the present embodiment, the output of the input terminal of first phase inverter 114 and first electrification circuit 111
End connection, the output end of first phase inverter 114 are connect with the input terminal of the clock generator 115, and, the clock
The output end of generator 115 is connect with the input terminal of the charge pump 112.In the work course, the first electrification circuit 111 produces
Raw first voltage signal Vpw1 is after-applied in occurring, the clock on clock generator 115 through first phase inverter 114
Device 115 generates a clock signal, and the clock signal is applied in the charge pump 112, and then makes the charge pump 112 can profit
Pump bias Vp is generated with the clock signal.
Shown in Fig. 2, the output end of the charge pump 112 is connect with the input terminal of the bias switch 122,
That is, when the bias switch 122 is opened, the pump bias Vp that the charge pump 112 generates is defeated by the bias switch 122
Go out.Wherein, the bias generating circuit 100 can be used for generating positive bias, it can also be used to generate back bias voltage.When for generating negative bias
When pressure, negative charge pump can be set for generating negative pump bias；Correspondingly, when for generating positive bias, positive charge can be set
Pump just pumps bias for generating.
In the present embodiment, the first power-on sequence 110 is by the conducting of controlling transistor to realize its power up.Cause
This, in the first power-on sequence 110, when first voltage signal Vpw1 reaches the first prearranged signals, due to the first transistor 113
The influence of the factors such as technique, temperature easily makes the conducting of the first transistor 113 unstable, and then charge pump 112 is caused to be held at it
The starting stage of row pump operation can not generate stable pump bias.And pass through the second beating to bias switch 122 of power-on sequence 120
It is open and close to be controlled, can make charge pump generate unstable bias without output, only export stable bias, avoid by
The influence of transistor switch.
Similar with the first power-on sequence 110, second power-on sequence 120 may also comprise a second transistor 123, lead to
Cross the power up for conducting the second power-on sequence 120 of realization for controlling the second transistor 123.As shown in Fig. 2, described second
The grid of transistor 123 is connect with the output end of second electrification circuit 121, the source electrode of the second transistor 123 and institute
State the connection of bias switch 122.That is, making a reservation for when the second voltage signal Vpw2 that second electrification circuit 121 generates reaches second
When voltage, the second transistor 123 is connected, and the bias switch 122 is opened.Specifically, the second transistor 123 also may be used
Think N-type transistor.
In the present embodiment, second power-on sequence 120 also includes one second phase inverter 124, second phase inverter 124
It is connected between second electrification circuit 121 and the bias switch 122.That is, second electrification circuit 120 generate the
Two voltage signal Vpw2 are after-applied in the bias switch 122 through second phase inverter 124, and then can control the bias
Switch 122 is turned on and off.Further, in the present embodiment, the bias switch 122 can be that positive bias switchs, and also may be used
Think that negative bias compresses switch, as long as the bias switch 122 is opened after the charge pump 112 executes pump operation, with output
Stable output bias.
Fig. 3 is the sequence diagram that existing bias generating circuit generates bias, and Fig. 4 is the bias generating circuit production in the present invention
The sequence diagram of raw bias, wherein VDD is the supply voltage being applied on the first electrification circuit and the second electrification circuit, so that its
First voltage signal Vpw1 and second voltage signal Vpw2 is generated respectively；Abscissa represents the time, and ordinate represents voltage value.Knot
Fig. 3 and Fig. 4 is closed it is found that in existing bias generating circuit, since electrification circuit is replied by cable to be formed generating voltage signal Vpw
When the signal POR of position, since power-on reset signal POR will produce certain fluctuation, charge pump is made to form unstable bias.And this
It is preferential to generate the first power-on reset signal POR1 and steady in the first power-on reset signal POR1 in the bias generating circuit of invention
On the basis of fixed, start to generate the second power-on reset signal POR2, makes the voltage that the output voltage Vout of output is stable.And
And the present invention in, the voltage value of the first predetermined voltage Vpw1 is turned down, so can be earlier the first power-on reset signal of formation
POR1 simultaneously executes pump operation (starting pump), realizes the purpose for quickly generating and stablizing bias.
Based on above-described bias generating circuit, the present invention also provides a kind of control circuit of MTP devices, including it is above
The bias generating circuit and memory cell array, the bias generating circuit generate bias and are applied to the storage list
On element array.
Fig. 5 is the schematic diagram of the control circuit of the memory in one embodiment of the invention, as shown in figure 5, the memory
Control circuit include bias generating circuit and memory cell array 200.Wherein, the bias generating circuit includes：
First power-on sequence 110, first power-on sequence 110 include the first electrification circuit 111 and charge pump 112, institute
The output end for stating the first electrification circuit 111 is connect with the charge pump 112, and first electrification circuit 111 generates first voltage
Signal Vpw1, when the first voltage signal Vpw1 reaches the first predetermined voltage, the charge pump 112 generates pump bias；
Second power-on sequence 120, second power-on sequence 120 include the second electrification circuit 121 and bias switch 122,
The output end of second electrification circuit 121 is connect with the bias switch 122, and second electrification circuit 121 generates second
Voltage signal Vpw2, when the second voltage signal Vpw2 reaches the second predetermined voltage, the bias switch 122 is opened, institute
The pump bias Vp for stating the generation of charge pump 112 is exported via the bias switch 122 to form output bias Vout；
Wherein, the time that the second voltage signal Vpw2 reaches the second predetermined voltage is later than the first voltage signal
Vpw1 reaches the time of the first predetermined voltage.
As described above, bias generating circuit can quickly generate stable output bias, the output bias of the stabilization is applied
It is added in the memory cell array 200 precise manipulation, it can be achieved that storage unit, is avoided due to the first power-on reset signal
POR1 leads to the problem of larger fluctuation and leads to maloperation.Wherein, the storage unit in the memory cell array 200 includes
Selection gate SG, wordline WL, source line SL and bit line BL.
Specifically, the bias generating circuit can be used for generating back bias voltage, it can also be used to positive bias is generated, therefore, according to
Physical storage type or according to different operations, the bias generating circuit can be applied to different occasions.The present embodiment
In, the bias generating circuit is applied in MTP devices, for realizing the read operation of MTP devices or erasing operation etc..With
For memory cell array in MTP devices is p-type memory cell array, when the MTP devices need to execute read operation, it can lead to
Overbias generation circuit generates back bias voltage, and is applied in the selection grid of the memory cell array 200；When the MTP devices
When need to execute read operation, positive bias can be generated by bias generating circuit, and be applied to the selection grid of the memory cell array
On.In the present embodiment, the memory is MTP memories, and in other embodiments, the memory cocoa is with for other classes
Memory of type, for example, OTP (disposable programmable memory) etc., are not limited herein.
In conclusion in bias generating circuit provided by the invention, there are two power-on sequence, the controls of the first power-on sequence for tool
The pump charge makes it generate pump bias, and after pump bias can generate stable bias, the second power-on sequence control bias is opened
Pass makes it open to export stable output bias.It specifically can be by the first power-on reset signal and the second power-on reset signal
Voltage be configured, to adjust the time difference that the first power-on sequence and the second power-on sequence execute power up.Also, it can lead to
The voltage value of the first power-on reset signal of setting is crossed, so that charge pump can be earlier starts to execute pump operation, and then reaching can be more
Quickly form the purpose of stable output bias.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (17)
1. a kind of bias generating circuit, which is characterized in that including：
First power-on sequence, first power-on sequence include the first electrification circuit and charge pump, the first electrification circuit production
Raw first voltage signal, when the first voltage signal reaches the first predetermined voltage, the charge pump generates pump bias；
Second power-on sequence, second power-on sequence include the second electrification circuit and bias switch, second electrification circuit
Second voltage signal is generated, when the second voltage signal reaches the second predetermined voltage, the bias switch is opened, the electricity
The pump bias that lotus pump generates is exported via the bias switch to form output bias；
Wherein, the time that the second voltage signal reaches the second predetermined voltage is later than the first voltage signal and reaches first in advance
The time of constant voltage.
2. bias generating circuit as described in claim 1, which is characterized in that first power-on sequence further includes first crystal
Pipe, the grid of the first transistor connect with the output end of first electrification circuit, the source electrode of the first transistor and
The charge pump connection, the grounded drain of the first transistor.
3. bias generating circuit as claimed in claim 2, which is characterized in that the first transistor is N-type transistor.
4. bias generating circuit as described in claim 1, which is characterized in that second power-on sequence further includes the second crystal
Pipe, the grid of the second transistor connect with the output end of second electrification circuit, the source electrode of the second transistor and
The bias switch connection, the grounded drain of the second transistor.
5. bias generating circuit as claimed in claim 4, which is characterized in that the second transistor is N-type transistor.
6. bias generating circuit as described in claim 1, which is characterized in that first power-on sequence further includes the first reverse phase
Device, first phase inverter are connected between first electrification circuit and the charge pump.
7. bias generating circuit as described in claim 1, which is characterized in that second power-on sequence further includes the second reverse phase
Device, second phase inverter are connected between second electrification circuit and the bias switch.
8. bias generating circuit as described in claim 1, which is characterized in that first power-on sequence further includes clock
Device, the output end of the clock generator are connect with the charge pump, when the first voltage signal reaches the first predetermined voltage
When, the clock generator generates clock signal, and the charge pump generates pump bias using the clock signal.
9. bias generating circuit as described in claim 1, which is characterized in that the charge pump is negative charge pump.
10. bias generating circuit as described in claim 1, which is characterized in that the charge pump is positive charge pump.
11. bias generating circuit as described in claim 1, which is characterized in that the bias switch compresses switch for positively biased.
12. bias generating circuit as described in claim 1, which is characterized in that the bias switch compresses switch for negative bias.
13. a kind of control circuit of memory, which is characterized in that include the bias production as described in one of claim 1-12
Raw circuit and memory cell array, the bias generating circuit generate bias and are applied in the memory cell array.
14. the control circuit of memory as claimed in claim 13, which is characterized in that the memory is MTP memories.
15. the control circuit of memory as claimed in claim 14, which is characterized in that the storage memory cell array is P
Type memory cell array.
16. the control circuit of memory as claimed in claim 15, which is characterized in that when executing read operation, the bias
Generation circuit generates back bias voltage and is applied in the selection grid of the memory cell array.
17. the control circuit of MTP devices as claimed in claim 15, which is characterized in that described inclined when executing erasing operation
Pressure generation circuit generates positive bias and is applied in the selection grid of the memory cell array.
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| OSAMA KHOURI等: "Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories", 《ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING》 * |
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