CN108336722B - Parallel surge suppression circuit - Google Patents
Parallel surge suppression circuit Download PDFInfo
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- CN108336722B CN108336722B CN201810323928.1A CN201810323928A CN108336722B CN 108336722 B CN108336722 B CN 108336722B CN 201810323928 A CN201810323928 A CN 201810323928A CN 108336722 B CN108336722 B CN 108336722B
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- 230000001629 suppression Effects 0.000 title claims abstract description 37
- 238000005070 sampling Methods 0.000 claims description 33
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 5
- 230000001012 protector Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
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Abstract
The invention provides a parallel surge suppression circuit which comprises a controller, a first switching tube and a second switching tube, wherein the control ends of the first switching tube and the second switching tube are electrically connected with the controller so as to be turned on or off under the control of the controller, the on-resistance of the second switching tube is smaller than that of the first switching tube, the single avalanche energy of the first switching tube is higher than that of the second switching tube, and when the voltage of an input signal is in a first preset range, the controller controls the first switching tube and the second switching tube to be turned on; when the voltage of the input signal is in a second preset range, the controller controls the first switching tube to be conducted and the second switching tube to be turned off, and through arranging the two switching tubes in parallel connection, different switching tubes are selected to be used according to the intensity of the electric signal, the intensity of the output signal is limited, the later-stage circuit is effectively protected, meanwhile, the energy conduction transmission loss in a normal working state can be reduced, the power MOS tube selection is facilitated, and the large-current output surge module is realized.
Description
Technical Field
The invention relates to the technical field of direct current surge suppressors, in particular to a parallel surge suppression circuit.
Background
A surge voltage suppressor (surge protector), also called a surge protector and a lightning protector, is an electronic device for providing safety protection for various electronic equipment, instruments and meters and communication lines. When a peak current or voltage is suddenly generated in an electric loop or a communication line due to external interference, the surge protector can conduct shunt in a very short time, so that damage of the surge to other equipment in the loop is avoided.
The internal MOS tube of the direct current surge suppressor is required to have higher single avalanche energy (EAS single avalanche energy), but the on-resistance (Rds) is large, and the loss is large under normal working voltage; it is difficult to manufacture a large current surge suppressor. Therefore, there is an urgent need to design a high-current surge suppression circuit with small loss.
Disclosure of Invention
The invention aims to provide a parallel surge suppression circuit so as to achieve the purpose of reducing the conduction loss of an MOS tube in a surge suppressor.
The invention is realized in the following way:
the surge suppression circuit comprises a controller, a first switching tube and a second switching tube, wherein the first switching tube and the second switching tube are connected in parallel, control ends of the first switching tube and the second switching tube are electrically connected with the controller so as to be conducted or cut off under the control of the controller, the conduction resistance of the second switching tube is smaller than that of the first switching tube, the single avalanche energy of the first switching tube is higher than that of the second switching tube, and when the voltage of an input signal is in a first preset range, the controller controls the first switching tube and the second switching tube to be conducted; when the voltage of the input signal is in a second preset range, the controller controls the first switching tube to be conducted and the second switching tube to be turned off.
Further, the parallel surge suppression circuit comprises a signal output end and an output signal sampling circuit, the output ends of the first switching tube and the second switching tube are electrically connected with the signal output end, the output signal sampling circuit is further electrically connected with the controller, the output signal sampling circuit is used for detecting the voltage of an output signal of the parallel surge suppression circuit, the detected voltage of the output signal is sent to the controller, and the controller controls the working state of the first switching tube according to the voltage of the output signal.
Further, the parallel surge suppression circuit comprises a signal input end and an input signal sampling circuit, wherein the signal input end is connected with the input end of the first switching tube and the input end of the second switching tube, the input signal sampling circuit is electrically connected with the signal input end, the input signal sampling circuit is further electrically connected with the controller, the input signal sampling circuit is used for detecting the voltage of an input signal of the parallel surge suppression circuit, the detected voltage of the input signal is sent to the controller, and the controller controls the on or off of the first switching tube and the second switching tube according to the voltage of the input signal.
Further, the grid electrode of the first switching tube is electrically connected with the controller, the drain electrode of the first switching tube is electrically connected with the signal input end, and the source electrode of the first switching tube is electrically connected with the signal output end.
Further, the grid electrode of the second switching tube is electrically connected with the controller, the drain electrode of the second switching tube is electrically connected with the signal input end, and the source electrode of the second switching tube is electrically connected with the signal output end.
Further, the first preset range is 8-36V.
Further, the second preset range is 36-80V.
Further, when the input signal is greater than a second preset range, the controller controls the first switching tube and the second switching tube to be turned off.
Further, the output signal sampling circuit comprises a first resistor and a second resistor, wherein a first end of the first resistor is electrically connected with the signal output end, a second end of the first resistor is electrically connected with the first I/O port of the controller, a first end of the second resistor is electrically connected with a second end of the first resistor, and a second end of the second resistor is grounded.
Further, the input signal sampling circuit comprises a third resistor and a fourth resistor, wherein a first end of the third resistor is electrically connected with the signal input end, a second end of the third resistor is electrically connected with the second I/O port of the controller, a first end of the fourth resistor is electrically connected with the second end of the third resistor, and a second end of the fourth resistor is grounded.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a parallel surge suppression circuit which comprises a controller, a first switching tube and a second switching tube, wherein the first switching tube and the second switching tube are connected in parallel, control ends of the first switching tube and the second switching tube are electrically connected with the controller so as to be turned on or off under the control of the controller, the on resistance of the second switching tube is smaller than that of the first switching tube, the single avalanche energy of the first switching tube is higher than that of the second switching tube, and when the voltage of an input signal is in a first preset range, the controller controls the first switching tube and the second switching tube to be turned on; when the voltage of the input signal is in a second preset range, the controller controls the first switching tube to be conducted and the second switching tube to be turned off, and two switching tubes connected in parallel are arranged, so that different switching tubes are selected to be used according to the intensity of the electric signal, the intensity of the output signal is limited, a later-stage circuit is effectively protected, meanwhile, the energy conduction transmission loss in a normal working state can be reduced, the power MOS tube model selection is facilitated, and the large-current output surge module is realized.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic block diagram of a parallel surge suppression circuit provided by the present invention.
Fig. 2 shows a schematic circuit connection diagram of a parallel surge suppression circuit.
Icon: 100-parallel surge suppression circuits; 110-a controller 111; MA-a first switching tube; MB-a second switching tube; p1-signal input terminal; p2-signal output terminal; 151-an input signal sampling circuit; r3-a third resistor; r4-fourth resistor; 153-output signal sampling circuit; r1-a first resistor; r2-second resistor.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, directions or positional relationships indicated by terms such as "upper", "lower", "left", "right", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or those that are conventionally put in use of the inventive product, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific direction, be configured and operated in a specific direction, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements.
In the description of the present invention, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "horizontal," "vertical," "overhang," and the like do not denote that the component is required to be absolutely horizontal or overhang, but may be slightly inclined. As "horizontal" merely means that its direction is more horizontal than "vertical", and does not mean that the structure must be perfectly horizontal, but may be slightly inclined. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Examples
Referring to fig. 1, fig. 1 shows a schematic diagram of a parallel surge suppression circuit 100 according to the present embodiment.
The parallel surge suppression circuit 100 includes a controller, a first switching tube MA and a second switching tube MB, where control ends of the first switching tube MA and the second switching tube MB are electrically connected to the controller, so as to be turned on or off under the control of the controller, so as to process signals and transmit the signals to a post-stage circuit.
The parallel surge suppression circuit 100 further includes an input signal sampling circuit 151 and an output signal sampling circuit 153, the input signal sampling circuit 151 being configured to sample an input signal and transmit the sampled input signal to the controller; the output signal sampling circuit 153 is configured to sample an output signal, and transmit the sampled output signal to the controller, where the controller controls the working states of the first switching tube MA and the second switching tube MB according to the sampled input signal and the sampled output signal.
For example, referring to fig. 2, in the present embodiment, the first switching tube MA and the second switching tube MB are connected in parallel, the parallel surge suppression circuit 100 further includes a signal input end P1 and a signal output end P2, the signal input end P1 is connected to the input end of the first switching tube MA and the input end of the second switching tube MB, the signal output end P2 is connected to the output ends of the first switching tube MA and the second switching tube MB, the signal input end P1 is used for accessing an input signal, so that the input signal is led into the first switching tube MA or the second switching tube MB, and the first switching tube MA or the second switching tube MB processes the input signal and then conducts the processed input signal to the signal output end P2 for outputting.
It should be noted that, in this embodiment, the parallel surge suppression circuit 100 further includes a protection circuit, where the protection circuit is electrically connected to the signal input end P1, and the protection circuit is configured to filter out a large current, so as to prevent the first switching tube MA and/or the second switching tube MB from being damaged by a signal with an excessive voltage or a signal with an excessive current.
In this embodiment, the first switching tube MA and the second switching tube MB may be MOS tubes, but not limited thereto. The grid electrode of the first switching tube MA is electrically connected with the controller, the drain electrode of the first switching tube MA is electrically connected with the signal input end P1, and the source electrode of the first switching tube MA is electrically connected with the signal output end P2. The grid electrode of the second switching tube MB is electrically connected with the controller, the drain electrode of the second switching tube MB is electrically connected with the signal input end P1, and the source electrode of the second switching tube MB is electrically connected with the signal output end P2. In this embodiment, the gate of the first switching tube MA and the gate of the second switching tube MB are electrically connected to the control end of the controller, and are used for being turned on or turned off under the control of the controller.
The input signal sampling circuit 151 is configured to sample an input signal and send the sampled input signal to the controller, and the output signal sampling circuit 153 is configured to sample an output signal and send the sampled output signal to the controller, where the controller controls the first switching tube MA or the second switching tube MB to be turned on or turned off according to the sampled input signal and the sampled output signal.
The input signal sampling circuit 151 is electrically connected to the signal input terminal P1, and the input signal sampling circuit 151 is further electrically connected to a controller, where the input signal sampling circuit 151 is configured to detect an input signal of the parallel surge suppression circuit 100, for example, detect a voltage of the input signal, send the detected voltage of the input signal to the controller, and the controller controls on or off of the first switching tube MA and the second switching tube MB according to the voltage of the input signal.
In this embodiment, the input signal sampling circuit 151 includes a third resistor R3 and a fourth resistor R4, wherein a first end of the third resistor R3 is electrically connected to the signal input terminal P1, a second end of the third resistor R3 is electrically connected to the second I/O port of the controller, a first end of the fourth resistor R4 is electrically connected to the second end of the third resistor R3, and a second end of the fourth resistor R4 is grounded.
The output ends of the first switching tube MA and the second switching tube MB are electrically connected with the signal output end P2, the output signal sampling circuit 153 is used for detecting the voltage of the output signal of the parallel surge suppression circuit 100, and sending the detected voltage of the output signal to the controller, and the controller controls the working state of the first switching tube MA according to the voltage of the output signal.
In this embodiment, the output signal sampling circuit 153 includes a first resistor R1 and a second resistor R2, wherein a first end of the first resistor R1 is electrically connected to the signal output end P2, a second end of the first resistor R1 is electrically connected to the first I/O port of the controller, a first end of the second resistor R2 is electrically connected to the second end of the first resistor R1, and a second end of the second resistor R2 is grounded.
It should be noted that, the input signal sampling circuit 151 and the output signal sampling circuit 153 each include a sub-circuit module such as a digital-to-analog conversion circuit, so as to convert the sampled analog signal into a digital signal and transmit the digital signal to the controller. In this embodiment, the controller may be a processing chip with the same or similar functions, such as a DSP control chip, a single chip, an FPGA chip, or the like.
In this embodiment, the first switching tube MA is a high EAS (single avalanche energy) and low Rdson (on-resistance) power device, and the second switching tube MB is a low EAS and low Rdson power device. The Rdson of the second switching tube MB is smaller than the Rdson of the first switching tube MA, and the EAS of the first switching tube MA is higher than the EAS of the second switching tube MB, and when the voltage of the input signal is in a first preset range, for example, the first preset range may be 8-36V. The controller controls the first switching tube MA and the second switching tube MB to be conducted; at this time, since the on-resistance of the second switching tube MB is small, the current flows through the second switching tube MB, and the energy loss at the time of normal conduction is small.
When the voltage of the input signal is in an overvoltage state, that is, the voltage of the input signal is in a second preset range, the controller controls the first switching tube MA to be turned on and the second switching tube MB to be turned off. In this embodiment, the second preset range may be 36 to 80V. The first switching tube MA is turned on, and the second switching tube MB is turned off, so that the electric signal is transmitted to the post-stage circuit through the signal output terminal P2 by the first switching tube MA. The first switching tube MA is a power device with high EAS (single avalanche energy) and low Rdson (on-resistance), and the electric signal can limit the energy of the signal when passing through. The controller controls the working state of the first switching tube MA according to the sampled output signal, for example, the controller controls the driving voltage of the first switching tube MA according to the sampled output signal, so that the first switching tube MA works in a linear state, the output signal is limited to a set value, and electric equipment of a later-stage circuit is effectively protected.
When the voltage of the sampled input signal received by the controller is normal, namely in a first preset range, the controller controls the second switching tube MB to be opened, and the electric signal is recovered to be transmitted through the second switching tube MB.
When the input signal is larger than a second preset range, the controller controls the first switching tube MA and the second switching tube MB to be turned off so as to prevent the protection of the later-stage circuit.
In summary, the present invention provides a parallel surge suppression circuit 100, which includes a controller, a first switching tube MA and a second switching tube MB, where the first switching tube MA and the second switching tube MB are connected in parallel, control ends of the first switching tube MA and the second switching tube MB are electrically connected to the controller, so as to be turned on or off under the control of the controller, an on-resistance of the second switching tube MB is smaller than an impedance of the first switching tube MA, a single avalanche energy of the first switching tube MA is higher than a single avalanche energy of the second switching tube MB, and when a voltage of an input signal is in a first preset range, the controller controls the first switching tube MA and the second switching tube MB to be turned on; when the voltage of the input signal is in a second preset range, the controller controls the first switching tube MA to be conducted and the second switching tube MB to be turned off, and two switching tubes connected in parallel are arranged, so that different switching tubes are selected to be used according to the intensity of the electric signal, the intensity of the output signal is limited, a later-stage circuit is effectively protected, meanwhile, the energy conduction transmission loss in a normal working state can be reduced, the power MOS tube selection is facilitated, and the large-current output surge module is realized.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The parallel surge suppression circuit is characterized by comprising a controller, a first switching tube and a second switching tube, wherein the first switching tube and the second switching tube are connected in parallel, the control ends of the first switching tube and the second switching tube are electrically connected with the controller so as to be turned on or turned off under the control of the controller, the on resistance of the second switching tube is smaller than the resistance of the first switching tube, and the single avalanche energy of the first switching tube is higher than the single avalanche energy of the second switching tube;
when the voltage of the input signal is in a first preset range, the controller controls the first switching tube and the second switching tube to be conducted;
when the voltage of the input signal is in a second preset range, the controller controls the first switching tube to be conducted and the second switching tube to be turned off, and controls the driving voltage of the first switching tube according to the sampled output signal, so that the first switching tube works in a linear state, the output signal is limited to a set value, and electric equipment of a later-stage circuit is effectively protected; the minimum value of the second preset range is the maximum value of the first preset range.
2. The parallel surge suppression circuit according to claim 1, wherein the parallel surge suppression circuit includes a signal output terminal and an output signal sampling circuit, the output terminals of the first switching tube and the second switching tube are electrically connected with the signal output terminal, the output signal sampling circuit is further electrically connected with the controller, the output signal sampling circuit is used for detecting a voltage of an output signal of the parallel surge suppression circuit, the detected voltage of the output signal is sent to the controller, and the controller controls an operating state of the first switching tube according to the voltage of the output signal.
3. The parallel surge suppression circuit according to claim 2, wherein the parallel surge suppression circuit includes a signal input terminal connected to both the input terminal of the first switching tube and the input terminal of the second switching tube, and an input signal sampling circuit electrically connected to the signal input terminal, the input signal sampling circuit further electrically connected to the controller, the input signal sampling circuit being configured to detect a voltage of an input signal of the parallel surge suppression circuit, and to send the detected voltage of the input signal to the controller, the controller controlling on or off of the first switching tube and the second switching tube according to the voltage of the input signal.
4. The parallel surge suppression circuit of claim 3, wherein a gate of the first switching tube is electrically connected to the controller, a drain of the first switching tube is electrically connected to the signal input, and a source of the first switching tube is electrically connected to the signal output.
5. The parallel surge suppression circuit of claim 4, wherein a gate of the second switching tube is electrically connected to the controller, a drain of the second switching tube is electrically connected to the signal input, and a source of the second switching tube is electrically connected to the signal output.
6. The parallel surge suppression circuit according to claim 1, wherein the first preset range is 8-36V.
7. The parallel surge suppression circuit according to claim 1, wherein the second preset range is 36-80V.
8. The parallel surge suppression circuit of claim 1, wherein the controller controls both the first switching tube and the second switching tube to turn off when the input signal is greater than a second preset range.
9. The parallel surge suppression circuit of claim 2, wherein the output signal sampling circuit comprises a first resistor and a second resistor, a first end of the first resistor being electrically connected to the signal output, a second end of the first resistor being electrically connected to a first I/O port of the controller, a first end of the second resistor being electrically connected to a second end of the first resistor, a second end of the second resistor being grounded.
10. The parallel surge suppression circuit of claim 4, wherein the input signal sampling circuit includes a third resistor and a fourth resistor, a first end of the third resistor being electrically connected to the signal input, a second end of the third resistor being electrically connected to the second I/O port of the controller, a first end of the fourth resistor being electrically connected to the second end of the third resistor, a second end of the fourth resistor being grounded.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810323928.1A CN108336722B (en) | 2018-04-11 | 2018-04-11 | Parallel surge suppression circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810323928.1A CN108336722B (en) | 2018-04-11 | 2018-04-11 | Parallel surge suppression circuit |
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| CN108336722A CN108336722A (en) | 2018-07-27 |
| CN108336722B true CN108336722B (en) | 2024-01-16 |
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| CN201810323928.1A Active CN108336722B (en) | 2018-04-11 | 2018-04-11 | Parallel surge suppression circuit |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11474581B2 (en) * | 2019-08-09 | 2022-10-18 | Analog Devices International Unlimited Company | Communication terminal for hot-swap controllers |
| CN116231610B (en) * | 2023-05-09 | 2023-08-01 | 四川泰瑞创通讯技术股份有限公司 | Front-end surge suppression device, control method, electronic device and readable storage medium |
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| CN206490429U (en) * | 2017-02-23 | 2017-09-12 | 无锡天和电子有限公司 | A kind of high current overvoltage surge suppression circuit |
| CN208209518U (en) * | 2018-04-11 | 2018-12-07 | 四川升华电源科技有限公司 | Surge restraint circuit in parallel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102010030064B4 (en) * | 2010-06-15 | 2022-04-28 | Infineon Technologies Ag | protection circuit |
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| JP2000013991A (en) * | 1998-06-22 | 2000-01-14 | Nec Corp | Method and circuit for limiting overcurrent using mosfet switch |
| CN1528040A (en) * | 2001-04-06 | 2004-09-08 | ����µ��ɷ�����˾ | Electric power supply with a safety cut-off |
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