CN108322275B - Link time delay measuring method and device based on unit impulse response - Google Patents
Link time delay measuring method and device based on unit impulse response Download PDFInfo
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Abstract
The invention discloses a link time delay measuring method based on unit impulse response, which comprises the following steps: acquiring an output signal containing all-zero data; detecting the zero value length of the output signal, generating a unit pulse digital response signal when verifying that the zero value length reaches a preset threshold value, and starting a time delay measurement counter; and detecting the unit pulse digital response signal, closing the delay measurement counter when the maximum peak value of the unit pulse digital response signal is detected, and dividing the count value of the delay measurement counter by the working frequency of the delay measurement counter to obtain a calculation result which is used as the delay value of an uplink or downlink digital link. The invention also discloses a link time delay measuring device based on the unit impulse response.
Description
Technical Field
The invention relates to a time delay measurement technology in the field of communication, in particular to a link time delay measurement method and device based on unit impulse response.
Background
In a wireless communication system, in order to avoid mutual interference between an uplink and a downlink in the same radio frequency unit, or to avoid interference generated between radio frequency units when a plurality of radio frequency units are connected to a baseband unit, it is generally necessary to measure a delay value of each uplink and downlink between the radio frequency unit and the baseband unit, and report the measured delay value to the baseband unit, so that the baseband unit performs delay compensation processing uniformly, thereby ensuring synchronization between received data and transmitted data of the system.
Generally, the delay values of the uplink and downlink between the rf unit and the baseband unit mainly include three parts, which are: optical fiber delay, analog link delay, and digital link delay. The optical fiber delay is related to the length of the optical fiber, so that for a link with a fixed optical fiber length, the optical fiber delay is fixed delay; the Analog link delay is related to Analog devices such as an Analog-to-Digital Converter (ADC) or a Digital-to-Analog Converter (DAC), and therefore, for a given board, the Analog link delay is also a fixed delay; digital link delay is related to communication systems, such as Global System for Mobile communications (GSM), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access (CDMA), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Time Division-Synchronous Code Division Multiple Access (LTE), Long Term Evolution (Long Term Evolution), and the like, and for different communication systems, processing units used on the link are different, such as the order of a filter, so that the delay of signal propagation on the link is different, and thus, the digital link delay is a variable delay.
Fig. 1 shows a conventional downlink schematic diagram, and as shown in fig. 1, the downlink delay refers to the total delay generated when a measurement signal is transmitted from an optical port of a baseband unit to an rf port of an rf unit. In the radio frequency unit, the time delay from the optical port to the DAC interface is the time delay of a downlink digital link; and the time delay from the DAC interface to the radio frequency interface is the time delay of a downlink analog link. Fig. 2 shows a schematic diagram of an existing uplink, and as shown in fig. 2, the uplink delay refers to the total delay generated when a measurement signal is transmitted from the rf port of the rf unit to the optical port of the baseband unit. In the radio frequency unit, the time delay from the radio frequency port to the ADC interface is the time delay of an uplink analog link; the delay from the ADC interface to the optical port is the uplink digital link delay.
At present, for time delay measurement of an uplink and a downlink of a radio frequency unit, external instruments such as a baseband unit, a signal source, a spectrometer and other instruments need to be used, in addition, in the uplink direction, data is sent by the signal source, and the baseband unit demodulates the data; in the downlink direction, the baseband unit transmits data and the spectrum analyzer demodulates the data. Although the total delay values of the analog link and the digital link inside the radio frequency unit can be directly measured by using the method, the existing radio frequency unit supports a multi-mode system scene, so that the delay of the digital link needs to be measured independently in different communication system scenes, and thus, the delay measurement work of the multi-mode scene is very easy to cause complexity.
Disclosure of Invention
In view of this, embodiments of the present invention are expected to provide a link delay measurement method and apparatus based on unit impulse response, which not only can simplify the measurement steps, but also can reduce the dependency on the test environment, and improve the test efficiency.
In order to achieve the above purpose, the technical solution of the embodiment of the present invention is realized as follows:
the embodiment of the invention provides a link time delay measuring method based on unit impulse response, which comprises the following steps:
acquiring an output signal containing all-zero data;
detecting the zero value length of the output signal, generating a unit pulse digital response signal when verifying that the zero value length reaches a preset threshold value, and starting a time delay measurement counter;
and detecting the unit pulse digital response signal, closing the delay measurement counter when the maximum peak value of the unit pulse digital response signal is detected, and dividing the count value of the delay measurement counter by the working frequency of the delay measurement counter to obtain a calculation result which is used as the delay value of an uplink or downlink digital link.
In the above solution, before the obtaining the output signal containing all-zero data, the method further includes:
switching an input of the uplink or downlink digital link to the test data path and an output of the uplink or downlink digital link to the peak detect path.
In the above scheme, the generating a unit pulse digital response signal includes: obtaining a unit pulse digital signal according to a received output request signal for starting the unit pulse digital signal; and obtaining a unit pulse digital response signal according to the excitation of the unit pulse digital signal to the digital link.
In the above scheme, the delay measurement counter counts by using the operating clock of the uplink or downlink digital link as a counting unit.
The embodiment of the invention provides a link time delay measuring device based on unit impulse response, which comprises: the device comprises a signal generation module, a signal detection module and a time delay measurement module; wherein,
the signal generation module is used for acquiring an output signal containing all-zero data, detecting the zero value length of the output signal, generating a unit pulse digital response signal when verifying that the zero value length reaches a preset threshold value, and starting a time delay measurement counter;
the signal detection module is configured to detect the unit pulse digital response signal, and close the delay measurement counter when a maximum peak value of the unit pulse digital response signal is detected;
and the time delay measuring module is used for dividing the counting value of the time delay measuring counter by the working frequency of the time delay measuring counter to obtain a calculation result which is used as the time delay value of the uplink or downlink digital link.
In the above scheme, the apparatus further comprises: and the route switching module is used for switching the input end of the uplink or downlink digital link to the test data path and switching the output end of the uplink or downlink digital link to the peak value detection path before the signal generation module acquires the output signal containing all-zero data.
In the foregoing solution, the signal generating module is specifically configured to: obtaining a unit pulse digital signal according to a received output request signal for starting the unit pulse digital signal; and obtaining a unit pulse digital response signal according to the excitation of the unit pulse digital signal to the digital link.
The embodiment of the invention provides a link time delay measuring method based on unit impulse response, which comprises the following steps:
acquiring a fixed time delay value of an uplink or a downlink of at least one braking type scene;
according to any one of the above-mentioned link delay measurement methods based on unit impulse response, obtaining a delay value of an uplink or downlink digital link of at least one manufacturing scenario;
and adding the fixed time delay value of the uplink or downlink and the time delay value of the uplink or downlink digital link to obtain the total time delay value of the uplink or downlink.
In the foregoing solution, the fixed delay value includes: a fiber delay value and an analog link delay value.
The embodiment of the invention also provides a unit impulse response-based link time delay measuring device, which comprises: the device comprises a first acquisition module, a second acquisition module and a calculation module; wherein,
the first obtaining module is configured to obtain a fixed time delay value of an uplink or a downlink of at least one braking scenario;
the second obtaining module is configured to obtain a delay value of an uplink or downlink digital link of at least one braking type scene; the second obtaining module is any one of the above link delay measuring devices based on unit impulse response;
and the calculation module is used for adding the fixed time delay value of the uplink or downlink and the time delay value of the uplink or downlink digital link to obtain the total time delay value of the uplink or downlink.
In the foregoing scheme, the first obtaining module is specifically configured to obtain an optical fiber delay value and an analog link delay value of an uplink or a downlink in at least one system type scenario.
The link time delay measuring method and device based on unit impulse response provided by the embodiment of the invention obtain an output signal containing all-zero data; detecting the zero value length of the output signal, generating a unit pulse digital response signal when verifying that the zero value length reaches a preset threshold value, and starting a time delay measurement counter; and detecting the unit pulse digital response signal, closing the delay measurement counter when the maximum peak value of the unit pulse digital response signal is detected, and dividing the count value of the delay measurement counter by the working frequency of the delay measurement counter to obtain a calculation result which is used as the delay value of an uplink or downlink digital link. Therefore, the online measurement of the time delay of the uplink or downlink digital link is realized by utilizing the characteristic that the unit pulse digital response signal has the maximum peak value in the time domain under the condition of not changing the working environment and the link processing function; meanwhile, the embodiment of the invention obtains the variable delay value through the digital circuit inside the link, and then obtains the total delay value of the link by adding the fixed delay value.
Drawings
Fig. 1 is a schematic diagram of a conventional downlink;
fig. 2 is a diagram of a conventional uplink;
fig. 3 is a schematic flowchart of a link delay measurement method based on unit impulse response according to an embodiment of the present invention;
FIG. 4 is a time domain diagram of an input unit pulse signal and an output response signal according to an embodiment of the present invention;
fig. 5 is a schematic flowchart of a specific implementation of the method for measuring a delay of a downlink digital link based on a unit impulse response according to the second embodiment of the present invention;
fig. 6 is a schematic flowchart of a specific implementation of the method for measuring uplink digital link delay based on unit impulse response according to a third embodiment of the present invention;
fig. 7 is a schematic flowchart of another link delay measurement method based on unit impulse response according to a fourth embodiment of the present invention;
fig. 8 is a schematic diagram of a circuit for measuring a downlink digital link delay of a radio frequency unit according to a fifth embodiment of the present invention;
fig. 9 is a schematic diagram of an rf unit uplink digital link delay measurement circuit according to a sixth embodiment of the present invention;
fig. 10 is a schematic structural diagram of a link delay measurement apparatus based on unit impulse response according to a seventh embodiment of the present invention;
fig. 11 is a schematic structural diagram of another link delay measurement apparatus based on unit impulse response according to an eighth embodiment of the present invention.
Detailed Description
So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the invention, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings.
Example one
As shown in fig. 3, an implementation process of the link delay measurement method based on unit impulse response in the embodiment of the present invention includes the following steps:
step 301: acquiring an output signal containing all-zero data;
here, the output signal including all-zero data is transmitted when the output request signal for starting the unit pulse digital signal is not detected.
It should be particularly noted that, before the step of measuring the link delay is performed, the embodiment of the present invention sends a long segment of zero data, so as to flush out response data of the filters in the link at time points T0-1 and T0-2 … … T0-N before time point T0, so as to ensure that output responses of filters in each stage in the current link are zero.
Here, before the obtaining the output signal containing all-zero data, the method further includes:
switching an input of the uplink or downlink digital link to the test data path and an output of the uplink or downlink digital link to the peak detect path.
Specifically, for an uplink digital link, an input path of the link is switched to a test data path from an ADC path, and an output path of the link is switched to a peak detection path from an optical port data path; for a downlink digital link, an input channel of the link is switched to a test data channel from an optical port data channel, and an output channel of the link is switched to a peak detection channel from a DAC channel. Here, it is necessary to ensure that the input path and the output path are switched at the same time.
Step 302: detecting the zero value length of the output signal, generating a unit pulse digital response signal when verifying that the zero value length reaches a preset threshold value, and starting a time delay measurement counter;
here, the generating of the unit impulse digital response signal in this step includes:
obtaining a unit pulse digital signal according to a received output request signal for starting the unit pulse digital signal; and obtaining a unit pulse digital response signal according to the excitation of the unit pulse digital signal to the digital link.
Fig. 4 shows a time domain diagram of an input unit pulse signal and an output response signal according to an embodiment of the present invention, as shown in fig. 4, the left diagram is the input unit pulse signal, the unit pulse signal is a unit pulse digital signal, in the time domain, the amplitude of the unit pulse digital signal is the maximum positive value represented by the link processing bit width, the unit pulse digital signal is used to excite the intermediate frequency digital link, and the unit pulse digital response signal shown in the right diagram is obtained, as shown in fig. 4, the unit pulse digital response signal has a characteristic of a maximum peak value in the time domain, and a maximum peak value point can be transmitted synchronously with the link processing delay and the group delay.
Here, the delay measurement counter counts in units of count of the operation clock of the up or down digital link.
Here, the zero length of the output signal can be detected by using a conventional detection method, and details thereof are not repeated.
Here, the predetermined threshold is determined depending on the total order of the filters in the link and how much response data the filters have at times T0-1, T0-2 … … T0-N before time T0, that is, the predetermined threshold may be specifically determined according to practical applications.
Step 303: and detecting the unit pulse digital response signal, closing the delay measurement counter when the maximum peak value of the unit pulse digital response signal is detected, and dividing the count value of the delay measurement counter by the working frequency of the delay measurement counter to obtain a calculation result which is used as the delay value of an uplink or downlink digital link.
Specifically, when the maximum peak value of the unit pulse digital response signal is detected, a timing closing signal is sent to the delay measurement counter, timing is stopped after the delay measurement counter receives the timing closing signal, a measurement completion marking signal is sent, a value obtained by counting of the delay measurement counter is latched, the value obtained by counting of the delay measurement counter is divided by the working frequency of the delay measurement counter, and an obtained calculation result is used as a delay value of an uplink or downlink digital link.
Here, the maximum peak value of the unit pulse digital response signal may be detected by a maximum threshold decision method, and how to detect the maximum peak value belongs to the prior art, and details are not described here.
The link delay measurement method based on unit impulse response provided by the embodiment of the invention can be Integrated in a digital intermediate frequency process such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA), can autonomously complete the delay measurement of an uplink or downlink digital link without changing the working environment and the link processing function, and is an online measurement method; and the measurement error of the measurement method only has the error of one output sampling point at most, and the requirement of link time delay can be met.
The following describes in detail a specific implementation process of the link delay measurement method based on unit impulse response according to the embodiment of the present invention.
Example two
Fig. 5 is a schematic diagram of a specific implementation flow of the method for measuring a downlink digital link delay based on a unit impulse response according to the embodiment of the present invention, and as shown in fig. 5, the method includes the following steps:
step 501: switching an input channel of a downlink digital link from an optical port data channel to a test data channel;
step 502: switching an output channel of a downlink digital link from a DAC channel to a peak detection channel;
here, it is necessary to ensure that the routes in step 501 and step 502 are switched simultaneously.
Step 503: acquiring an output signal containing all-zero data;
here, the output signal including all-zero data is transmitted when the output request signal for starting up the unit pulse data is not detected.
It should be noted that, a long segment of zero data is sent first, so as to flush out response data of the filters in the link at time points T0-1 and T0-2 … … T0-N before time point T0, so as to ensure that output responses of the filters in each stage in the current link are zero.
Step 504: detecting the length of all zero values of the output signal;
here, the length of all zeros of the output signal can be detected by using the existing detection method, and will not be described in detail herein.
Step 505: when the length of the all-zero value is equal to the N value, unit pulse data is sent, and a time delay measurement counter is started at the same time;
here, the unit pulse data is a unit pulse digital signal, and the intermediate frequency digital link is excited based on the unit pulse digital signal to obtain a unit pulse digital response signal for subsequent peak detection processing.
Here, the N value is determined according to the total order of the filters in the link and how much response data the filters have at times T0-1, T0-2 … … T0-N before time T0.
Here, the delay measurement counter counts in units of count of the operation clock of the downstream digital link.
Step 506: carrying out peak value detection on the unit pulse data, and stopping counting of the time delay measurement counter when the maximum peak value is detected;
here, the maximum peak value of the unit impulse digital response signal can be detected by using the existing maximum threshold decision method, which belongs to the prior art and is not described in detail herein.
Step 507: latching the value obtained by counting of the delay measurement counter, dividing the value by the working frequency of the delay measurement counter, and taking the obtained calculation result as the delay value of the downlink digital link;
step 508: and returning the time delay value of the downlink digital link to the controller.
EXAMPLE III
Fig. 6 is a schematic diagram of a specific implementation flow of the uplink digital link delay measurement method based on a unit impulse response according to the embodiment of the present invention, and as shown in fig. 6, the method includes the following steps:
step 601: switching an input path of an uplink digital link from an ADC path to a test data path;
step 602: switching an output path of the uplink digital link from an optical port data path to a peak detection path;
here, it is necessary to ensure that the routes in step 601 and step 602 are switched simultaneously.
Step 603: acquiring an output signal containing all-zero data;
here, the output signal including all-zero data is transmitted when the output request signal for starting up the unit pulse data is not detected.
It should be noted that, a long segment of zero data is sent first, so as to flush out response data of the filters in the link at time points T0-1 and T0-2 … … T0-N before time point T0, so as to ensure that output responses of the filters in each stage in the current link are zero.
Step 604: detecting the length of all zero values of the output signal;
here, the length of all zeros of the output signal can be detected by using the existing detection method, and will not be described in detail herein.
Step 605: when the length of the all-zero value is equal to the N value, unit pulse data is sent, and a time delay measurement counter is started at the same time;
here, the unit pulse data is a unit pulse digital signal, and the intermediate frequency digital link is excited based on the unit pulse digital signal to obtain a unit pulse digital response signal for subsequent peak detection processing.
Here, the N value is determined according to the total order of the filters in the link and how much response data the filters have at times T0-1, T0-2 … … T0-N before time T0.
Here, the delay measurement counter counts in units of count of an operation clock of the uplink digital link.
Step 606: carrying out peak value detection on the unit pulse data, and stopping counting of the time delay measurement counter when the maximum peak value is detected;
here, the maximum peak value of the unit impulse digital response signal can be detected by using the existing maximum threshold decision method, which belongs to the prior art and is not described in detail herein.
Step 607: latching the value obtained by counting of the delay measurement counter, dividing the value by the working frequency of the delay measurement counter, and taking the obtained calculation result as the delay value of the uplink digital link;
step 608: and returning the time delay value of the uplink digital link to the controller.
Example four
Fig. 7 is a schematic flowchart of another link delay measurement method based on unit impulse response according to an embodiment of the present invention, and as shown in fig. 7, the method includes the following steps:
step 701: acquiring a fixed time delay value of an uplink or a downlink of at least one braking type scene;
here, the fixed delay value includes: a fiber delay value and an analog link delay value. Wherein the optical fiber delay value is related to the length of the optical fiber, and therefore, for a link with a fixed optical fiber length, the optical fiber delay is a fixed delay; the analog link delay value is related to the analog device, and therefore, for a given board, the analog link delay is also a fixed delay.
Here, the analog device includes an ADC or a DAC.
Here, the system scenario may be any one of communication systems such as GSM, UMTS, CDMA, TD-SCDMA, and LTE.
Step 702: according to any one of the above-mentioned link delay measurement methods based on unit impulse response, obtaining a delay value of an uplink or downlink digital link of at least one manufacturing scenario;
here, the delay value of the uplink or downlink digital link is a variable delay, and is related to a communication system.
Step 703: and adding the fixed time delay value of the uplink or downlink and the time delay value of the uplink or downlink digital link to obtain the total time delay value of the uplink or downlink.
Compared with the existing link time delay measuring method, the embodiment of the invention does not need to build measuring environments of various system scenes, can reduce actual measuring times, and only needs to measure once under a certain system measuring environment to obtain the total fixed time delay value so as to obtain the link total time delay values of all the system scenes, thereby greatly simplifying measuring steps and methods and improving measuring efficiency.
EXAMPLE five
Fig. 8 is a schematic diagram of a circuit for measuring a downlink digital link delay of a radio frequency unit according to an embodiment of the present invention, where, as shown in fig. 8, the circuit includes two route switching units, a unit pulse signal generating unit, a peak detecting unit, a delay measuring unit, and a control unit; wherein, two route switching units are respectively: an input route switching unit and an output route switching unit.
The functions of the above-mentioned several units are explained in further detail below.
The input route switching unit can control the switching selection of the input data channel of the link, so that the working link does not need to switch data in a power-down mode, and an internal test signal source is switched through the route, thereby realizing online measurement.
The output route switching unit can control the switching selection of the link output data channel, and further cooperates with the input route switching unit to switch the link output data route to the detection channel, and meanwhile, the abnormal data flow to the baseband unit or the radio frequency analog circuit is also avoided. It should be noted that the input route switching unit and the output route switching unit are to implement simultaneous switching.
The unit pulse signal generating unit can output all-zero data or unit pulse digital signal data, control the on or off of signal data output, and start timing measurement by matching with the peak detection unit and the time delay measuring unit.
The peak value detection unit can detect the peak value and the zero value length of the signal, and when the zero value length is judged to meet the preset threshold value, the unit pulse signal generation unit is controlled to output the unit pulse digital signal and the time delay measurement unit is matched to stop timing measurement.
And the time delay measuring unit is used for timing based on a working clock of the digital link, receiving control commands of the unit pulse signal generating unit and the peak value detecting unit, has the functions of reporting a measurement completion mark and reporting a measured value, and can process clock domain crossing timing.
And the control unit has the functions of controlling a time delay measuring mechanism, receiving a time delay measuring result, automatically compensating a link time delay value and the like.
The overall process of the downlink digital link delay measurement of the lower rf unit is described in detail with reference to fig. 8, which is roughly as follows: starting a time delay measurement trigger signal by a control unit; the input route switching unit controls the downlink digital input path to be switched to the test data path from the optical port path, and the output route switching unit controls the downlink digital output path to be switched to the peak detection path from the DAC path; at this time, the unit pulse signal generating unit outputs an all-zero signal data; the peak value detection unit carries out all-zero value detection on all-zero signal data, counts the length of all-zero values, and sends a request signal for starting unit pulse digital signal output to the unit pulse signal generation unit when detecting that the length of all-zero values is equal to the N value, wherein the N value can be configured by the control unit; after receiving the request signal, the unit pulse signal generating unit outputs unit pulse signal data and sends a signal for starting timing to the time delay measuring unit; after receiving the signal for starting timing, the time delay measuring unit starts timing and counts by taking a working clock of a downlink as a counting unit; when the peak value detection unit detects the peak value of the unit pulse digital response signal by adopting a maximum threshold judgment method, a signal for stopping timing is sent to the time delay measurement unit, so that the time delay measurement unit stops timing, a measurement completion signal is sent to the control unit, and a time delay value is latched; after receiving the measurement completion signal, the control unit reads the latched time delay value, and reports the calculation result obtained by dividing the value by the working frequency of the time delay measurement counter to the user in a register mode, so that the measurement of the time delay of the downlink digital link of the radio frequency unit can be completed.
EXAMPLE six
Fig. 9 is a schematic diagram of a circuit for measuring uplink digital link delay of a radio frequency unit according to an embodiment of the present invention, and as shown in fig. 9, the circuit includes two route switching units, a unit pulse signal generating unit, a peak detecting unit, a delay measuring unit, and a control unit; wherein, two route switching units are respectively: an input route switching unit and an output route switching unit. Since the functions of the above units in the uplink digital link delay measurement circuit of the radio frequency unit are similar to the functions of the corresponding units in the downlink digital link delay measurement circuit, they will not be described in detail here.
The overall process of the uplink digital link delay measurement of the lower rf unit is described in detail with reference to fig. 9, which is roughly as follows: starting a time delay measurement trigger signal by a control unit; the input route switching unit controls the uplink digital input channel to be switched to the test data channel from the ADC channel, and the output route switching unit controls the uplink digital output channel to be switched to the peak detection channel from the optical port channel; at this time, the unit pulse signal generating unit outputs an all-zero signal data; the peak value detection unit carries out all-zero value detection on all-zero signal data, counts the length of all-zero values, and sends a request signal for starting unit pulse digital signal output to the unit pulse signal generation unit when detecting that the length of all-zero values is equal to the N value, wherein the N value can be configured by the control unit; after receiving the request signal, the unit pulse signal generating unit outputs unit pulse signal data and sends a signal for starting timing to the time delay measuring unit; after receiving the signal for starting timing, the time delay measuring unit starts timing and counts by taking the working clock of the uplink as a counting unit; when the peak value detection unit detects the peak value of the unit pulse digital response signal by adopting a maximum threshold judgment method, a signal for stopping timing is sent to the time delay measurement unit, so that the time delay measurement unit stops timing, a measurement completion signal is sent to the control unit, and a time delay value is latched; after receiving the measurement completion signal, the control unit reads the latched time delay value, and reports the calculation result obtained by dividing the value by the working frequency of the time delay measurement counter to the user in a register mode, so that the measurement of the uplink digital link time delay of the radio frequency unit can be completed.
EXAMPLE seven
In order to implement the foregoing method, an embodiment of the present invention further provides a link delay measurement apparatus based on unit impulse response, as shown in fig. 10, the apparatus includes a signal generation module 1001, a signal detection module 1002, and a delay measurement module 1003; wherein,
the signal generating module 1001 is configured to acquire an output signal including all-zero data, detect a zero-value length of the output signal, generate a unit pulse digital response signal when verifying that the zero-value length reaches a preset threshold, and start a delay measurement counter;
the signal detection module 1002 is configured to detect the unit pulse digital response signal, and close the delay measurement counter when a maximum peak value of the unit pulse digital response signal is detected;
the delay measurement module 1003 is configured to divide the count value of the delay measurement counter by the working frequency of the delay measurement counter to obtain a calculation result, which is used as the delay value of the uplink or downlink digital link.
The signal generating module 1001 is specifically configured to: obtaining a unit pulse digital signal according to a received output request signal for starting the unit pulse digital signal; and obtaining a unit pulse digital response signal according to the excitation of the unit pulse digital signal to the digital link.
Here, the apparatus further includes: a route switching module 1004, configured to switch an input end of the uplink or downlink digital link to the test data path and switch an output end of the uplink or downlink digital link to the peak detection path before the signal generating module 1001 obtains the output signal containing all-zero data.
Here, the delay measurement counter counts in units of count of the operation clock of the up or down digital link.
Example eight
In order to implement the foregoing method, another link delay measurement apparatus based on unit impulse response is further provided in the embodiments of the present invention, as shown in fig. 11, the apparatus includes a first obtaining module 1101, a second obtaining module 1102, and a calculating module 1103; wherein,
the first obtaining module 1101 is configured to obtain a fixed time delay value of an uplink or a downlink of at least one braking scenario;
the second obtaining module 1102 is configured to obtain a delay value of an uplink or a downlink digital link of at least one manufacturing scenario; the second obtaining module is any one of the above link delay measuring devices based on unit impulse response;
the calculating module 1103 is configured to add the fixed delay value of the uplink or downlink and the delay value of the uplink or downlink digital link to obtain a total delay value of the uplink or downlink.
Here, the first obtaining module 1101 is specifically configured to obtain an optical fiber delay value and an analog link delay value of an uplink or a downlink of at least one manufacturing scenario.
Here, the system scenario may be any one of communication systems such as GSM, UMTS, CDMA, TD-SCDMA, and LTE.
In practical applications, the Signal generating module 1001, the Signal detecting module 1002, the delay measuring module 1003, the route switching module 1004, the first obtaining module 1101, the second obtaining module 1102 and the calculating module 1103 can be implemented by a Central Processing Unit (CPU), a microprocessor Unit (MPU), a Digital Signal Processor (DSP), an FPGA or the like on the Digital intermediate frequency Processing device.
The embodiment of the invention acquires an output signal containing all-zero data; detecting the zero value length of the output signal, generating a unit pulse digital response signal when verifying that the zero value length reaches a preset threshold value, and starting a time delay measurement counter; and detecting the unit pulse digital response signal, closing the delay measurement counter when the maximum peak value of the unit pulse digital response signal is detected, and dividing the count value of the delay measurement counter by the working frequency of the delay measurement counter to obtain a calculation result which is used as the delay value of an uplink or downlink digital link. Therefore, the online measurement of the time delay of the uplink or downlink digital link is realized by utilizing the characteristic that the unit pulse digital response signal has the maximum peak value in the time domain under the condition of not changing the working environment and the link processing function; meanwhile, the embodiment of the invention obtains the variable delay value through the digital circuit inside the link, and then obtains the total delay value of the link by adding the fixed delay value.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (12)
1. A method for measuring link delay based on unit impulse response is characterized in that the method comprises the following steps:
acquiring an output signal containing all-zero data;
detecting the zero value length of the output signal, generating a unit pulse digital response signal when verifying that the zero value length reaches a preset threshold value, and starting a time delay measurement counter, wherein the preset threshold value is an N value, and the N value is a value determined according to the total order of filters in a link and the data volume of response data of the filters at T0-1 and T0-2 … … T0-N moments before a specified T0 moment;
and detecting the unit pulse digital response signal, closing the delay measurement counter when the maximum peak value of the unit pulse digital response signal is detected, and dividing the count value of the delay measurement counter by the working frequency of the delay measurement counter to obtain a calculation result which is used as the delay value of an uplink or downlink digital link.
2. The method of claim 1, wherein prior to said obtaining an output signal containing all-zero data, the method further comprises:
switching an input of the uplink or downlink digital link to the test data path and an output of the uplink or downlink digital link to the peak detect path.
3. The method of claim 1 or 2, wherein generating a unit pulse digital response signal comprises:
obtaining a unit pulse digital signal according to a received output request signal for starting the unit pulse digital signal; and obtaining a unit pulse digital response signal according to the excitation of the unit pulse digital signal to the digital link.
4. A method according to claim 1 or 2, wherein the delay measurement counter counts in units of counts of the operating clock of the upstream or downstream digital link.
5. A link delay measurement device based on unit impulse response, the device comprising: the device comprises a signal generation module, a signal detection module and a time delay measurement module; wherein,
the signal generation module is used for acquiring an output signal containing all-zero data, detecting the zero value length of the output signal, generating a unit pulse digital response signal when verifying that the zero value length reaches a preset threshold value, and starting a time delay measurement counter; wherein,
the preset threshold is a value N which is a value determined according to the total order of the filters in the link and the data amount of response data of the filters at the time T0-1 and T0-2 … … T0-N before the specified time T0;
the signal detection module is configured to detect the unit pulse digital response signal, and close the delay measurement counter when a maximum peak value of the unit pulse digital response signal is detected;
and the time delay measuring module is used for dividing the counting value of the time delay measuring counter by the working frequency of the time delay measuring counter to obtain a calculation result which is used as the time delay value of the uplink or downlink digital link.
6. The apparatus of claim 5, further comprising: and the route switching module is used for switching the input end of the uplink or downlink digital link to the test data path and switching the output end of the uplink or downlink digital link to the peak value detection path before the signal generation module acquires the output signal containing all-zero data.
7. The apparatus according to claim 5 or 6, wherein the signal generation module is specifically configured to:
obtaining a unit pulse digital signal according to a received output request signal for starting the unit pulse digital signal; and obtaining a unit pulse digital response signal according to the excitation of the unit pulse digital signal to the digital link.
8. The apparatus of claim 5 or 6, wherein the delay measurement counter counts in units of counts of an operating clock of the upstream or downstream digital link.
9. A method for measuring link delay based on unit impulse response is characterized in that the method comprises the following steps:
acquiring a fixed time delay value of an uplink or a downlink of at least one braking type scene;
the method for measuring the link delay based on the unit impulse response according to any one of claims 1 to 4, obtaining the delay value of the uplink or downlink digital link of at least one manufacturing scenario;
and adding the fixed time delay value of the uplink or downlink and the time delay value of the uplink or downlink digital link to obtain the total time delay value of the uplink or downlink.
10. The method of claim 9, wherein the fixed delay value comprises: a fiber delay value and an analog link delay value.
11. A link delay measurement device based on unit impulse response, the device comprising: the device comprises a first acquisition module, a second acquisition module and a calculation module; wherein,
the first obtaining module is configured to obtain a fixed time delay value of an uplink or a downlink of at least one braking scenario;
the second obtaining module is configured to obtain a delay value of an uplink or downlink digital link of at least one braking type scene; the second acquisition module is the link delay measurement device based on unit impulse response of any one of claims 5 to 8;
and the calculation module is used for adding the fixed time delay value of the uplink or downlink and the time delay value of the uplink or downlink digital link to obtain the total time delay value of the uplink or downlink.
12. The apparatus according to claim 11, wherein the first obtaining module is specifically configured to obtain the fiber delay value and the analog link delay value of the uplink or downlink of at least one braking scenario.
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