CN108321121B - Method for manufacturing back gate type semiconductor device - Google Patents

Method for manufacturing back gate type semiconductor device Download PDF

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CN108321121B
CN108321121B CN201710039744.8A CN201710039744A CN108321121B CN 108321121 B CN108321121 B CN 108321121B CN 201710039744 A CN201710039744 A CN 201710039744A CN 108321121 B CN108321121 B CN 108321121B
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CN108321121A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

The invention provides a manufacturing method of a back gate type semiconductor device, which is characterized in that after first annealing for eliminating defects of a high-K gate dielectric layer, firstly, an oxygen-rich material layer and an oxygen-absorbing material layer are sequentially formed on the surface of the high-K gate dielectric layer, and second annealing is carried out, wherein in the second annealing process, part of oxygen in the oxygen-rich material layer is diffused into the high-K gate dielectric layer, so that the oxygen vacancy defects in the high-K gate dielectric layer are reduced, the performance of the high-K gate dielectric layer is ensured, the oxygen-absorbing material layer can absorb the oxygen in the oxygen-rich material layer, and excessive oxygen is prevented from diffusing into the high-K gate dielectric layer and an interlayer dielectric layer to thicken the interlayer dielectric layer and influence the device performance; and secondly, carrying out third annealing after removing the oxygen absorption material layer and the oxygen-enriched material layer to reactivate the activity of the source drain region ions, reduce the resistance of the source drain region and improve the performance of the transistor.

Description

Method for manufacturing back gate type semiconductor device
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a manufacturing method of a back gate type semiconductor device.
Background
With the rapid development of integrated circuits, gate length and silicon dioxide (SiO)2) The gate stack structure combining the metal gate and the gate dielectric layer of the high-k material with low Equivalent Oxide Thickness (EOT) is widely applied because the gate Oxide layer is continuously reduced in Thickness, the phenomena of gate dielectric layer reliability problem, polysilicon gate depletion effect, pinning of fermi level, too high gate resistance, severe boron penetration and the like are more severe, and the further improvement of the characteristics of the semiconductor device is severely restricted. Currently, a high-K Gate dielectric/metal Gate technology includes a front Gate (Gate First) process and a back Gate (Gate Last) process, wherein the back Gate process generally forms a structure stacked by a high-K Gate dielectric layer and a metal Gate through a Gate replacement process after a source/drain region is formed, but an annealing temperature of an annealing step for eliminating the high-K Gate dielectric defect in the process is generally lower than that of a source/drain ion activation thermal annealing process, so that the activity degradation and even loss of originally activated source/drain ions can be caused, and the performance of a device is seriously reduced。
Therefore, a new method for manufacturing a back gate type semiconductor device is needed, which can solve the problem that the annealing process after the deposition of the high-K gate dielectric layer has an influence on the activity of ions in the source/drain region and improve the performance of the device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a back gate type semiconductor device, which can eliminate the influence of an annealing process after a high-K gate dielectric layer is deposited on the ion activity of a source region and a drain region, simultaneously guarantee the performance of the high-K gate dielectric layer and the ion activity of the source region and the drain region and improve the performance of the device.
In order to achieve the above object, the present invention provides a method of manufacturing a back gate type semiconductor device, comprising the steps of:
providing a semiconductor substrate, forming an interlayer dielectric layer on the surface of the semiconductor substrate, forming a gate groove in the interlayer dielectric layer, and forming a source drain region in the semiconductor substrate at two sides of the gate groove;
depositing a high-K dielectric material on the surface of the gate groove and the surface of the interlayer dielectric layer and carrying out primary annealing to form a high-K gate dielectric layer;
sequentially forming an oxygen-rich material layer and an oxygen absorption material layer on the surface of the high-K gate dielectric layer, and performing secondary annealing to diffuse part of oxygen in the oxygen-rich material layer into the high-K gate dielectric layer;
removing the oxygen absorbing material layer and the oxygen-enriched material layer, and carrying out third annealing;
and forming a metal gate in the gate groove.
Furthermore, the surface of the semiconductor substrate is provided with a fin part, the gate groove is positioned above the fin part, and the source and drain regions are positioned in the fin parts at two sides of the gate groove.
Further, before the high-K gate dielectric layer is formed, an interface protection layer is formed on the side wall of the gate groove.
Furthermore, the interface protection layer is made of silicon dioxide, silicon nitride or silicon oxynitride.
Further, the temperature of the first annealing is 500-600 ℃.
Further, the material of the oxygen-rich material layer is titanium nitride or tantalum nitride.
Furthermore, the oxygen absorbing material layer is made of any material capable of absorbing part of oxygen in the oxygen-rich material layer in the second annealing process.
Further, the oxygen absorption material layer is at least one of amorphous silicon, amorphous germanium, amorphous gallium arsenide, amorphous arsenic sulfide, amorphous selenium, amorphous oxide, amorphous carbide and amorphous nitride.
Further, the thickness of the oxygen absorption material layer is
Figure GDA0002881908630000021
Further, the temperature of the second annealing is 800-1000 ℃.
Further, the temperature of the third annealing is 800-1200 ℃.
Further, the semiconductor substrate comprises a first device region and a second device region, and the step of forming the metal gate in the gate trench comprises:
depositing a first functional function layer on the surfaces of the first device area and the second device area, wherein the first functional function layer covers the side wall and the bottom of the gate groove;
removing the first functional layer on the surface of the second device area, and reserving the first functional layer on the surface of the first device area;
depositing an adhesion layer on a surface of the first device region and the second device region;
and sequentially depositing a second function layer and electrode metal on the surfaces of the first device area and the second device area to form a metal gate in all the gate grooves.
Furthermore, the first function layer and the adhesion layer are both made of titanium nitride, the second function layer is made of titanium aluminum carbide, and the electrode metal is made of tungsten.
Compared with the prior art, the preparation method of the rear gate type semiconductor device comprises the steps of sequentially forming an oxygen-rich material layer and an oxygen-absorbing material layer on the surface of a high-K gate dielectric layer after primary annealing for eliminating the defects of the high-K gate dielectric layer, carrying out secondary annealing, and diffusing part of oxygen in the oxygen-rich material layer into the high-K gate dielectric layer in the secondary annealing process, so that the oxygen vacancy defects in the high-K gate dielectric layer are reduced, the performance of the high-K gate dielectric layer is ensured, the oxygen-absorbing material layer can absorb oxygen in the oxygen-rich material layer, and excessive oxygen is prevented from diffusing into the high-K gate dielectric layer and the interlayer dielectric layer to thicken the interlayer dielectric layer and influence the performance of the device; and secondly, carrying out third annealing after removing the oxygen absorption material layer and the oxygen enrichment material layer to reactivate the activity of ions in the source drain region, reduce the resistance of the source drain region, improve the performance of the transistor, simultaneously prevent the stress introduced into the high-K gate dielectric layer by the oxygen enrichment material layer and the oxygen absorption material layer, and further improve the performance of the high-K gate dielectric layer.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a back gate type semiconductor device according to an embodiment of the present invention;
fig. 2A to 2E are device sectional structures in the process of manufacturing a back gate type semiconductor device according to an embodiment of the present invention.
Detailed Description
The existing gate-last process generally comprises the following steps: firstly, forming a silicon dioxide gate dielectric/pseudo gate structure on the surface of a semiconductor substrate; then completing source/drain ion implantation and annealing activation processes in the semiconductor substrate at two sides of the silicon dioxide gate dielectric/pseudo gate structure; then, removing the silicon dioxide gate dielectric/pseudo gate through CMP planarization and corrosion treatment to form a gate groove; then, depositing the high-K gate dielectric again, and carrying out spike annealing treatment to reduce the defects of oxygen vacancy and the like in the high-K gate dielectric layer and improve the compactness of the high-K gate dielectric layer; and forming a metal gate on the high-K gate dielectric layer of the gate groove, thereby completing the preparation of the high-K gate dielectric/metal gate semiconductor device. The gate-last process has the advantages that the metal gate is formed after the source/drain ion activation thermal annealing process, the influence of a high-temperature process on the characteristics of the metal gate is avoided, the device obtains high stability and consistency, and the high-performance high-K gate dielectric/metal gate semiconductor device and circuit are favorably formed.
The core idea of the invention is as follows: after the annealing step for eliminating the defects of the high-K gate dielectric, sequentially forming an oxygen-rich material layer and an oxygen-absorbing material layer on the surface of the high-K gate dielectric layer, and carrying out secondary annealing, wherein in the secondary annealing process, part of oxygen in the oxygen-rich material layer is diffused into the high-K gate dielectric layer, so that the oxygen vacancy defects in the high-K gate dielectric layer are reduced, the performance of the high-K gate dielectric layer is ensured, the oxygen-absorbing material layer can absorb the oxygen in the oxygen-rich material layer, and excessive oxygen is prevented from diffusing into the high-K gate dielectric layer and the interlayer dielectric layer to thicken the interlayer dielectric layer, so that the device performance is influenced; and secondly, carrying out third annealing after removing the oxygen absorption material layer and the oxygen enrichment material layer to reactivate the activity of ions in the source drain region, reduce the resistance of the source drain region, improve the performance of the transistor, simultaneously prevent the stress introduced into the high-K gate dielectric layer by the oxygen enrichment material layer and the oxygen absorption material layer, and further improve the performance of the high-K gate dielectric layer.
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
Referring to fig. 1, the present invention provides a method for manufacturing a back gate type semiconductor device, comprising the following steps:
s1, providing a semiconductor substrate, forming an interlayer dielectric layer on the surface of the semiconductor substrate, forming a gate groove in the interlayer dielectric layer, and forming a source drain region in the semiconductor substrate at two sides of the gate groove;
s2, depositing high-K dielectric materials on the surface of the gate groove and the surface of the interlayer dielectric layer, and performing primary annealing to form a high-K gate dielectric layer;
s3, sequentially forming an oxygen-rich material layer and an oxygen-absorbing material layer on the surface of the high-K gate dielectric layer, and performing secondary annealing to diffuse part of oxygen in the oxygen-rich material layer into the high-K gate dielectric layer;
s4, removing the oxygen absorbing material layer and the oxygen-enriched material layer, and carrying out third annealing;
and S5, forming a metal gate in the gate groove.
Referring to fig. 2A, in step S1, a semiconductor substrate 200 is provided, an interlayer dielectric layer 202 is formed on the semiconductor substrate 200, a gate trench 203 is formed in the interlayer dielectric layer 202, and source/drain regions 201 are formed in the semiconductor substrate 200 at two sides of the gate trench 203. Gate trench 203 and source drain regions 201 may be formed by any suitable method known in the art. In the present embodiment, the semiconductor substrate 200 may include any semiconductor material, such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, an alloy semiconductor, or other compound semiconductors, and the semiconductor substrate 200 may also be a stacked semiconductor structure, such as Si/SiGe, silicon-on-insulator (SOI), or silicon germanium-on-insulator (SGOI), or the like. The semiconductor substrate 200 in this embodiment is a structure having a fin 200a, and an active region thereof may be divided into a first device region I (e.g., a PMOS device region) and a second device region II (e.g., an NMOS device region). The specific process of step S1 in this embodiment includes:
firstly, providing a semiconductor substrate 200, and vertically etching the semiconductor substrate 200 to form a fin part 200 a;
then, a dummy gate dielectric layer (not shown), a dummy gate electrode (not shown), a hard mask layer (not shown) and a photoresist layer (not shown) are sequentially formed on the surfaces of the semiconductor substrate 200 and the fin portion 200a, and the photoresist layer is patterned;
then, with the photoresist layer as a mask, sequentially etching the hard mask layer, the dummy gate layer and the dummy gate dielectric layer to form a dummy gate structure (not shown) located at the top of the fin portion 200a, and then forming one or more layers of sidewalls of a dielectric material structure, such as silicon dioxide or silicon nitride, on the sidewalls of the dummy gate structure through sidewall deposition and etching processes;
then, according to the existing source-drain region forming process and the type required by the device, a source-drain region 201 is formed in the fin portions on both sides of the dummy gate structure, for example, the source-drain region 201 may be formed in the fin portions on both sides of the dummy gate structure by processes of lightly doped source-drain region ion implantation, heavily doped source-drain region ion implantation, high temperature annealing, and the like, or the source-drain region 201 may be formed in the fin portions on both sides of the dummy gate structure by performing selective epitaxy in the fin portions on both sides of the dummy gate structure, or an embedded source-drain region such as e-SiGe, e-SiGeC, and the like, and the specific process of the source-drain region ion implantation process or the embedded source-drain region epitaxy;
then, depositing an interlayer dielectric layer 202 on the surfaces of the semiconductor substrate 200 and the dummy gate structure, wherein the material of the interlayer dielectric layer can be silicon oxide, silicon nitride, silicon oxynitride or low-K dielectric with dielectric constant lower than that of silicon dioxide, and removing the interlayer dielectric layer on the top of the dummy gate structure by a chemical mechanical planarization process to expose the upper surface of the dummy gate structure;
next, the dummy gate structure (including the dummy gate dielectric layer and the dummy gate layer) is removed by a wet etching process to form a gate trench in the interlayer dielectric layer 202.
Referring to fig. 2A and 2B, in step S2, first, an interface protection layer 204 is formed on the sidewall of the gate trench 203 by thermal oxidation or chemical vapor deposition, and the interface protection layer 204 mainly protects the source/drain regions 201 from the subsequent deposition of high-K dielectric material and the annealing process; next, a chemical vapor deposition process or a monoatomic layer deposition process may be used to deposit a high-K dielectric material on the surface of the gate trench 203 and the surface of the interlayer dielectric layer 202, and perform a first annealing to form the high-K gate dielectric layer 205. Wherein the high-K dielectric material has a dielectric constant K value of 4 or more, and can be selected from hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxynitride (HfTaON), hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Hafnium titanium oxide (HfTiO), lanthanum oxide (La)2O3) Lanthanum aluminum oxide (LaAlO), lanthanum silicon oxide (LaSiO), zirconium silicon oxide (ZrSiO), titanium oxide (TiO)2) Tantalum oxide (Ta)2O5) Barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO) and aluminum oxide (Al)2O3) Aluminum nitride (AlN), yttrium oxide (Y)2O3) At least one of (1). The first annealing process is microwave annealing, rapid thermal annealing or laser annealing, the annealing temperature is 500-600 ℃, and the first annealing can eliminate partial defects in the high-K gate dielectric layer 205 and improve the compactness thereof. Meanwhile, the interface protection layer 204 can prevent oxygen in the first annealing atmosphere from reaching the interface with the source/drain region 201 through the high-K gate dielectric layer 205 and react to generate an oxide interface layer, so that the equivalent oxide layer thickness of the device is increased. The first annealing for eliminating the defects of the high-K gate dielectric layer 205 may affect the activity of the dopant ions in the source/drain region 201 because the temperature is lower than the annealing temperature for activating the dopant ions in the source/drain region 201 when the source/drain region 201 is formed.
In other embodiments of the present invention, in order to maintain the amorphous characteristic of the high-K gate dielectric layer 205, the high-K gate dielectric layer 205 may be doped, for example, with nitrogen, silicon, or aluminum to improve its thermal stability.
With continued reference to fig. 2B, in step S3, an oxygen-rich material layer 206 and an oxygen-gettering material layer 207 are sequentially deposited on the surface of the high-K gate dielectric layer 205, and a second annealing is performed. The oxygen-rich material layer 206 is deposited mainly to diffuse oxygen into the high-K gate dielectric layer 205 during the second annealing process to reduce oxygen vacancy defects in the high-K gate dielectric layer 205 and ensure the performance of the high-K gate dielectric layer 205, and the oxygen-rich material layer 206 may be titanium nitride or tantalum nitride. The deposited oxygen-absorbing material layer 207 may be any material capable of absorbing a part of oxygen in the oxygen-rich material layer 206 during the second annealing, and the oxygen-absorbing material layer 207 absorbs excess oxygen in the oxygen-rich material layer 206 during the second annealing to prevent excess oxygen from diffusing into the high-K gate dielectric layer 205, the interlayer dielectric layer 202 and the interface protection layer 204, so that the interlayer dielectric layer 202 and the interface protection layer 204 are formed204 become thicker, resulting in poor device performance. The oxygen absorbing material layer 207 may be an amorphous material, for example, at least one of amorphous silicon (α -Si), amorphous germanium (α -Ge), amorphous gallium arsenide (α -GaAs), amorphous arsenic sulfide (α -AsS), amorphous selenium (α -Se), amorphous oxide (e.g., indium gallium zinc amorphous oxide IGZO, etc.), amorphous carbide (e.g., α -SiC, etc.), and amorphous nitride (e.g., α -SiN), and may have a thickness of at least one of
Figure GDA0002881908630000061
The second annealing process is spike annealing, rapid thermal annealing or laser annealing, and the annealing temperature is 600-1100 ℃, for example 800-1000 ℃. The temperature of the second annealing process is still lower than the annealing temperature for activating the doped ions in the source/drain region 201 when the source/drain region 201 is formed, which may further affect the activity of the ions in the source/drain region 201.
Referring to fig. 2C, in step S4, the oxygen-rich material layer and the oxygen-absorbing material layer on the surface of the high-K gate dielectric layer 205 may be removed by a wet etching process or a dry etching process; and then annealing for the third time to reactivate the doped ions in the source and drain regions, reduce the resistance of the source and drain regions 201, and improve the performance of the finally formed transistor device. The third annealing process is laser annealing, rapid thermal annealing or spike annealing, the annealing temperature can be higher than the first annealing and the second annealing, and the annealing temperature can be in the range of 800-1200 ℃. The high-K gate dielectric layer 205 processed in step S3 has good thermal stability and mechanical strength, and therefore can withstand the high temperature processing of the third annealing, and the third annealing is performed after the oxygen-rich material layer and the oxygen-absorbing material layer on the surface of the high-K gate dielectric layer 205 are removed, so that the oxygen-rich material layer 206 and the oxygen-absorbing material layer 207 can be prevented from generating stress during the third annealing to impact the high-K gate dielectric layer 205, and the high-K gate dielectric layer 205 is prevented from being broken, thereby reducing the leakage current of the formed transistor.
In the present embodiment, since the semiconductor substrate 200 has two device regions: a first device region I and a second device region II, which are formed in opposite device types, so that in step S5, metal gates need to be formed in gate trenches of the first device region I and the second device region II, respectively, and the specific process includes:
first, referring to fig. 2D, a first functional layer 208 may be deposited on the interlayer dielectric layer 202 and all the surfaces of the gate trenches by ALD (atomic layer deposition), PVD (physical vapor deposition), CVD (chemical vapor deposition), e-beam evaporation or other suitable processes, the first functional layer 208 may be a titanium nitride (TiN) layer, the deposition thickness of which is not enough to fill the gate trenches 203, and the specific deposition thickness is determined according to the device requirements, for example
Figure GDA0002881908630000071
Then, with continued reference to fig. 2D, the first functional layer 208 on the surface of the second device region II may be removed by a wet etching process, while the first functional layer 208 on the surface of the first device region I remains. The wet etching solution can be SC1 or SC2 solution, and NH in the SC1 solution4OH、H2O2And H2The molar volume ratio of O is 1:1: 5-1: 2:7, and HCl and H are contained in the SC2 solution2O2And H2The molar volume ratio of O is 1:1: 6-1: 2: 8.
Next, with continued reference to fig. 2D, an adhesion layer 209 is deposited on the surface of the first device region I and the surface of the second device region II, and specifically, the adhesion layer 209 may be deposited on the surface of the first functional function layer 208 of the first device region I and the surface of the high-K dielectric layer 205, the top surface of the interface protection layer 204 and the surface of the interlayer dielectric layer 202 of the second device region II by ALD (atomic layer deposition), PVD (physical vapor deposition), CVD (chemical vapor deposition), e-beam evaporation or other suitable processes, where the adhesion layer 209 may be TiN, and the deposition thickness is determined according to the device requirements, for example, the deposition thickness is determined by the device requirements
Figure GDA0002881908630000072
The thickness of the first functional layer 208 and the adhesion layer 209 in the gate trench of the first device region II is still insufficient to fill the gate trench 203.
Then, referring to fig. 2E, a second functional function layer 210 may be deposited on the surface of the first device region I and the surface of the second device region II by ALD (atomic layer deposition), PVD (physical vapor deposition), CVD (chemical vapor deposition), E-beam evaporation or other suitable process, and the second functional function layer 210 may be titanium aluminum carbide (TiAlC) deposited to a thickness still insufficient to fill the gate trench 203 of the first device region I.
Thereafter, with reference to fig. 2E, all the gate trenches 203 may be filled with an electrode metal 211 by a sputtering deposition or an electroplating process until the gate trenches 203 are filled, and the electrode metal 211 may be made of tungsten (W).
Thereafter, with continued reference to fig. 2E, the excess material on the surface of the interlayer dielectric layer 202, including the high-K gate dielectric layer 205, the first functional function layer 208, the adhesion layer 209, the second functional function layer 210 and the electrode metal 211, may be removed by a chemical mechanical planarization process.
In this embodiment, the first functional layer 208 and the second functional layer 210 are both single-layer structures. The first and second functional function layers 208 and 210 may also be a stacked structure in other embodiments of the present invention, such as various combinations of work function metal layers, liner layers, wetting layers, adhesion layers, metal alloys, or metal silicides that have selective work functions to improve device performance. Since the first device region I and the second device region II form different device types, the first functional layer 208 and the second functional layer 210 are made of different materials. In other embodiments of the present invention, the material of the first functional layer 208 may also be selected from at least one of titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), copper (Cu), tungsten (W), rhenium (Re), iridium (Ir), cobalt (Co), nickel (Ni), nickel silicide (NiSi), cobalt silicide (CoSi), the material of the second functional function layer 210 is at least one selected from titanium, silver, aluminum, titanium aluminum nitride, tantalum carbide, tantalum carbon nitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, copper, tungsten, rhenium, iridium, cobalt, nickel silicide, and cobalt silicide. For example, the first device region I is used to form an n-channel FinFET, the first functional function layer 208 may be one or more layers of TaN, TiAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi, and the second device region II is used to form a p-channel FinFET, and the second functional function layer 210 may be one or more layers of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co. And the adhesion layer 209 is selected from one or more of titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel silicide (NiSi), and cobalt silicide (CoSi). The electrode metal 211 is made of one or a combination of aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), cobalt (Co), manganese (Mn), zirconium (Zr), ruthenium (Ru), molybdenum (Mo), rhenium (Re), iridium (Ir), thallium (Tl), palladium (Pd), tantalum (Ta), and tungsten (W).
In order to further improve the device performance, the functional function of the first functional function layer 208 and the second functional function layer 210 can be adjusted by doping ions In the functional function layers, wherein for NMOS, the doping ions for adjusting the work function include aluminum (Al), gallium (Ga), indium (In), boron (B), and combinations thereof; for PMOS, the dopant ions that adjust the work function include antimony (Sb), arsenic (As), phosphorus (P), nitrogen (N), argon (Ar), and combinations thereof.
In summary, according to the manufacturing method of the back gate type semiconductor device of the present invention, after the first annealing for eliminating the defect of the high K gate dielectric layer, firstly, an oxygen-rich material layer and an oxygen-absorbing material layer are sequentially formed on the surface of the high K gate dielectric layer, and the second annealing is performed, wherein during the second annealing, a part of oxygen in the oxygen-rich material layer is diffused into the high K gate dielectric layer, so as to reduce the oxygen vacancy defect in the high K gate dielectric layer, ensure the performance of the high K gate dielectric layer, and the oxygen-absorbing material layer can absorb oxygen in the oxygen-rich material layer, so as to prevent excessive oxygen from diffusing into the high K gate dielectric layer and the interlayer dielectric layer to thicken the interlayer dielectric layer, thereby affecting the device performance; and secondly, carrying out third annealing after removing the oxygen absorption material layer and the oxygen enrichment material layer to reactivate the activity of ions in the source drain region, reduce the resistance of the source drain region, improve the performance of the transistor, simultaneously prevent the stress introduced into the high-K gate dielectric layer by the oxygen enrichment material layer and the oxygen absorption material layer, and further improve the performance of the high-K gate dielectric layer.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (13)

1. A method of manufacturing a back gate type semiconductor device, comprising the steps of:
providing a semiconductor substrate, forming an interlayer dielectric layer on the surface of the semiconductor substrate, forming a gate groove in the interlayer dielectric layer, and forming a source drain region in the semiconductor substrate at two sides of the gate groove;
depositing a high-K dielectric material on the surface of the gate groove and the surface of the interlayer dielectric layer and carrying out primary annealing to form a high-K gate dielectric layer;
sequentially forming an oxygen-rich material layer and an oxygen absorption material layer on the surface of the high-K gate dielectric layer, and carrying out secondary annealing to diffuse part of oxygen in the oxygen-rich material layer into the high-K gate dielectric layer so as to reduce oxygen vacancy defects in the high-K gate dielectric layer, and absorbing redundant oxygen in the oxygen-rich material layer through the oxygen absorption material layer so as to prevent redundant oxygen in the oxygen-rich material layer from diffusing into the high-K gate dielectric layer, the interlayer dielectric layer and the interface protective layer;
removing the oxygen absorbing material layer and the oxygen-enriched material layer, and carrying out third annealing;
and forming a metal gate in the gate groove.
2. The method of manufacturing a back gate semiconductor device according to claim 1, wherein the surface of the semiconductor substrate has a fin, the gate trench is located above the fin, and the source and drain regions are located in the fin on both sides of the gate trench.
3. The method of manufacturing a back gate type semiconductor device according to claim 1, wherein an interface protection layer is formed on the sidewall of the gate trench before the high-K gate dielectric layer is formed.
4. The method of manufacturing a back gate semiconductor device according to claim 3, wherein the interface protection layer is made of silicon dioxide, silicon nitride, or silicon oxynitride.
5. The method for manufacturing a back gate type semiconductor device according to claim 1, wherein the temperature of the first annealing is 500 to 600 ℃.
6. The method for manufacturing a back gate type semiconductor device according to claim 1, wherein a material of the oxygen-rich material layer is oxygen-containing titanium nitride or oxygen-containing tantalum nitride.
7. The method according to claim 1, wherein the oxygen-absorbing material layer is made of any material that can absorb part of oxygen in the oxygen-rich material layer during the second annealing.
8. The method for manufacturing a back-gate type semiconductor device according to claim 7, wherein the oxygen-absorbing material layer is at least one of amorphous silicon, amorphous germanium, amorphous gallium arsenide, amorphous arsenic sulfide, amorphous selenium, amorphous oxide, amorphous carbide, and amorphous nitride.
9. The method of manufacturing a back-gate semiconductor device according to claim 8, wherein the oxygen-gettering material layer has a thickness of
Figure FDA0002881908620000021
。
10. The method for manufacturing a back gate type semiconductor device according to claim 1, wherein the temperature of the second annealing is 800 to 1000 ℃.
11. The method for manufacturing a back gate type semiconductor device according to claim 1, wherein the temperature of the third annealing is 800 to 1200 ℃.
12. The method of manufacturing a back gate type semiconductor device according to claim 1, wherein the semiconductor substrate includes a first device region and a second device region, and the step of forming a metal gate in the gate trench includes:
depositing a first functional function layer on the surfaces of the first device area and the second device area, wherein the first functional function layer covers the side wall and the bottom of the gate groove;
removing the first functional layer on the surface of the second device area, and reserving the first functional layer on the surface of the first device area;
depositing an adhesion layer on a surface of the first device region and the second device region;
and sequentially depositing a second function layer and electrode metal on the surfaces of the first device area and the second device area to form a metal gate in all the gate grooves.
13. The method for manufacturing a back-gate semiconductor device according to claim 12, wherein the first functional layer and the adhesion layer are both made of titanium nitride, the second functional layer is made of titanium aluminum carbide, and the electrode metal is made of tungsten.
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