CN108319560B - Conversion circuit of TLK2711 transmission interface and Camera-Link transmission interface - Google Patents
Conversion circuit of TLK2711 transmission interface and Camera-Link transmission interface Download PDFInfo
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- CN108319560B CN108319560B CN201810215519.XA CN201810215519A CN108319560B CN 108319560 B CN108319560 B CN 108319560B CN 201810215519 A CN201810215519 A CN 201810215519A CN 108319560 B CN108319560 B CN 108319560B
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 64
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 27
- 238000012545 processing Methods 0.000 claims abstract description 8
- 238000013139 quantization Methods 0.000 claims description 4
- 238000013461 design Methods 0.000 description 5
- 238000003384 imaging method Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008521 reorganization Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a conversion circuit of a TLK2711 transmission interface and a Camera-Link transmission interface, which comprises a data serial input unit, an FPGA unit and a data output unit; the data serial input unit comprises an external connector and at least one TLK2711 receiving chip; the FPGA unit comprises processing units which are in one-to-one correspondence with the TLK2711 receiving chips, wherein the processing units comprise an input logic unit, a FIFO and an output logic unit; the data output unit comprises a Camera-Link transmitting chip and a Camera-Link interface which are in one-to-one correspondence with the TLK2711 receiving chip; the TLK2711 receiving chip is connected with the external connector in series; the input end of the input logic unit is connected with the output end of the TLK2711 receiving chip; the input end of the FIFO is connected with the output end of the input logic unit; the input end of the output logic unit is connected with the output end of the FIFO, the output end of the output logic unit is connected with the input end of the Camera-Link transmitting chip, and the Camera-Link interface is connected with the Camera-Link transmitting chip in series. The invention solves the practical application problem of converting the TLK2711 data transmission interface to the Camera-Link standard image transmission interface.
Description
Technical Field
The invention belongs to the field of high-speed data transmission, and relates to the technical field of conversion from high-speed serial data to high-speed parallel data, in particular to a conversion circuit of a TLK2711 transmission interface and a Camera-Link transmission interface.
Background
With the development of space remote sensing technology in China, satellite remote sensing has increasingly developed trend of high time resolution, high space resolution and high spectrum resolution, load data types are more and more diversified, data volume is more and more large, and data rate, bandwidth and the like are developed from past several Mbps to current several Gbps or even higher. The data transmission is gradually changed from the traditional adoption of a multi-path LVDS parallel transmission interface to a higher-bandwidth and higher-reliability interface, such as the application based on a high-speed serial/deserializing transceiver TLK2711, the single-path transmission rate of the TLK2711 is up to 2.5Gbps, and meanwhile, the TLK2711 adopts a self-synchronous communication mode, and the clock and data recovery technology is utilized to replace synchronous transmission data and clock, so that the problems of signal and clock offset are effectively solved; in addition, the serial communication technology is adopted, so that equipment and cable wiring are simpler, and the anti-interference capability of the system is stronger.
The TLK2711 is convenient for the transmission of the satellite-borne high-resolution imaging data, but for the satellite-borne high-resolution imaging equipment, the connection relation between the satellite-borne high-resolution imaging equipment and an acquisition storage computer cannot be directly established in the ground demonstration verification stage (the current computer universal interface does not have the novel transmission interface), while the Camera-Link interface is very mature in image acquisition transmission along with the technical development of years, and a large number of industrialized Camera-Link-to-PCI/PCI-E acquisition cards are available in the market. Therefore, it is important to design an efficient real-time image data interface conversion circuit to convert the TLK2711 data interface into a standard Camera-Link protocol data interface, and it can provide an advantageous technical support for the high-resolution imaging technology.
Disclosure of Invention
In order to realize the protocol conversion between the TLK2711 interface and the Camera-Link interface of the high-speed data serial bus, the invention provides a conversion circuit of the TLK2711 transmission interface and the Camera-Link transmission interface, which is easy to realize, and provides a new technical means and method for real-time storage and display of the TLK2711 transmission data on a computer.
The technical scheme of the invention is as follows:
a conversion circuit of a TLK2711 transmission interface and a Camera-Link transmission interface is characterized in that: the device comprises a data serial input unit, an FPGA unit and a data output unit;
the data serial input unit comprises an external connector and at least one TLK2711 receiving chip;
the FPGA unit comprises processing units which are in one-to-one correspondence with the TLK2711 receiving chips, and the processing units comprise an input logic unit, a FIFO and an output logic unit;
the data output unit comprises a Camera-Link transmitting chip and a Camera-Link interface which are in one-to-one correspondence with the TLK2711 receiving chip;
the TLK2711 receiving chip is connected with the external connector in series;
the input end of the input logic unit is connected with the output end of the TLK2711 receiving chip, and the transmitted data are converted into a data form taking pixels as units;
the input end of the FIFO is connected with the output end of the input logic unit, and data caching is carried out according to pixels;
the input end of the output logic unit is connected with the output end of the FIFO, the output end of the output logic unit is connected with the input end of the Camera-Link transmitting chip, and the output logic unit generates line synchronization, frame synchronization, data effective signals and data according to the size and quantization bit number of an actual image and transmits the data to the Camera-Link transmitting chip according to a Camera-Link data transmission protocol;
the Camera-Link interface is connected with the Camera-Link transmitting chip in series.
Further, in order to send command words to the output logic unit to adjust the size format of the output image, the conversion circuit of the TLK2711 transmission interface and the Camera-Link transmission interface further includes a control input unit and a connector thereof, an output end of the control input unit is connected with an input end of the output logic unit, an input end of the control input unit is connected with an output end of the connector, and an input end of the connector is used for being connected with an output end of a lower computer or a computing and storage device, namely, the connector is also an external connector, and an input end of the control input unit is connected with an output end of the lower computer or the computer storage device through the connector.
Further, the external connector is an MKHS connector.
Further, the model of the FPGA is XC4VSX55-10FF1148I.
Further, the Camera-Link transmitting chip adopts a DS90CR287 chip.
Further, the Camera-Link interface is an MDR26 standard interface.
Compared with the prior art, the invention has the advantages that:
1. the invention adopts the FPGA unit, sets the processing unit (comprising the input logic unit, the FIFO and the output logic unit) corresponding to the TLK2711 receiving chip one by one, converts the input data into a data form taking pixels as units, caches the data according to the pixels, generates line synchronization, frame synchronization, data effective signals and data, constructs and forms a conversion circuit between the TLK2711 transmission interface and the Camera-Link transmission interface, solves the practical application problem of converting the TLK2711 data transmission interface into the Camera-Link standard image transmission interface, and provides a new hardware architecture for mass data output of the current high-resolution imager.
2. The conversion circuit of the TLK2711 transmission interface and the Camera-Link transmission interface can configure the image size of the Camera-Link output interface through controlling the input unit instruction, so that the conversion circuit has certain universality, is reasonable and reliable in design, and can complete high-speed real-time data transmission with the bandwidth of 2.98 Gbps.
3. The conversion circuit of the TLK2711 transmission interface and the Camera-Link transmission interface provided by the invention has the advantages of high image resolution, good instantaneity and low error rate; and has the advantages of small volume, portability, simplicity, convenience, stable working performance and the like.
4. The conversion circuit of the TLK2711 transmission interface and the Camera-Link transmission interface provided by the invention has wide application prospect, and can be used for the following purposes: high resolution imaging spectrometer, stereo mapping camera, wide bandwidth visible light camera, short wave infrared camera, etc.
5. The invention has good economy and practicability, the board card can be matched with PCI-E image acquisition cards widely used in the market to conveniently display and store images, and a user does not need to spend effort to develop special acquisition display software.
Drawings
FIG. 1 is a schematic diagram of an example of the present invention;
FIG. 2 is a block diagram of a conversion circuit according to the present invention;
fig. 3 is a block diagram showing the constitution of a conversion circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples.
As shown in FIG. 1, the invention is mainly designed for a conversion circuit from a TLK2711 data transmission interface to a Camera-Link image data transmission interface, and realizes the conversion from the TLK2711 data transmission interface to a Camera-Link standard image transmission interface.
As shown in fig. 2-3, the high-speed data transmission interface conversion circuit board card provided by the invention comprises an FPGA unit, a FLASH memory unit, a data serial input unit, a data output unit, a control input unit, a crystal oscillator unit and a power supply and distribution unit.
(1) Data serial input unit
The data serial input unit consists of an interface connector and a TLK2711 receiving chip, wherein the TLK2711 receiving chip is a high-speed serial/deserializing transceiver; in the specific application implementation case, the connector adopts an MKHS connector produced by AirBorn company, 2 TLK2711 receiving chips are used in design according to engineering requirements, and a single working clock is 100Mhz; the 2 TLK2711 receiving chips respectively decode the respectively input high-speed serial data into 16bit parallel data, 1 path of 100Mhz associated clock and 2 paths of K/D coding control signals (the 2 paths of signals are used for judging whether the data are valid data according to an originating data format protocol); the TLK2711 receiving chip deserializes the serial data and outputs the data stream to the FPGA unit in a bus mode for data processing.
(2) FPGA unit
The FPGA unit receives data, a clock and control signals input by the data serial input unit, the FPGA invokes an internal input logic unit through internal operation software to realize data recombination, the recombined data is stored in an internal memory FIFO module of the FPGA unit, and an internal output logic unit generates line synchronization, frame synchronization, data effective signals and data according to the size and quantization bit number of an actual image and sends the data to the data output unit according to a Camera-Link data transmission protocol. Specifically, in an actual application case of the invention, xilinx company FPGA model XC4VSX55-10FF1148I is selected, an internal input logic unit thereof is used for re-splitting 16bit data into each pixel with 12bit depth according to a data transmission format of an originating high-resolution imager, so that the data is stored according to the pixel when the FIFO is stored, namely, the FIFO bit width is set to be 12bit, and the bit depth is specifically set according to the size of an image; the TLK2711 receiving chip 1 receives data through a data recombination, FIFO buffer memory and output logic unit and then sends the data to the Camera-Link transmitting chip 1, and the TLK2711 receiving chip 2 receives data through the data recombination, FIFO buffer memory and output logic unit and then sends the data to the Camera-Link transmitting chip 2; the output logic unit sends the image data according to the Camera-Link image transmission protocol, in this case, a Medium format is adopted, and each channel outputs a row 1 channel synchronizing signal, a row 1 channel frame synchronizing signal, a row 1 channel data valid signal, 24bit parallel image data (2 pixels) and a row 1 channel clock 80Mhz respectively.
The FPGA unit also needs to respond to the control command of the control input unit and give a response in time, and the size of the effective image of the Camera-Link is regulated and output according to the command word (namely, the image is set to be m rows and n columns), so that the invention has better universality.
An input logic unit in the FPGA unit respectively carries out data recombination on received data streams; the part of the technical personnel in the art carries out data reorganization according to the transmission protocol of the data transmitting end, namely, 16bit data transmitted by a TLK2711 receiving chip are sequentially converted into pixels; for example, a 12bit quantized image, if it is transmitted according to 16 bits, it needs to compose 3 16bit data every 4 pixels, and sequentially transmit the data in 3 beats, and then the data reorganization needs to reorganize the data in 3 beats into 4 pixels. This is based on the art designer custom image transmission format, i.e. the restoration of the custom transmission image.
And an output logic unit in the FPGA unit generates line synchronization, frame synchronization, data effective signals and data according to the size and quantization bit number of an actual image, and sends the line synchronization, the frame synchronization, the data effective signals and the data to a Camera-Link sending chip according to a Camera-Link data transmission protocol. Those skilled in the art can implement this part according to the specific format of the selected camellink transmission protocol, for example, base, medium, full is adopted, the design system only supports Base or Medium format, and the Medium mode is actually selected in implementation.
The control input unit sends command words to the FPGA to realize the adjustment of the size and the format of the output image; the control input unit receives command words sent by the lower computer/computer storage device through the serial port, the command words can be customized, and a logic unit running in the FPGA modifies line effective signals, frame effective signals, data effective signals and data sent to a special sending chip of the Camera-Link interface protocol according to the received control commands, so that the adjustment of the output size of an image is achieved.
(3) Data output unit
The data output unit consists of an output connector Camera-Link interface and a Camera-Link transmitting chip, and in the working process, a power supply and distribution unit is required to provide a working level and receive 1 path of synchronous signals, 1 path of frame synchronization, 1 path of data effective signals, 24bit parallel image data and 1 path of clock signals transmitted by the FPGA. In the design, 2 DS90CR287 is adopted to form a Medium format as a transmitting chip, and the working clock is 80Mhz; the Camera-Link interface adopts an MDR26 standard interface.
(4) Control input unit
The control input unit is used for sending command words to the FPGA unit to realize the adjustment of the size format of the output image, and serial communication is adopted. In particular to this case, the control input unit is constituted by a differential transceiver DS90LV019, the baud rate 9600, the external devices of which are input by a universal Camera-Link transmission cable integrated on the MDR26 interface.
(5) FLASH memory cell
The FLASH memory unit is a nonvolatile and electrically erasable programmable read-only memory and is mainly used for providing program loading for starting the FPGA. Specifically, in this case, a special FLASH configuration chip XCF32P of Xilinx company is used.
(6) Crystal oscillator unit
The crystal oscillator provides a working clock for the FPGA and is a source clock for the whole board card to work. In particular, in the present case, a 100Mhz external crystal oscillator is used.
(7) Power supply and distribution unit
The power supply and distribution unit comprises a power interface connector and a plurality of power conversion chips, and provides a plurality of types of power sources required for the work of the whole circuit device.
Claims (6)
1. A conversion circuit of a TLK2711 transmission interface and a Camera-Link transmission interface is characterized in that: the device comprises a data serial input unit, an FPGA unit and a data output unit;
the data serial input unit comprises an external connector and at least one TLK2711 receiving chip;
the FPGA unit comprises processing units which are in one-to-one correspondence with the TLK2711 receiving chips, and the processing units comprise an input logic unit, a FIFO and an output logic unit;
the data output unit comprises a Camera-Link transmitting chip and a Camera-Link interface which are in one-to-one correspondence with the TLK2711 receiving chip;
the TLK2711 receiving chip is connected with the external connector in series;
the input end of the input logic unit is connected with the output end of the TLK2711 receiving chip, and the transmitted data are converted into a data form taking pixels as units; the bit depth of the pixel converted by the input logic unit is 12 bits;
the input end of the FIFO is connected with the output end of the input logic unit, and data caching is carried out according to pixels;
the input end of the output logic unit is connected with the output end of the FIFO, the output end of the output logic unit is connected with the input end of the Camera-Link transmitting chip, and the output logic unit generates line synchronization, frame synchronization, data effective signals and data according to the size and quantization bit number of an actual image and transmits the data to the Camera-Link transmitting chip according to a Camera-Link data transmission protocol;
the Camera-Link interface is connected with the Camera-Link transmitting chip in series.
2. The conversion circuit of a TLK2711 transmission interface and a Camera-Link transmission interface according to claim 1, wherein:
the control input unit is connected with the input end of the output logic unit, the input end of the control input unit is connected with the output end of the connector, and the input end of the connector is used for being connected with the output end of a lower computer or computing and storage equipment.
3. The conversion circuit of a TLK2711 transmission interface and a Camera-Link transmission interface according to claim 1 or 2, wherein: the external connector is an MKHS connector.
4. The conversion circuit of a TLK2711 transmission interface and a Camera-Link transmission interface according to claim 1 or 2, wherein: the model of the FPGA is XC4VSX55-10FF1148I.
5. The conversion circuit of a TLK2711 transmission interface and a Camera-Link transmission interface according to claim 1 or 2, wherein: the Camera-Link transmitting chip adopts a DS90CR287 chip.
6. The conversion circuit of a TLK2711 transmission interface and a Camera-Link transmission interface according to claim 1 or 2, wherein: the Camera-Link interface is an MDR26 standard interface.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810186505 | 2018-03-07 | ||
| CN201810186505X | 2018-03-07 |
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| CN108319560A CN108319560A (en) | 2018-07-24 |
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| CN201820353941.7U Withdrawn - After Issue CN208156657U (en) | 2018-03-07 | 2018-03-15 | Conversion circuit of T L K2711 transmission interface and Camera-L ink transmission interface |
| CN201810215519.XA Active CN108319560B (en) | 2018-03-07 | 2018-03-15 | Conversion circuit of TLK2711 transmission interface and Camera-Link transmission interface |
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| CN109413354B (en) * | 2018-11-19 | 2021-08-06 | 天津津航技术物理研究所 | Infrared detector interface switching device |
| CN109491940A (en) * | 2018-12-18 | 2019-03-19 | 中国科学院西安光学精密机械研究所 | Conversion circuit and conversion method for TLK2711 transmission interface and USB3.0 transmission interface |
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| CN108319560A (en) | 2018-07-24 |
| CN208156657U (en) | 2018-11-27 |
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