CN108304658B

CN108304658B - FPGA-based polarization code encoder hardware implementation method

Info

Publication number: CN108304658B
Application number: CN201810107445.8A
Authority: CN
Inventors: 王秀敏; 吴卓铤; 王怡; 李君�; 洪波
Original assignee: China Jiliang University
Current assignee: China Jiliang University
Priority date: 2018-02-02
Filing date: 2018-02-02
Publication date: 2020-05-19
Anticipated expiration: 2038-02-02
Also published as: CN108304658A

Abstract

The invention discloses a hardware implementation method of a polarization code encoder based on an FPGA (field programmable gate array). the method is mainly used for solving the problems that the design of a parallel structure is difficult and the like due to strong correlation between the front and rear stages of a polarization code encoding structure, and a method for simplifying operation is designed on the basis of summarizing a polarization code encoding generation matrix rule. The method only needs to perform the operation of generating the first column of the matrix, and then the whole coding result can be obtained according to the rule. The method also introduces a ROM table look-up method as an initial calculation unit on the basis of solving the parallel problem, thereby greatly improving the overall operation speed of the encoder.

Description

FPGA-based polarization code encoder hardware implementation method

Technical Field

The invention belongs to the field of channel coding, and particularly relates to a polarization code encoder hardware implementation method based on an FPGA.

Background

Polarization code coding technique proposed by e.arika in 2007, which is a coding technique that under binary discrete memoryless channel conditions, a channel polarization phenomenon occurs when the code length tends to infinity, i.e., part of the channel capacity tends to 1 and part tends to 0. Under the condition, the polar code can reach the fragrance limit, and the complexity of the coding algorithm is low, so that the polar code coding becomes a great breakthrough on the channel coding history. Polar codes are a new coding technology, which attracts great attention in the wireless communication field. Is one of the most important research topics in the field of coding.

This makes the polar code have many difficulties in parallel design due to the high correlation between the front and back stages of the polar code coding structure. At present, the encoder design of the polarization code mainly refers to the processing idea of an FFT algorithm to carry out FPGA hardware design, but the method still belongs to serial operation. The invention designs a polarization code encoder with a parallel structure by utilizing the distribution rule of a G matrix and combining a table look-up method.

Disclosure of Invention

The polar code coding method mainly aims at the problems of the polar code coding in parallel design, and designs the polar code coder based on the FPGA by utilizing a table look-up method on the basis of summarizing the structural rule of a polar code coding generation matrix, thereby greatly improving the parallelism of the polar code coding.

The technical scheme adopted by the invention is as follows:

(1) and finding out the structural rule of the generated matrix. The structure of the polar code encoder is formed based on a unit matrix, and the unit matrix is as follows:

when the code length is 2ⁿThen, the relationship between the generating matrix and the unit matrix is:

wherein

Is a 2ⁿ×2ⁿAnd (4) matrix.

from the above characteristics, it can be seen that there must be many repeated calculations when the generator matrix is used for operation, and we can calculate the repeated part only once and replace the repeated part with the result.

Wherein A is:

let the information bit with length of 64 bits be C ═ C₀,c₁,c₂,c₃,c₄,c₅,c₆,c₇In which c is_iIs 8 bits. We can simplify in the following way, let a₁＝{a₀,a₁,a₂,a₃,a₄,a₅,a₆,a₇In which a_i＝c_iAnd (4) x A. Is provided withThe coded information sequence is S ═ S₀,s₁,s₂,s₃,s₄,s₅,s₆,s₇}, then there are

s₀＝a₀^a₁^a₂^a₃^a₄^a₅^a₆^a₇(5)

s₁＝a₁^a₃^a₅^a₇(6)

s₂＝a₂^a₃^a₆^a₇(7)

s₃＝a₃^a₇(8)

s₄＝a₄^a₅^a₆^a₇(9)

s₅＝a₅^a₇(10)

s₆＝a₆^a₇(11)

s₇＝a₇(12)

The formulas (5) to (12) are basic operation formulas of the algorithm, compared with direct operation, the method simplifies the operation process, only the operation of the first column is carried out, the speed is improved by 7 times on the whole, 0 element in the G matrix is directly removed in the later operation, and the G matrix is a sparse matrix, so that the calculation unit is saved to a great extent.

(2) FPGA-based encoder design. The encoder system is constructed as shown in fig. 1. The system comprises an information segmentation module, a table look-up coding module, an 8-bit coding result memory, a coding intermediate result memory, a coding structure arithmetic unit and an output module. Based on the simplified algorithm, the hardware design of the encoder is performed. In order to further simplify the operation and improve the throughput of the encoder, the encoder uses a table lookup method to perform table lookup on the eight-bit encoding result. Firstly, all the inputs (256 types in total) of an 8-bit encoder are subjected to encoding calculation through MATLAB to obtain an encoding result, then an 8-bit read-only memory ROM with the depth of 256 is created in QUARTUS II, information bits are used as the address of the ROM, and the encoding result is used as the storage information of the corresponding address in the ROM. In order to improve the parallelism, 2 double-port ROMs are established in the system, and 8-bit polarization code coding of 4 threads is carried out simultaneously. Under the same parallelism, the table look-up method saves 8 times of calculation period.

Drawings

FIG. 1 System Structure

FIG. 2256 bit encoder System flow diagram

Detailed Description

The following describes the present invention in detail with reference to fig. 2 by taking an FPGA polarization code encoder with a code length of 1024 as an example, and the specific implementation manner includes the following steps:

the method comprises the following steps: enabling an encoder, setting a cycle flag bit n to be 1, starting to receive 32-bit information bits, dividing the 32-bit information bits into four threads, respectively transmitting the four threads to a ROM (read only memory) for table look-up operation, and respectively outputting 4 8-bit coding sequences by the ROM. And stores the result in an encoded intermediate result store.

Step two: the code structure operator reads data from the intermediate result memory and calculates the 32-bit code sequence according to the algorithm described in technical solution (1). And stored in 32-bit encoded memory. And selecting whether to carry out the next group of coding according to the current coding code length of the coder.

Step three: and adding 1 to the cyclic flag bit, receiving the next group of 32-bit information bits, and repeating the operation of the step one and the step two.

Step four: when n is 9, the system stops receiving information bits, calls the coding structure arithmetic unit to read 8 32-bit coding sequences, and calculates 256 codes according to the algorithm in the technical scheme (1). And begins encoding the next 256-bit information sequence.

Claims

1. A method for realizing FPGA-based polar code encoder hardware is characterized by comprising the following steps:

(1) finding out the structural rule of the generator matrix G and designing a simplified method for calculating the generator matrix G;

(2) constructing a ROM for 8-bit coding table lookup;

the step (1) directly eliminates the 0 part in the generated matrix G in the calculation process by utilizing the structural rule of the generated matrix G to realize the simplified calculation of the generated matrix G, and comprises the following steps:

let the information bit with length of 64 bits be C ═ C₀，c₁，c₂，c₃，c₄，c₅，c₆，c₇In which c is_iIs 8 bits, it is simplified by the following way, let A₁＝{a₀，a₁，a₂，a₃，a₄，a₅，a₆，a₇}；

a_i＝c_iX A, wherein,

let the coded information sequence be S ═ S₀，s₁，s₂，s₃，s₄，s₅，s₆，s₇And then, there are:

s₀＝a₀^a₁^a₂^a₃^a₄^a₅^a₆^a₇(1)；

s₁＝a₁^a₃^a₅^a₇(2)；

s₂＝a₂^a₃^a₆^a₇(3)；

s₃＝a₃^a₇(4)；

s₄＝a₄^a₅^a₆^a₇(5)；

s₅＝a₅^a₇(6)；

s₆＝a₆^a₇(7)；

s₇＝a₇(8)；

the expressions (1) to (8) are basic operation expressions of the simplified method, compared with direct operation, the method simplifies the operation process, only the operation of the first column is carried out, the speed is improved by 7 times on the whole, the 0 part in the generator matrix G is directly removed in the later operation, and the generator matrix G is a sparse matrix, so that the calculation unit is saved to a great extent.

2. The hardware implementation method of the FPGA-based polar code encoder according to claim 1, wherein the step (2) constructs a ROM for an 8-bit encoding look-up table, comprising:

all inputs of an 8-bit encoder are subjected to encoding calculation through MATLAB to obtain encoding results, wherein the inputs are 256 in total, then an 8-bit read only memory ROM with the depth of 256 is created in QUARTUS II, information bits are used as the address of the ROM, the encoding results are used as the storage information of the corresponding address in the ROM, in order to improve the parallelism, 2 double-port ROMs are established in the system, 8-bit polarization code encoding of 4 threads is carried out at the same time, and under the same parallelism, the calculation period is saved by 8 times through a table lookup method.