CN108304658A - A kind of polarization code encoder hardware implementation method based on FPGA - Google Patents

A kind of polarization code encoder hardware implementation method based on FPGA Download PDF

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CN108304658A
CN108304658A CN201810107445.8A CN201810107445A CN108304658A CN 108304658 A CN108304658 A CN 108304658A CN 201810107445 A CN201810107445 A CN 201810107445A CN 108304658 A CN108304658 A CN 108304658A
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matrix
coding
rom
polarization code
hardware implementation
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CN108304658B (en
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王秀敏
吴卓铤
王怡
李君�
洪波
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China Jiliang University
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China Jiliang University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Evolutionary Computation (AREA)
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  • General Engineering & Computer Science (AREA)
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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The polarization code encoder hardware implementation method based on FPGA that the invention discloses a kind of, this method mainly for relevance between the front stage of polarization code coding structure it is relatively strong caused by parallel organization difficult design the problems such as, on the basis of summing up polarization code code generator matrix rule, a kind of method of simplified operation is designed.This method need to only carry out the operation of generator matrix first row, then can obtain entire coding result according to rule.This method also introduces ROM look-up tables as initial computation unit, to substantially increase the arithmetic speed of encoder entirety on the basis of solving Parallel Problem.

Description

A kind of polarization code encoder hardware implementation method based on FPGA
Technical field
The invention belongs to field of channel coding more particularly to a kind of polarization code encoder hardware realization sides based on FPGA Method.
Background technology
Polarization code coding techniques was proposed that the coding techniques is in binary system discrete memoryless channel(DMC) by E.Arikan in 2007 Under the conditions of, it will appear channel-polarization phenomenon when code length tends to infinity, i.e., local channel capacity levels off to 1 and part levels off to 0.Polarization code can reach the aromatic limit under these conditions, and the complexity of its encryption algorithm is relatively low, this makes polarization code Coding becomes a great breakthrough in channel coding history.Polarization code causes wireless as a kind of emerging coding techniques Communication circle is widely paid close attention to.As one of the hot research topic being widely noticed in coding field.
Due to having higher relevance between the front stage of polarization code coding structure, this makes polarization code in Parallel Design On there is many difficulties.The encoder design of polarization code mainly uses for reference the processing thought progress FPGA hardware of fft algorithm at present Design, but this method still belongs to serial arithmetic.The present invention designs one by using the regularity of distribution of G matrix in conjunction with look-up table The polarization code coder of kind parallel organization.
Invention content
Present invention polarization code encoding method is encoded mainly for polarization code in problem present on Parallel Design, is being summed up On the basis of polarization code code generator matrix structure law, a kind of polarization code coding based on FPGA is designed using look-up table Device, to substantially increase the degree of parallelism of polarization code coding.
The technical solution used in the present invention is as follows：
(1) structure law of generator matrix is found out.The structure of polarization code coder is formed based on a cell matrix, The cell matrix is：
When code length is 2nWhen, the relationship of generator matrix and cell matrix is：
WhereinIt is one 2n×2nMatrix.
Can be seen that according to the above characteristic when carrying out operation with the generator matrix, must have it is many compute repeatedly, The part repeated can only be calculated part that is primary and replacing other to repeat with the result by we.Assuming that the generation square of code length 64 Battle array G such as formulas are (3) shown：
Wherein, A is：
If the information bit that length is 64 is C={ c0,c1,c2,c3,c4,c5,c6,c7, wherein ciIt is 8.Then we It can simplify with the following methods, enable A1={ a0,a1,a2,a3,a4,a5,a6,a7, wherein ai=ci×A.If the letter after coding Breath sequence is S={ s0,s1,s2,s3,s4,s5,s6,s7, then have
s0=a0^a1^a2^a3^a4^a5^a6^a7 (5)
s1=a1^a3^a5^a7 (6)
s2=a2^a3^a6^a7 (7)
s3=a3^a7 (8)
s4=a4^a5^a6^a7 (9)
s5=a5^a7 (10)
s6=a6^a7 (11)
s7=a7 (12)
Formula (5)~(12) are the basic operation formula of the algorithm, and in contrast to direct operation, this method simplifies operation Journey only carries out the operation of first row, improves 7 times of speed on the whole, and 0 element in G matrix is directly rejected in the operation in later stage, And the G matrix is sparse matrix, this has just largely saved computing unit.
(2) encoder design based on FPGA.The encoder system structure is as shown in Figure 1.The system includes information segmentation Module, coding module of tabling look-up, 8 coding result memories, coding scratch-pad storage, coding structure arithmetic unit, output mould Block.Based on above simplification algorithm, the hardware design of encoder is carried out.In order to further simplify operation, encoder is improved Throughput, which is tabled look-up using eight coding results of look-up table pair.Pass through MATLAB pairs of 8 encoder first All inputs (in total 256 kinds) carry out coding calculating and obtain coding result, and it is 256 that depth is then created in QUARTUS II 8 read only memory ROMs deposited its coding result as corresponding address in ROM using information bit as the address of ROM Store up information.In order to improve degree of parallelism, 2 twoport ROM are established in this system, are carried out at the same time the 8 bit polarization codes coding of 4 threads. Under same degree of parallelism, look-up table has saved 8 times of calculating cycle.
Description of the drawings
Fig. 1 system construction drawings
256 encoder system program charts of Fig. 2
Specific implementation mode
The FPGA that code length is 1024 is used to polarize code coder as example below, and it is detailed to combine Fig. 2 to carry out the present invention Description, specific implementation mode following steps：
Step 1：Enabled encoder, setting cycle flag bit n=1, encoder starts to receive 32 information bits, by 32 Position information bit is divided into four threads and is respectively transmitted to carry out table lookup operation in ROM, and ROM exports 48 coded sequences respectively.And Result is stored in coding scratch-pad storage.
Step 2：Coding structure arithmetic unit reads data from scratch-pad storage, and according to institute in technical solution (1) It states algorithm and calculates 32 coded sequences.And it is stored in 32 coded stacks.Further according to encoder current encoder code length It chooses whether to carry out next group of coding.
Step 3：Cycle flag bit adds 1, and receives next group of 32 information bits, repeats the operation of step 1 step 2.
Step 4：As n=9, system stops receiving information bit, and coding structure arithmetic unit is called to read 8 32 Coded sequence calculates 256 codings according to algorithm described in technical solution (1).And start to encode next 256 information sequences Row.

Claims (3)

1. a kind of polarization code encoder hardware implementation method based on FPGA, it is characterised in that this approach includes the following steps：
(1) structure law of generator matrix, the simplification method that design G matrix calculates are found out；
(2) structure encodes the ROM to table look-up for 8；
2. hardware implementation method according to claim 1, it is characterised in that the step (1) finds out the structure of generator matrix Rule, the simplification method that design G matrix calculates, specifically：
If the information bit that length is 64 is C={ c0,c1,c2,c3,c4,c5,c6,c7, wherein ciIt is 8.Then we can be with Simplify with the following methods, enables A1={ a0,a1,a2,a3,a4,a5,a6,a7, wherein ai=ci×A.If the information sequence after coding It is classified as S={ s0,s1,s2,s3,s4,s5,s6,s7, then have
s0=a0^a1^a2^a3^a4^a5^a6^a7 ⑴
s1=a1^a3^a5^a7 ⑵
s2=a2^a3^a6^a7 ⑶
s3=a3^a7 ⑷
s4=a4^a5^a6^a7 ⑸
s5=a5^a7 ⑹
s6=a6^a7 ⑺
s7=a7 ⑻
Formula (1)~(8) be the simplification method basic operation formula, in contrast to direct operation, this method simplifies calculating process, only The operation for carrying out first row, improves 7 times of speed, 0 part in G matrix, and the G are directly rejected in the operation in later stage on the whole Matrix is sparse matrix, this has just largely saved computing unit.
3. hardware implementation method according to claim 1, it is characterised in that step (2) structure is looked into for 8 codings The ROM of table, specifically：
Coding calculating is carried out by all inputs (in total 256 kinds) of MATLAB pairs of 8 encoders and obtains coding result, then 8 read only memory ROMs that depth is 256 are created in QUARTUS II to be encoded using information bit as the address of ROM As a result the storage information as corresponding address in ROM.In order to improve degree of parallelism, 2 twoport ROM are established in this system, simultaneously Carry out the 8 bit polarization codes coding of 4 threads.Under same degree of parallelism, look-up table has saved 8 times of calculating cycle.
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