CN108289158A - Modular video processing method based on FPGA partial reconfigurations - Google Patents
Modular video processing method based on FPGA partial reconfigurations Download PDFInfo
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- CN108289158A CN108289158A CN201711293591.6A CN201711293591A CN108289158A CN 108289158 A CN108289158 A CN 108289158A CN 201711293591 A CN201711293591 A CN 201711293591A CN 108289158 A CN108289158 A CN 108289158A
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- video
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- video processing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2628—Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0135—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/646—Circuits for processing colour signals for image enhancement, e.g. vertical detail restoration, cross-colour elimination, contour correction, chrominance trapping filters
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Image Processing (AREA)
Abstract
The invention belongs to embedded computer technical field of video processing, more particularly to a kind of modular video processing method based on FPGA partial reconfigurations.It safeguards by establishing and commonly use that video processnig algorithms library is converted and commonly used to video format, dynamic recognition FPGA dynamic areas realize the online switching of various video Processing Algorithm.Solve the problems, such as that Embedded Application middle and small scale FPGA can not realize Various Complex video processnig algorithms simultaneously.
Description
Technical field
The invention belongs to embedded computer technical field of video processing, and FPGA local dynamic stations are based on more particularly to one kind
The method for processing video frequency of reconfiguration technique.
Background technology
For Embedded Application, it is generally desirable that can with volume small as possible and energy consumption few as possible come complete as possible mostly and
Complicated function as possible.Currently, embedded video processing has been widely used for industry-by-industry, simple transmission of video and display
It can no longer meet the demand of complicated applications.In general, needing to do noise reduction, image scaling, picture quality enhancement, target for original video
The processing such as identification, target following.However, being limited to small product size and power consumption, embedded video processing apparatus can only often select
Property the more single processing method of realization.
FPGA partial reconfigurations are emerging technology schemes in recent years, and logic can be dynamically changed using technique
Module is without interfering other function logics to run.It, can be in the FPGA of limited scale by technique applied to video processing
It realizes more method for processing video frequency, while reducing power consumption, lifting scheme flexibility.
Invention content
Purpose of the present invention is to overcome the shortcomings of above-mentioned prior art, a module based on FPGA partial reconfigurations is proposed
Change method for processing video frequency.
The technical scheme is that two function modules grounds of maintenance management.One for maintenance management video pre-filtering and
Show analytic function, another is used for maintenance management video processnig algorithms.According to original video lattice after the determination of product function demand
Formula, method for processing video frequency show output format to choose corresponding video pre-filtering module, display analysis from function modules ground
Module and video processnig algorithms.FPGA is divided into dynamic area and static zones when specific design is realized, video is done in static zones
Pretreatment, display control, index calculates and dynamic configuration control, and video processing is done in dynamic area.The video pre-filtering of static zones
It is calculated including video-signal filter, format conversion, color space conversion, display output and index, the video processing of dynamic area needs
Video processnig algorithms synthesis is embodied as FPGA local configuration files, configuration control logic selects certain according to method for processing video frequency
A local configuration file load, to dynamic translation method for processing video frequency.
Technical solution：
Modular video processing method based on FPGA partial reconfigurations, realization are as follows：
1 first step, the foundation and maintenance of function modules ground.By common video pre-filtering conversion, display control, index meter
It calculates, dynamic configuration controls, video processnig algorithms are stored with RTL code file or net meter file.Before product design and development, work(
Energy module library just should tentatively establish, and with the exploitation or modification of new video Processing Algorithm and conversion process method, library is also answered
This is updated therewith.
Second step, fpga logic design.According to product function demand, corresponding function mould is selected from function modules ground
Block.FPGA is divided into static zones and dynamic area.Video pre-filtering, display control, index are calculated and dynamic configuration control is patrolled
It collects and does comprehensive realization in static zones.Selected video processnig algorithms are realized in dynamic area.
Third walks, configuration file load.The global configuration file box dynamic area that the static zones FPGA synthesis is realized is integrated real
Three existing local dynamic station configuration files merge in the configuration FLASH of write-in FPGA.
4th step, video processing procedure.After original video enters FPGA, video-signal filter is carried out first, and the processing is logical
It crosses and the synchronizing signals such as VS, HS, DE in vision signal is filtered, filter out burr, form the VESA sequential vision signals of stability criterion
Export rear class processing.Video format and color are done in the requirement according to original video format and video processnig algorithms to video format later
Color space is converted.For the video input of format match to video processing module, video processing module, which can do video, meets function need
The transformation asked.Changed according to application scenarios, the local dynamic station configuration control modules of static zones can be controlled by dynamic area again
Load, to realize the switching of video processnig algorithms.
5th step, processing video display analysis.Treated vision signal is shown after doing conversion process according to display demand
Show output.Meanwhile index computing module can calculate video processing procedure and take and handle the fingers such as rear video signal-to-noise ratio in real time
Mark parameter.
Three kinds of different video Processing Algorithms or three kinds of algorithm combinations, each method for processing video frequency quilt can be achieved at the same time in the present invention
Synthesis is embodied as an individual dynamic configuration file.
The video pre-filtering conversion includes video-signal filter, interlaced video interpolation, progressive video extraction, 444 formats
Down-sampling, 422 format interpolation, 420 format interpolation, rgb color space turn YUV color spaces, YUV color spaces turn rgb color
Space etc..
Display control includes that standard VESA sequential generates, video data reads filling.
Index calculating includes signal-to-noise ratio computation, processing delay calculating etc..
Video processnig algorithms include noise reduction, image scaling, picture quality enhancement, target identification, target following etc.
Description of the drawings
Fig. 1 is process chart of the present invention
Fig. 2 is FPGA functional structure charts of the present invention
Specific implementation mode
The present invention will be further described below in conjunction with the accompanying drawings：
By taking certain video is superimposed defogging system as an example, which needs to complete 1080I SDI original videos doing character graphics
Superposition and the processing of two different defogging videos, output 1080P DVI videos are shown.The FPGA scales of scheme use are limited to,
Character graphics is superimposed and two kinds of video defogging Processing Algorithms can not integrate realization simultaneously, and three kinds of method for processing video frequency are in different application
Lower selection one of which of scene.It is as follows using this method.
The first step, according to system requirements, original video format is mismatched with video processing format, is needed by interlaced video
Interpolation, 422 interpolation, color space need to be converted to RGB from YUV.Video-processed format and display output format demand
Match, need not convert.The application only needs display to export, and is calculated without index.Vision signal is selected from function modules ground
Filter module, interlaced video interpolating module, 422 format interpolating modules, YUV color spaces turn rgb color space module, standard
VESA sequential generation module, video data read filling module and dynamic restructuring control module.By these modules according to system need
It asks and sets corresponding parameter.
Second step, FPGA divide static zones and dynamic area.Video pre-filtering, display analysis and the dynamic of parameter will be set
Reconstruct configuration correlation module is embodied as global configuration file in static zones synthesis, by character graphics superposition and two different defoggings
In dynamic area, synthesis is embodied as three local dynamic station configuration files to algorithm respectively.
Third walks, by global configuration file and three local configuration Piece file mergence write-in configuration FLASH.
4th step first passes around video-signal filter after 1080I SDI original videos enter FPGA, filters out burr, is formed
The VESA sequential vision signals output rear class processing of stability criterion.Filtered video is that 444 formats regard by 422 format interpolation
Frequently, then pass through color space conversion and rgb color space is converted to by YUV color spaces.Meet video processnig algorithms after conversion
The RGB444 format videos of demand are sent into dynamic area and do video processing.Dynamic area can be needed according to application scenarios from configuration
Dynamic load local configuration file in FLASH is realized and is switched in character graphics superposition and two kinds of video defogging processing methods.
5th step generates 1080P VESA sequential, filling processing rear video data, display output.
Claims (6)
1. the modular video processing method based on FPGA partial reconfigurations, it is characterised in that：Include the following steps realization；
The first step, the foundation and maintenance of function modules ground；Common video pre-filtering conversion, display control, index are calculated, is dynamic
State configuration control, video processnig algorithms are stored with RTL code file or net meter file；
Second step, fpga logic design；According to product function demand, corresponding function module is selected from function modules ground；It will
FPGA is divided into static zones and dynamic area；Video pre-filtering, display control, index are calculated and dynamic configuration control logic is quiet
Do comprehensive realization in state area；Selected video processnig algorithms are realized in dynamic area；
Third walks, configuration file load；The global configuration file box dynamic area synthesis that the static zones FPGA synthesis is realized is realized
Three local dynamic station configuration files merge in the configuration FLASH of write-in FPGA；
4th step, video processing procedure；After original video enters FPGA, carry out video-signal filter first, the processing by pair
VS, HS, DE synchronizing signal filter in vision signal, filter out burr, after forming the VESA sequential vision signals output of stability criterion
Grade processing；Video format and color space are done in the requirement according to original video format and video processnig algorithms to video format later
Conversion；The video input of format match to video processing module, video processing module can do video the change for meeting functional requirement
It changes；Being changed according to application scenarios, the local dynamic station configuration control module that can control static zones reloads dynamic area, with
Realize the switching of video processnig algorithms；
5th step, processing video display analysis；Treated vision signal done according to display demand show after conversion process it is defeated
Go out；Meanwhile index computing module can calculate video processing procedure and take and handle rear video signal-to-noise ratio index parameter in real time.
2. the modular video processing method according to claim 1 based on FPGA partial reconfigurations, it is characterised in that：
Video pre-filtering conversion include video-signal filter, interlaced video interpolation, progressive video extraction, 444 format down-samplings,
422 format interpolation, 420 format interpolation, rgb color space turn YUV color spaces, YUV color spaces turn rgb color space.
3. the modular video processing method according to claim 1 based on FPGA partial reconfigurations, it is characterised in that：
The display control includes that standard VESA sequential generates, video data reads filling.
4. the modular video processing method according to claim 1 based on FPGA partial reconfigurations, it is characterised in that：
The index calculating includes signal-to-noise ratio computation, processing delay calculating.
5. the modular video processing method according to claim 1 based on FPGA partial reconfigurations, it is characterised in that：
The video processnig algorithms include noise reduction, image scaling, picture quality enhancement, target identification, target following.
6. the modular video processing method according to claim 1 based on FPGA partial reconfigurations, it is characterised in that：
Further include that three kinds of different video Processing Algorithms can be achieved at the same time or three kinds of algorithm combinations, each method for processing video frequency are integrated into realization
For an individual dynamic configuration file.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070046820A1 (en) * | 2005-08-26 | 2007-03-01 | John Mead | Video image processing with programmable scripting and remote diagnosis |
| CN101833368A (en) * | 2010-04-13 | 2010-09-15 | 杭州电子科技大学 | Method for managing energy of local dynamic reconfigurable system by coordinatively processing software and hardware |
| CN102819818A (en) * | 2012-08-14 | 2012-12-12 | 公安部第三研究所 | Method for realizing image processing based on dynamic reconfigurable technology of field programmable gate array (FPGA) chip |
-
2017
- 2017-12-07 CN CN201711293591.6A patent/CN108289158A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070046820A1 (en) * | 2005-08-26 | 2007-03-01 | John Mead | Video image processing with programmable scripting and remote diagnosis |
| CN101833368A (en) * | 2010-04-13 | 2010-09-15 | 杭州电子科技大学 | Method for managing energy of local dynamic reconfigurable system by coordinatively processing software and hardware |
| CN102819818A (en) * | 2012-08-14 | 2012-12-12 | 公安部第三研究所 | Method for realizing image processing based on dynamic reconfigurable technology of field programmable gate array (FPGA) chip |
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