CN108269802B - Carbon nano tube beam field effect transistor array and manufacturing method thereof - Google Patents
Carbon nano tube beam field effect transistor array and manufacturing method thereof Download PDFInfo
- Publication number
- CN108269802B CN108269802B CN201710004518.6A CN201710004518A CN108269802B CN 108269802 B CN108269802 B CN 108269802B CN 201710004518 A CN201710004518 A CN 201710004518A CN 108269802 B CN108269802 B CN 108269802B
- Authority
- CN
- China
- Prior art keywords
- carbon nanotube
- material layer
- array
- bundle
- nanotube bundle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 202
- 239000002041 carbon nanotube Substances 0.000 title claims abstract description 175
- 229910021393 carbon nanotube Inorganic materials 0.000 title claims abstract description 175
- 230000005669 field effect Effects 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000007772 electrode material Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims description 91
- 239000003054 catalyst Substances 0.000 claims description 29
- 229910052799 carbon Inorganic materials 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 20
- 150000002500 ions Chemical class 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 229910052735 hafnium Inorganic materials 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 229910052741 iridium Inorganic materials 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 229910052707 ruthenium Inorganic materials 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000005535 acoustic phonon Effects 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- -1 e.g. Chemical compound 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000006163 transport media Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
Abstract
The invention provides a carbon nanotube bundle field effect transistor array and a manufacturing method thereof, wherein the carbon nanotube bundle field effect transistor array comprises: the carbon nanotube array comprises a source electrode material layer, a drain electrode material layer and a carbon nanotube bundle array connected between the source electrode material layer and the drain electrode material layer; the carbon nanotube bundle array comprises a plurality of carbon nanotube bundle units which are separately arranged, wherein the axial first ends of the carbon nanotube bundle units are connected with the source electrode material layer, and the axial second ends of the carbon nanotube bundle units are connected with the drain electrode material layer; the carbon nanotube bundle unit is surrounded by a grid structure. The carbon nanotube bundle field effect transistor array can bear higher operating voltage and operating current and can be applied to high-power devices. And the invention adopts the surrounding gate structure, which can improve the control ability of the gate to the channel. The manufacturing method of the carbon nano tube beam field effect transistor array has the characteristic of simple process steps, and is beneficial to reducing the production cost.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and relates to a carbon nano tube beam field effect transistor array and a manufacturing method thereof.
Background
For carrier transport media, vacuum is inherently preferred over solid because it allows ballistic transport, whereas in semiconductors carriers are subject to optical and acoustic phonon scattering. The electron velocity in vacuum is theoretically 3X 1010cm/s, but in semiconductors the electron velocity is only about 5X 107cm/s. Some scientists believe that in vacuum transistors, it appears that only electrons can flow between the electrodes, while holes cannot. Unless we learn to handle positrons, it would not be possible to do any complementary circuits, such as CMOS. Without the complementary circuit, the power would be too high, most likely limiting the vacuum transistor to market segments. It is hard to imagine that any large digital circuit will use vacuum transistors.
Currently, there are four main types of Vacuum transistors (Jin-Woo Han, Jae Sub Oh and M.Meyyappan, Vacuum Nanoelectronics: Back to the Future: (a) vertical field emission type, (b) planar lateral field emission type, (c) MOSFET type, (d) insulated gate air channel transistor.
In recent years, it has been reported that carbon nanotube field effect crystals are disclosed in ideal wrap gate geometriesThe self-aligned gate size of the tube (CNTFET) can be scaled down to 20 nm (IBM created the first 9nm carbon nanotube transistor published by Gareth Halfacree at 1/30/2012). The uniformity of the gate surrounding the carbon nanotube channel has been demonstrated and this process does not damage the carbon nanotubes. Furthermore, with a suitable gate dielectric layer, an N-type transistor or a P-type transistor can be realized, wherein HfO is used2The gate dielectric layer can be used for realizing N-type transistor and Al2O3P-type transistors (Aaron D. Franklin, Carbon Nanotube complete Wrap-Gate transistors, Nano Lett.,2013,13(6), pp 2490-. These findings not only provide a promising platform for further studies of wrap gate carbon nanotube devices, but also suggest that large-scale digital switches employing carbon nanotubes possess realistic technological potential.
However, there remains a need to develop the potential and possibilities of CNTFETs that can be used to fabricate high power devices with high operating voltages and high drive currents.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a carbon nanotube bundle field effect transistor array and a manufacturing method thereof, which are used for solving the problem that the carbon nanotube bundle field effect transistor in the prior art cannot be applied to a high-power device.
To achieve the above and other related objects, the present invention provides a carbon nanotube-bundle field effect transistor array, comprising:
a source material layer;
a drain material layer formed over the source material layer;
the carbon nanotube bundle array is connected between the source electrode material layer and the drain electrode material layer; the carbon nanotube bundle array comprises a plurality of carbon nanotube bundle units which are separately arranged, wherein the axial first ends of the carbon nanotube bundle units are connected with the source electrode material layer, and the axial second ends of the carbon nanotube bundle units are connected with the drain electrode material layer;
the grid structure is formed between the carbon nanotube bundle units in the carbon nanotube bundle array, the grid structure is isolated from the source electrode material layer through a first insulating layer, and the grid structure is isolated from the drain electrode material layer through a second insulating layer; the grid structure comprises a grid dielectric layer and a grid material layer, the grid dielectric layer surrounds the outer side face of the carbon nanotube bundle unit, and the grid material layer surrounds the outer side face of the grid material layer.
Optionally, the carbon nanotube beam field effect transistor array further includes a substrate and a third insulating layer formed on the substrate, and the source material layer is formed on the third insulating layer.
Optionally, an angle between the axial direction of the carbon nanotube bundle unit and the plane of the source material layer is 80-100 °.
Optionally, the carbon nanotube-bundle unit has a height greater than 100 μm.
Optionally, the gate dielectric layer is a high-K dielectric, and the gate material layer includes a metal material.
Optionally, the source material layer and the drain material layer both include a metal material.
The invention also provides a manufacturing method of the carbon nano tube beam field effect transistor array, which comprises the following steps:
s1: providing a substrate, and sequentially forming a third insulating layer, a source material layer and a first insulating layer on the substrate;
s2: forming an array of vias in the first insulating layer; the through hole array comprises a plurality of through holes which are separately arranged, and the through holes expose the upper surface of the source electrode material layer;
s3: forming an array of carbon nanotube bundles based on the array of through holes; the carbon nanotube bundle array comprises a plurality of carbon nanotube bundle units corresponding to the positions of the through holes, wherein the first axial ends of the carbon nanotube bundle units are connected with the source electrode material layer;
s4: forming a grid dielectric layer covering the outer side surface of the carbon nanotube bundle unit;
s5: forming a grid electrode material layer covering the outer side surface of the grid electrode dielectric layer;
s6: and sequentially forming a second insulating layer and a drain electrode material layer, wherein the axial second end of the carbon nanotube bundle unit is connected with the drain electrode material layer, and the grid electrode dielectric layer and the grid electrode material layer are isolated from the drain electrode material layer through the second insulating layer.
Optionally, in step S3, the carbon nanotube bundle array is formed by a chemical vapor deposition method under a protective atmosphere using a catalyst and a carbon source.
Optionally, the protective atmosphere comprises N2、H2And Ar, the catalyst comprises one or more of Fe, Ni and Co, and the growth temperature range of the carbon nanotube bundle array is 500-740 ℃.
Optionally, the catalyst is first formed on the upper surface of the source material layer based on the array of through holes, and then the array of carbon nanotube bundles is grown based on the catalyst.
Optionally, a solution containing catalyst ions is applied to the surface of the source material layer and annealed to increase the bonding strength of the catalyst ions to the source material layer.
Optionally, the annealing temperature range is 700-900 ℃, and the annealing time is 30-90 min.
Optionally, the method further comprises the step of removing the redundant catalyst ions on the surface of the second insulating layer.
Optionally, removing the excessive catalyst ions on the surface of the second insulating layer by wet etching.
Optionally, an angle between the axial direction of the carbon nanotube bundle unit and the plane of the source material layer is 80-100 °.
Optionally, the carbon nanotube-bundle unit has a height greater than 100 μm.
As described above, the carbon nanotube-bundle field effect transistor array and the method for manufacturing the same according to the present invention have the following advantageous effects: the carbon nanotube bundle field effect transistor array adopts the carbon nanotube bundle as a channel material, wherein only the outer carbon nanotube of the carbon nanotube bundle unit is surrounded by the grid dielectric layer, and the inner carbon nanotube is not surrounded by the grid dielectric layer, but the carbon nanotube in the carbon nanotube bundle unit still can play an effective role due to the interaction among the carbon nanotubes in the carbon nanotube bundle unit. The carbon nanotube bundle field effect transistor array can bear higher operating voltage and operating current and can be applied to high-power devices. And the invention adopts the surrounding gate structure, which can improve the control ability of the gate to the channel. The manufacturing method of the carbon nano tube beam field effect transistor array has the characteristic of simple process steps, and is beneficial to reducing the production cost.
Drawings
Fig. 1 is a schematic structural diagram of a carbon nanotube bundle field effect transistor array according to the present invention.
Fig. 2 is a schematic view illustrating a third insulating layer, a source material layer and a first insulating layer sequentially formed on the substrate according to the method for manufacturing a carbon nanotube beam field effect transistor array of the present invention.
Fig. 3 is a schematic diagram illustrating a method for fabricating a carbon nanotube bundle field effect transistor array according to the present invention, in which a via array is formed in the first insulating layer.
Fig. 4 is a schematic diagram illustrating the formation of the catalyst on the upper surface of the source material layer based on the via array in the method for manufacturing a carbon nanotube bundle field effect transistor array according to the present invention.
Fig. 5 is a schematic diagram of the method for manufacturing the carbon nanotube bundle field effect transistor array according to the present invention, which is based on the catalyst growth of the carbon nanotube bundle array.
Fig. 6 is a schematic diagram illustrating a method for manufacturing a carbon nanotube bundle field effect transistor array according to the present invention, wherein a gate dielectric layer is formed to cover an outer side surface of the carbon nanotube bundle unit.
Fig. 7 is a schematic diagram illustrating a gate material layer covering the outer side of the gate dielectric layer formed by the method for manufacturing a carbon nanotube beam field effect transistor array according to the present invention.
Fig. 8 is a schematic diagram illustrating the method for manufacturing a carbon nanotube bundle field effect transistor array according to the present invention, in which a portion of the gate dielectric layer and the gate material layer is removed to expose the upper portion of the carbon nanotube bundle array.
FIG. 9 is a schematic view of a second insulating layer and a drain material layer formed by the method of fabricating a carbon nanotube beam field effect transistor array according to the present invention.
Description of the element reference numerals
101 substrate
102 third insulating layer
103 source material layer
104 first insulating layer
105 carbon nano-tube bundle unit
106 gate dielectric layer
107 gate material layer
108 second insulating layer
109 layer of drain material
110 through hole
111 catalyst
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The present invention provides a carbon nanotube bundle field effect transistor array, please refer to fig. 1, which shows a schematic structural diagram of the carbon nanotube bundle field effect transistor array, including:
a source material layer 103;
a drain material layer 109 formed over the source material layer 103;
an array of carbon nanotube bundles connected between the source material layer 103 and the drain material layer 109; the carbon nanotube bundle array comprises a plurality of carbon nanotube bundle units 105 which are separately arranged, wherein a first axial end of each carbon nanotube bundle unit 105 is connected with the source material layer 103, and a second axial end of each carbon nanotube bundle unit 105 is connected with the drain material layer 109;
a gate structure formed between each carbon nanotube bundle unit 105 in the carbon nanotube bundle array, and the gate structure is isolated from the source material layer 103 by a first insulating layer 104, and the gate structure is isolated from the drain material layer 109 by a second insulating layer 108; the gate structure comprises a gate dielectric layer 106 and a gate material layer 107, wherein the gate dielectric layer 106 surrounds the outer side surface of the carbon nanotube bundle unit 105, and the gate material layer 107 surrounds the outer side surface of the gate material layer 107.
In this embodiment, the carbon nanotube beam field effect transistor array further includes a substrate 101 and a third insulating layer 102 formed on the substrate 101, and the source material layer 103 is formed on the third insulating layer 102.
Specifically, the base 101 includes, but is not limited to, conventional semiconductor substrate materials such as Si, Ge, and the like. The third insulating layer 102 may be made of silicon oxide or other insulating materials, and is used for isolating the source material layer 103 from the substrate 101.
Specifically, each carbon nanotube bundle unit 105 is used as a channel material of a field effect transistor, and two axial ends of the carbon nanotube bundle unit are respectively connected to the source material layer 103 and the drain material layer 109. The source material layer 103 serves as an N + type source of the carbon nanotube beam field effect transistor, and the drain material layer 109 serves as an N + type drain of the carbon nanotube beam field effect transistor.
In this embodiment, the height of the carbon nanotube-bundle unit 105 is greater than 100 μm. The angle between the axial direction of the carbon nanotube bundle unit 105 and the plane of the source material layer 103 is 80-100 degrees, and preferably 90 degrees. In other words, the carbon nanotube-bundle unit 105 has an axial direction perpendicular to, or substantially perpendicular to, the plane of the source material layer 103.
Specifically, the carbon nanotube bundle unit 105 is composed of a plurality of carbon nanotubes, wherein only the carbon nanotubes located at the periphery of the carbon nanotube bundle are partially or completely surrounded by the gate dielectric layer 106, while the carbon nanotubes located inside the carbon nanotube bundle are not surrounded by the gate dielectric layer 106, but due to the interaction among the carbon nanotubes in the carbon nanotube bundle unit 105, the carbon nanotubes located inside the carbon nanotube bundle unit 105 can still exert an effective effect. Compared with a single carbon nano tube as a channel, the carbon nano tube bundle containing a plurality of carbon nano tubes is used as a channel material, so that the carbon nano tube bundle field effect transistor array can bear higher operating voltage and operating current, and can be applied to high-power devices.
In the invention, the gate dielectric layer 106 surrounds the outer side surface of the carbon nanotube bundle unit 105, and the gate material layer 107 surrounds the outer side surface of the gate material layer 107, so that the gate structure forms a ring gate structure, and the control capability of the gate on the carbon nanotube bundle channel can be improved.
As an example, in the gate structure, the gate dielectric layer 106 is a high-K dielectric (higher than the dielectric constant of silicon dioxide by 3.9), such as hafnium-based oxide (HFO)2HfSiO, HfSiON, HfTaO, HfTiO, etc., or other dielectric materials. The gate material layer 107 is a metal gate, which includes a metal material, such as any one of Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo, or any one of their alloys.
As an example, the source material layer 103 and the drain material layer 109 both include a metal material, such as any one of Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo, or any alloy thereof.
The carbon nanotube bundle field effect transistor array adopts the carbon nanotube bundle as a channel material and adopts a ring grid structure, so that the carbon nanotube bundle field effect transistor array not only can be applied to high-power devices, but also has strong channel control capability.
Example two
The invention also provides a manufacturing method of the carbon nano tube beam field effect transistor array, which comprises the following steps:
referring to fig. 2, step S1 is executed: a substrate 101 is provided, and a third insulating layer 102, a source material layer 103 and a first insulating layer 104 are sequentially formed on the substrate 101.
Specifically, the base 101 includes, but is not limited to, conventional semiconductor substrate materials such as Si, Ge, and the like. The third insulating layer 102 is made of silicon oxide or other insulating materials, and is used for isolating the source material layer 103 from the substrate 101. The source material layer 103 includes a metal material, for example, any one of Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo, or any one of their alloys. The first insulating layer 104 is made of silicon oxide or other insulating materials.
The third insulating layer 102, the source material layer 103, and the first insulating layer 104 can be formed by physical vapor deposition or chemical vapor deposition.
Then, referring to fig. 3, step S2 is executed: forming an array of vias in the first insulating layer 104; the through hole array comprises a plurality of through holes 110 which are separately arranged, and the through holes 110 expose the upper surface of the source material layer 103.
Specifically, the through hole array is formed through the process steps of photoetching, etching and the like. The shape of the through-hole 110 includes, but is not limited to, a polygon, a circle, an ellipse, etc.
Referring to fig. 4-5, step S3 is executed: forming an array of carbon nanotube bundles based on the array of through holes; the carbon nanotube bundle array comprises a plurality of carbon nanotube bundle units 105 corresponding to the positions of the through holes 110, wherein the first axial ends of the carbon nanotube bundle units 105 are connected with the source material layer 103.
Specifically, each through hole 110 corresponds to one carbon nanotube-bundle unit 105, and each carbon nanotube-bundle unit 105 serves as a channel material of one field effect transistor.
In this embodiment, the carbon nanotube bundle array is formed by a chemical vapor deposition method using a catalyst and a carbon source in a protective atmosphere. The protective atmosphere comprises N2、H2And Ar, the carbon source comprises carbon-containing gas such as but not limited to methane, acetylene and the like, the catalyst comprises one or more of Fe, Ni and Co, and the growth temperature range of the carbon nanotube bundle array is 500-740 ℃.
Specifically, as shown in fig. 4, the catalyst 111 is first formed on the upper surface of the source material layer 103 based on the via array. As an example, a solution containing catalyst ions is applied to the surface of the source material layer 103 to form the catalyst 111. In this embodiment, an annealing step is further included to increase the bonding strength of the catalyst ions to the source material layer 103. The annealing temperature range is 700-900 ℃, and the annealing time is 30-90 min.
Further, after the annealing, a step of removing the excess catalyst ions on the surface of the second insulating layer 104 is also included. As an example, the excess catalyst ions on the surface of the second insulating layer 104 are removed by wet etching.
The array of carbon nanotube bundles is then grown based on the catalyst 111, as shown in fig. 5. In this embodiment, the angle between the axial direction of the carbon nanotube bundle unit 105 and the plane of the source material layer 103 is 80 ° to 100 °, and preferably 90 °. In other words, the carbon nanotube-bundle unit 105 has an axial direction perpendicular to, or substantially perpendicular to, the plane of the source material layer 103.
As an example, the treated substrate is placed in a reaction furnace, heated to 500 ℃ to 740 ℃ under a protective gas environment, and then carbon source gas is introduced and reacted for about 5 to 30 minutes, so as to grow the carbon nanotube bundle array, wherein the height of the carbon nanotube bundle array is more than 100 micrometers. The carbon nanotube bundle array is a pure carbon nanotube bundle array formed by a plurality of carbon nanotubes which are parallel to each other and grow vertical to the substrate. The carbon nanotube bundle has substantially the same area as the through hole. By controlling the growth conditions, the carbon nanotube bundle array does not contain amorphous carbon or residual impurities such as catalyst metal particles.
Referring to fig. 6, step S4 is executed: a gate dielectric layer 106 is formed to cover the outer side of the carbon nanotube bundle unit 105.
Specifically, the gate dielectric layer 106 is formed by a physical vapor deposition method or a chemical vapor deposition method. As an example, the gate dielectric layer 106 may be a high-K dielectric (higher than the dielectric constant of silicon dioxide, e.g., hafnium-based oxide, HfO)2HfSiO, HfSiON, HfTaO, HfTiO, etc., or other dielectric materials.
Referring to fig. 7, step S5 is executed: a gate material layer 107 is formed to cover the outer side of the gate dielectric layer 106.
Specifically, the gate material layer 107 is formed by a physical vapor deposition method or a chemical vapor deposition method. As an example, the gate material layer 107 is a metal gate, which includes a metal material, such as any one of Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo, or any one of their alloys.
Further, as shown in fig. 8, a portion of the gate material layer 107 and the gate dielectric layer 106 is removed to expose an upper portion of the carbon nanotube bundle array. The removing method may be a suitable method such as wet etching or plasma etching.
Finally, referring to fig. 9, step S6 is executed: and sequentially forming a second insulating layer 108 and a drain material layer 109, wherein the second axial end of the carbon nanotube bundle unit 105 is connected with the drain material layer 109, and the gate dielectric layer 106 and the gate material layer 107 are isolated from the drain material layer 109 by the second insulating layer 108.
Specifically, the second insulating layer 108 is made of silicon oxide or other insulating materials, and the drain material layer 109 includes a metal material, such as any one of Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, and Mo, or any one of their alloys.
Specifically, the top end of the carbon nanotube-bundle unit 105 is embedded in the drain material layer 109, so that the connection between the carbon nanotube-bundle unit 105 and the drain material layer 109 can be strengthened.
Thus, the carbon nanotube bundle field effect transistor array of the present invention was completed. The manufacturing method of the carbon nano tube beam field effect transistor array has the characteristic of simple process steps, and is beneficial to reducing the production cost.
In summary, the carbon nanotube bundle field effect transistor array of the present invention employs the carbon nanotube bundle as the channel material, wherein only the outer carbon nanotubes of the carbon nanotube bundle unit are surrounded by the gate dielectric layer, and the inner carbon nanotubes are not surrounded by the gate dielectric layer, but the carbon nanotubes in the carbon nanotube bundle unit still can exert their effective functions due to the interaction among the carbon nanotubes in the carbon nanotube bundle. The carbon nanotube bundle field effect transistor array can bear higher operating voltage and operating current and can be applied to high-power devices. And the invention adopts the surrounding gate structure, which can improve the control ability of the gate to the channel. The manufacturing method of the carbon nano tube beam field effect transistor array has the characteristic of simple process steps, and is beneficial to reducing the production cost. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (16)
1. A carbon nanotube bundle field effect transistor array, comprising:
a source material layer;
a drain material layer formed over the source material layer;
the carbon nanotube bundle array is connected between the source electrode material layer and the drain electrode material layer; the carbon nanotube bundle array comprises a plurality of carbon nanotube bundle units which are separately arranged, wherein the axial first ends of the carbon nanotube bundle units are connected with the source electrode material layer, and the axial second ends of the carbon nanotube bundle units are connected with the drain electrode material layer;
the grid structure is formed between the carbon nanotube bundle units in the carbon nanotube bundle array, the grid structure is isolated from the source electrode material layer through a first insulating layer, and the grid structure is isolated from the drain electrode material layer through a second insulating layer; the grid structure comprises a grid dielectric layer and a grid material layer, the grid dielectric layer surrounds the outer side face of the carbon nanotube bundle unit, and the grid material layer surrounds the outer side face of the grid dielectric layer;
the carbon nanotube bundle unit is composed of a plurality of carbon nanotubes, wherein only the carbon nanotubes positioned at the periphery of the carbon nanotube bundle are partially or completely surrounded by the gate dielectric layer, and the carbon nanotubes positioned in the carbon nanotube bundle are not surrounded by the gate dielectric layer.
2. The array of carbon nanotube-bundle field effect transistors of claim 1, wherein: the carbon nano tube beam field effect transistor array further comprises a substrate and a third insulating layer formed on the substrate, and the source material layer is formed on the third insulating layer.
3. The array of carbon nanotube-bundle field effect transistors of claim 1, wherein: the angle between the axial direction of the carbon nanotube bundle unit and the plane of the source electrode material layer is 80-100 degrees.
4. The array of carbon nanotube-bundle field effect transistors of claim 1, wherein: the height of the carbon nanotube bundle unit is more than 100 μm.
5. The array of carbon nanotube-bundle field effect transistors of claim 1, wherein: the grid dielectric layer adopts a high-K dielectric, and the grid material layer comprises a metal material.
6. The array of carbon nanotube-bundle field effect transistors of claim 1, wherein: the source material layer and the drain material layer both comprise a metal material.
7. A method for manufacturing a carbon nanotube beam field effect transistor array is characterized by comprising the following steps:
s1: providing a substrate, and sequentially forming a third insulating layer, a source material layer and a first insulating layer on the substrate;
s2: forming an array of vias in the first insulating layer; the through hole array comprises a plurality of through holes which are separately arranged, and the through holes expose the upper surface of the source electrode material layer;
s3: forming an array of carbon nanotube bundles based on the array of through holes; the carbon nanotube bundle array comprises a plurality of carbon nanotube bundle units corresponding to the positions of the through holes, wherein the first axial ends of the carbon nanotube bundle units are connected with the source electrode material layer;
s4: forming a grid dielectric layer covering the outer side surface of the carbon nanotube bundle unit;
s5: forming a grid electrode material layer covering the outer side surface of the grid electrode dielectric layer;
s6: sequentially forming a second insulating layer and a drain electrode material layer, wherein the axial second end of the carbon nanotube bundle unit is connected with the drain electrode material layer, and the grid electrode dielectric layer and the grid electrode material layer are isolated from the drain electrode material layer through the second insulating layer;
the carbon nanotube bundle unit is composed of a plurality of carbon nanotubes, wherein only the carbon nanotubes positioned at the periphery of the carbon nanotube bundle are partially or completely surrounded by the gate dielectric layer, and the carbon nanotubes positioned in the carbon nanotube bundle are not surrounded by the gate dielectric layer.
8. The method of manufacturing a carbon nanotube bundle field effect transistor array as claimed in claim 7, wherein: in step S3, the carbon nanotube bundle array is formed by chemical vapor deposition under a protective atmosphere using a catalyst and a carbon source.
9. The method of manufacturing a carbon nanotube-bundle field effect transistor array as set forth in claim 8, wherein: the protective atmosphere comprises N2、H2And Ar, the catalyst comprises one or more of Fe, Ni and Co, and the growth temperature range of the carbon nanotube bundle array is 500-740 ℃.
10. The method of manufacturing a carbon nanotube-bundle field effect transistor array as set forth in claim 8, wherein: firstly, forming the catalyst on the upper surface of the source electrode material layer based on the through hole array, and then growing the carbon nano tube bundle array based on the catalyst.
11. The method of manufacturing a carbon nanotube-bundle field effect transistor array as set forth in claim 10, wherein: applying a solution containing catalyst ions to the surface of the source material layer, and annealing to increase the bonding strength of the catalyst ions and the source material layer.
12. The method of manufacturing a carbon nanotube-bundle field effect transistor array as set forth in claim 11, wherein: the annealing temperature range is 700-900 ℃, and the annealing time is 30-90 min.
13. The method of manufacturing a carbon nanotube-bundle field effect transistor array as set forth in claim 11, wherein: the method also comprises a step of removing redundant catalyst ions on the surface of the second insulating layer.
14. The method of manufacturing a carbon nanotube bundle field effect transistor array as claimed in claim 13, wherein: and removing redundant catalyst ions on the surface of the second insulating layer by wet etching.
15. The method of manufacturing a carbon nanotube bundle field effect transistor array as claimed in claim 7, wherein: the angle between the axial direction of the carbon nanotube bundle unit and the plane of the source electrode material layer is 80-100 degrees.
16. The method of manufacturing a carbon nanotube bundle field effect transistor array as claimed in claim 7, wherein: the height of the carbon nanotube bundle unit is more than 100 μm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710004518.6A CN108269802B (en) | 2017-01-04 | 2017-01-04 | Carbon nano tube beam field effect transistor array and manufacturing method thereof |
| TW106122286A TWI657041B (en) | 2017-01-04 | 2017-07-03 | A nano tube field effect transistor array and the method for preparing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710004518.6A CN108269802B (en) | 2017-01-04 | 2017-01-04 | Carbon nano tube beam field effect transistor array and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108269802A CN108269802A (en) | 2018-07-10 |
| CN108269802B true CN108269802B (en) | 2020-11-06 |
Family
ID=62770874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710004518.6A Active CN108269802B (en) | 2017-01-04 | 2017-01-04 | Carbon nano tube beam field effect transistor array and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108269802B (en) |
| TW (1) | TWI657041B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102020109756A1 (en) | 2019-08-29 | 2021-03-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | TRANSISTORS WITH CHANNELS FORMED FROM LOW DIMENSIONAL MATERIALS AND METHOD OF FORMING THE SAME |
| US11417729B2 (en) | 2019-08-29 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistors with channels formed of low-dimensional materials and method forming same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1330412A (en) * | 2000-06-27 | 2002-01-09 | 三星电子株式会社 | Vertical nanometer size transistor using carbon monometer tube and manufacturing method thereof |
| CN1638066A (en) * | 2004-01-07 | 2005-07-13 | 国际商业机器公司 | Vertical carbon nanotube field effect transistor |
| CN101217128A (en) * | 2007-01-04 | 2008-07-09 | 奇梦达股份公司 | Method for making an integrated circuit having a via hole |
| US8168495B1 (en) * | 2006-12-29 | 2012-05-01 | Etamota Corporation | Carbon nanotube high frequency transistor technology |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7084507B2 (en) * | 2001-05-02 | 2006-08-01 | Fujitsu Limited | Integrated circuit device and method of producing the same |
| DE10250829B4 (en) * | 2002-10-31 | 2006-11-02 | Infineon Technologies Ag | Nonvolatile memory cell, memory cell array, and method of making a nonvolatile memory cell |
| TWI222742B (en) * | 2003-05-05 | 2004-10-21 | Ind Tech Res Inst | Fabrication and structure of carbon nanotube-gate transistor |
| US7598516B2 (en) * | 2005-01-07 | 2009-10-06 | International Business Machines Corporation | Self-aligned process for nanotube/nanowire FETs |
| US20070155064A1 (en) * | 2005-12-29 | 2007-07-05 | Industrial Technology Research Institute | Method for manufacturing carbon nano-tube FET |
| CN105810748B (en) * | 2014-12-31 | 2018-12-21 | 清华大学 | N-type TFT |
-
2017
- 2017-01-04 CN CN201710004518.6A patent/CN108269802B/en active Active
- 2017-07-03 TW TW106122286A patent/TWI657041B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1330412A (en) * | 2000-06-27 | 2002-01-09 | 三星电子株式会社 | Vertical nanometer size transistor using carbon monometer tube and manufacturing method thereof |
| CN1638066A (en) * | 2004-01-07 | 2005-07-13 | 国际商业机器公司 | Vertical carbon nanotube field effect transistor |
| US8168495B1 (en) * | 2006-12-29 | 2012-05-01 | Etamota Corporation | Carbon nanotube high frequency transistor technology |
| CN101217128A (en) * | 2007-01-04 | 2008-07-09 | 奇梦达股份公司 | Method for making an integrated circuit having a via hole |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI657041B (en) | 2019-04-21 |
| TW201836970A (en) | 2018-10-16 |
| CN108269802A (en) | 2018-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6948100B2 (en) | Graphene FET with graphite interface on contacts | |
| CN102598277B (en) | Semiconductor device and process for manufacturing same | |
| TWI479547B (en) | Method of fabricating thin film transistor and top-gate type thin film transistor | |
| JP5139368B2 (en) | Thin film transistor manufacturing method | |
| Liu et al. | Aligned carbon nanotubes: from controlled synthesis to electronic applications | |
| CN105742156B (en) | The method for forming graphene-structured | |
| WO2014017592A1 (en) | Graphene transistor and manufacturing method therefor | |
| Liu et al. | Atomic layer deposited 2D MoS 2 atomic crystals: From material to circuit | |
| CN108242444B (en) | Vacuum tube field effect transistor array and manufacturing method thereof | |
| US9741568B2 (en) | Sulfur doping method for graphene | |
| CN111146079B (en) | Synthesis and application of two-dimensional metal-semiconductor Van der Waals heterojunction array | |
| US9735362B2 (en) | Tunneling nanotube field effect transistor and manufacturing method thereof | |
| CN108269802B (en) | Carbon nano tube beam field effect transistor array and manufacturing method thereof | |
| CN107946364A (en) | Inorganic, metal oxide thin film transistor (TFT) and its manufacture method with compound crystal form | |
| CN101941696B (en) | Nanolithographic method applied to manufacture of graphene-based field effect tube | |
| US9768400B2 (en) | Method of making N-type semiconductor layer and method of making N-type thin film transistor | |
| US10141261B2 (en) | Device comprising nanostructures and method of manufacturing thereof | |
| CN107527803B (en) | The preparation method of SiC device gate dielectric layer and SiC device structure | |
| CN114477105B (en) | Two-dimensional BiCuSeO nanosheet, preparation method thereof and semiconductor device | |
| JP4774665B2 (en) | Manufacturing method of semiconductor device | |
| JP2007165473A (en) | Electronic element using carbon nano-tube and method of manufacturing same | |
| CN210156382U (en) | SiC-based MOS device | |
| JP6350983B2 (en) | Method for producing thin film by applying electric field and thin film semiconductor device using the same | |
| TWI307958B (en) | Field effect transistor | |
| JP2013098396A (en) | Method of manufacturing graphene structure and method of manufacturing semiconductor device using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |