1307958 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種場效應電晶體，尤指一種基於奈米碳管之場效 應電晶體。 【先前技術】 自k第一個IC(Integrated Circuit)誕生以來，以矽器件為基礎 之微處理器產品之研發與製造在摩爾定律下以每18個月電晶體之數量 ，一番之速度極速發展著。到2〇〇2年’微處理器已經含有76〇〇萬個 電晶體，能夠實現非常強大之功能。然而，科學界普遍認為摩爾定律 不會永遠有效，50納米係現代半導體工藝之極限，而inte丨之最新工 藝係0.13微米，即矽極限將在10〜15年内到達。 矽器件之基礎係石夕原子組成之晶體。晶體甲石夕原子不連續之能極 構成了能量帶，半導體中之電子於能量帶中運動。能帶之能量遠遠大 於矽原子能極之能量’它會使電子從原子之特定能級中逸出。如果矽 片上電晶體尺寸非常小，能帶導致之電子逸出就會產生相鄰電晶體之 間嚴重漏電，造成電子開關無法“關斷” ^另外，電晶體尺寸過小亦 會給散熱造成巨大困難。這些物理性之難題將使提高矽器件集成度之 .成本越來越高。 自從1991年發現奈米碳管（具體參見Nature, 1991,354,56) 以來’ 1998年’ IBM與NEC合作成功地用一根半導體性之奈米碳管製 成場效應電晶體（具體參見Applied Physics Letters, 1998, 73, 2447)，從而拉開了用碳器件取代矽器件之序幕。該基於一根奈米碳管 之電晶體體現出良好地電學性能，當閘極電壓變動時，源極汲極間之 電導變化為10萬倍。由於奈米碳管之尺寸非常小，據預測，如果用奈 米碳官製成器件，其電晶體之密度可比當前最先進之〇· 13微米矽器件 高6萬倍。 然而，上述用單根奈米碳管製作之場效應電晶體需要採用特殊製 作工藝，如使用原子力顯微鏡(八跗，Atom Force Microscope)進行加 工，製作成本非常高，僅適合用於實驗階段，不適合於大規模生產。 1307958 、成本低、熱性能好之場效應 有鑒於此，提供一種製作方法簡單 電晶體實為必要。 【發明内容】 解決先前技術之問題，本發明之目的在於提供―種製作方法 早、成本低、熱性能好之場效應電晶體。 a 本，明之另-目的在於提供一種製作上述場效應電晶體之方法。 〃為實現本發明之目的’本發明提供_種場效應電晶體，其包括： -第-導電翻之半導體層；—第二導電難之源腿雜 電類型之祕區域分獅成於上述半導體層，騎㈣域與沒極^域 相距-定距離；-絕緣氧化層職於上述半導體層上，錄于上述源 極區域與祕區域之間；-源極電極、—祕雜及—閘極電極分別 形成於上述源極區域、汲極區域與絕緣氧化層上，其中上述第一 類型之半導體層為一半導體性奈米碳管層。 ’、 ~ 本發明奈米碳管層中奈米碳管之直徑為2，奈米，高度為2〇〜5〇〇 奈米’絕緣氧化層之材料為二氧化石夕。 為實現本發明之另-目的，本發明還提供一種製作上述場效應電 晶體之方法，包括以下步驟：提供一第一導電類型之半導體性奈米碳 管層，；於上述奈米碳管層襯底形成第二導電類型之源極區二與二 極區域，該源極區域與汲極區域相距一定距離；於奈米碳管層襯底上、 源極區域倾麵域之間形成-縣氧化層；分別設置金屬電極於上 述源極區域、>及極區域與絕緣氧化層上。 與先前技術之場效應電晶體相較，本發明之場效應電晶體具有如 下優點：其-’直接採用奈来碳管屢替代傳統場效應電晶體之石夕概底， 能夠與傳統矽工藝技術相結合，適合大規模生産應用；其二，奈米碳 管本身具有極高之導熱係數，達到4⑻〜1〇〇〇Watt/m κ，因而可二有二 地將電晶體工作所產生之熱量快速散掉，從而解決當集成度提高所存 在之散熱問題；其三，由於採用奈米碳管作爲襯底，其奈米級加工可 以使得目前矽器件〇. 13微米之工藝變得更小，如60奈米以下，所以 每個電晶體之尺寸亦變得更小，且由於碳原子本身比矽原子穩定，可 1307958 以實現以更少之電子移動來完成電晶體之開關功能’從而能夠減少系 統熱量之產生。 ” 【實施方式】 請參閱第—圖，一 P型奈米碳管層12襯底；一 N型摻雜區域作爲 源極區域13與一N型摻雜區域作爲汲極區域14分別形成於上述上述p 型奈米破官層12，該源極區域13與汲極區域14相距一定距離；一絕 緣氧化層15形成於上述上述p型奈米碳管層ι2上，且位于上述源極 區域13與及極區域14之間；一源極電極131、一汲極電極14丨及一閘 極電極丨51分別形成於上述源極區域13、汲極區域14與絕緣氧化層 15上。其中，本實施例之絕緣氧化層15為二氧化矽層，金屬電極選自 |呂、金或銅電極。 請參閱第二圖，本發明進一步提供一種場效應電晶體U之製作方 法，其包括以下步驟： 步驟10係提供一 P型奈米碳管層襯底； 步驟20係於上述p型奈米碳管層襯底相距一定距離通過離子注入 方法進行掺雜，形成N型之源極區域與汲極區域，其中本實施例採用 麟離子進行摻雜；1307958 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a field effect transistor, and more particularly to a field effect transistor based on a carbon nanotube. [Prior Art] Since the birth of the first IC (Integrated Circuit), the development and manufacture of microprocessor products based on germanium devices has been extremely fast in the number of transistors per 18 months under Moore's Law. Developed. By the end of the year, the microprocessor already contains 600,000 transistors, which can achieve very powerful functions. However, the scientific community generally believes that Moore's Law will not last forever, 50 nanometers is the limit of modern semiconductor technology, and the latest process of inte丨 is 0.13 micron, that is, the limit will reach within 10 to 15 years. The basis of the germanium device is the crystal composed of the stone atoms. The energy of the discontinuity of the crystals of the crystals forms an energy band, and the electrons in the semiconductor move in the energy band. The energy of the energy band is much larger than the energy of the atomic energy of the atom. It causes electrons to escape from the specific energy level of the atom. If the size of the transistor on the enamel is very small, the electrons that can be caused by the band will cause serious leakage between adjacent transistors, causing the electronic switch to not be "turned off". In addition, the size of the transistor is too small, which will cause huge heat dissipation. difficult. These physical challenges will increase the cost of integration of devices. Since the discovery of carbon nanotubes in 1991 (see Nature, 1991, 354, 56 for details), '1998' IBM and NEC have successfully fabricated field-effect transistors using a semiconducting carbon nanotube (see Applied for details). Physics Letters, 1998, 73, 2447), which opened the curtain for replacing germanium devices with carbon devices. The transistor based on a carbon nanotube exhibits good electrical performance. When the gate voltage fluctuates, the conductance change between the source and the drain is 100,000 times. Due to the very small size of the carbon nanotubes, it is predicted that if the device is made of nanocarbon, the density of the transistor can be 60,000 times higher than that of the most advanced 13 micron device. However, the above-mentioned field effect transistor made of a single carbon nanotube requires a special fabrication process, such as processing using an atomic force microscope (Atom Force Microscope), which is very expensive to manufacture and is only suitable for use in an experimental stage. For mass production. 1307958, low cost, good thermal performance field effect In view of this, it is necessary to provide a simple manufacturing method. SUMMARY OF THE INVENTION In order to solve the problems of the prior art, it is an object of the present invention to provide a field effect transistor having an early production method, low cost, and good thermal performance. a, in addition, is intended to provide a method of fabricating the above-described field effect transistor. In order to achieve the object of the present invention, the present invention provides a field effect transistor comprising: - a first conductive turn-on semiconductor layer; - a second conductive difficult source leg type of impurity type divided into the above semiconductor Layer, riding (four) domain and immersion ^ domain distance - fixed distance; - insulating oxide layer on the above semiconductor layer, recorded between the source region and the secret region; - source electrode, - secret and gate The electrodes are respectively formed on the source region, the drain region and the insulating oxide layer, wherein the first type of semiconductor layer is a semiconducting carbon nanotube layer. The carbon nanotubes in the carbon nanotube layer of the present invention have a diameter of 2, a nanometer, and a height of 2 〇 to 5 Å. The material of the insulating oxide layer is sulphur dioxide. In order to achieve the other object of the present invention, the present invention also provides a method for fabricating the above field effect transistor, comprising the steps of: providing a first conductivity type semiconductor carbon nanotube layer; and the above carbon nanotube layer The substrate forms a source region second and a bipolar region of the second conductivity type, the source region and the drain region are separated by a certain distance; forming a county on the carbon nanotube layer substrate and the source region tilt region An oxide layer; respectively, a metal electrode is disposed on the source region, > and a pole region and an insulating oxide layer. Compared with the field effect transistor of the prior art, the field effect transistor of the present invention has the following advantages: it can directly replace the traditional field effect transistor with the Nile carbon tube, and can be combined with the traditional 矽 process technology. Combined, suitable for large-scale production applications; second, the carbon nanotube itself has a very high thermal conductivity, reaching 4 (8) ~ 1 〇〇〇 Watt / m κ, so that the heat generated by the transistor can be two and two Quickly dissipate, so as to solve the heat dissipation problem when the integration is improved; Third, due to the use of carbon nanotubes as the substrate, the nano-scale processing can make the process of the current device 13. 13 microns smaller, For example, below 60 nm, the size of each transistor is also smaller, and since the carbon atoms themselves are more stable than helium atoms, 1307958 can be used to achieve the switching function of the transistor with less electron movement'. System heat generation. [Embodiment] Please refer to the first figure, a P-type carbon nanotube layer 12 substrate; an N-type doped region as a source region 13 and an N-type doped region as a drain region 14 are respectively formed in the above In the p-type nano-destroy layer 12, the source region 13 is spaced apart from the drain region 14; an insulating oxide layer 15 is formed on the p-type carbon nanotube layer ι2, and is located in the source region 13 A source electrode 131, a drain electrode 14A, and a gate electrode 51 are formed on the source region 13, the drain region 14, and the insulating oxide layer 15, respectively. The insulating oxide layer 15 of the embodiment is a ruthenium dioxide layer, and the metal electrode is selected from a ruthenium, gold or copper electrode. Referring to the second figure, the present invention further provides a method for fabricating the field effect transistor U, which comprises the following steps: Step 10 is to provide a P-type carbon nanotube layer substrate; Step 20 is to dope the substrate of the p-type carbon nanotube layer at a certain distance by ion implantation to form an N-type source region and a drain electrode. Region, wherein the embodiment uses cation ions for doping ;
步驟30係於奈米碳管層襯底上、源極區域與汲極區域之 絕緣氣化層； X 步驟40係分別設置金屬電極於上述源極區域、汲極區域與絕緣氧 化層上刀別开》成場效應電晶體之源極電極、没極電極與閘極電極。 本發明奈米碳管層襯底之形成方法包括以下步驟： 提供一基底，基底材料可選自碳、玻璃或矽； 於基底上沈積一催化劑層，催化劑層之厚度為5〜3〇奈米，催化劑 層沈積之方法可顧真空熱蒸鍍揮發法，亦可選用電子束轉法。催 材料可選職、m域其合金，本實施方式選用鐵 1乍為催化劑材料，其沈積之厚度為10奈米； 將TT有催化劑層之基底置於空氣中，退火以使催化劑層氧化、收 縮成爲奈米級之催化劑顆粒。待退火完畢，再將分佈有催化劑顆粒之 1307958 基底置於反應室内（圖未示）’通入碳源氣乙快以及保護氣體氮氣，利 用低温，化學目沈積法，於上述催化劑馳上生長奈米❹，形成 奈米碳官薄膜’碟源氣亦可選用其他含峻之氣體，如乙稀、笨、一氧 化=等n以笨作Μ源氣時，其保護氣體應賴氫氣，以一氧 化碳作爲碳職時’其槪舰·錢基鐵阿⑽。本發明生成之 奈米碳管之直徑為2〜1G奈米，高度為2G〜5⑽奈米’低溫化學氣相沈 積法之生長溫度為550〜600攝氏度。 曰本實施例之場效應電晶體u為？溝道金屬氧化物半導體場效應電 晶體’本領域之技術人貢應明白，肖N型奈米碳管層襯底進行p型播 掏可形成N 4道型金騎化物半賴場效應電晶體。同樣，用半導 體型奈米碳T層取代傳統電晶體之賴底亦可形成結型場效應電晶 體，絕緣柵型場效應電晶體等其他場效應電晶體。 〜 本發明之場效應電晶體具有如下優點：其…直接制奈米碳管 層替代傳麟效應電晶體之独底，能触傳财工紐術相結合， 適合大規模生錢用；其二’奈米碳管本身具有極高之導齡數，達 到40(M_watt/m K ’因而可以有效地將電晶體工作所產生之執量快 速散^從而解決當集成度提高所存在之散熱問題；其三，由於採用 奈米，管作爲襯底，其奈米級加卫可以使得目前㈣件Q l3微米之工 藝變得更小，如6G奈米以下’所以每個電晶體之尺寸亦變得更小，且 ^於碳原子本身比Μ子歡，可以實現处少之電子祕來完成電 晶體之開關功能，從而能夠減少系統熱量之產生。 ,綜上所述，本發明符合發明專利之要件，爰依法提出專利申請。 惟’以上所述者僅為本發明之較佳實施例，舉凡熟悉本案技藝之人士， 在援，本案發明精神所作之等效_或變化，皆應包含於以下之申許 專利摩色圍内。 月 【圖式簡單說明】 第一圖係本發明場效應電晶體之示意圖。 第一圖係本發明場效應電晶體之製作方法之流程示意圖。 【主要元件符號說明】 1307958 場效應電晶體 11 奈米碳管層 12 源極區域 13 源極電極 131 >及極區域 14 汲極電極 141 絕緣氧化層 15 閘極電極 151Step 30 is an insulating gasification layer on the carbon nanotube layer substrate, the source region and the drain region; X step 40 is respectively provided with a metal electrode on the source region, the drain region and the insulating oxide layer The source electrode, the electrodeless electrode and the gate electrode of the field effect transistor. The method for forming a carbon nanotube layer substrate of the present invention comprises the steps of: providing a substrate, the substrate material may be selected from carbon, glass or germanium; depositing a catalyst layer on the substrate, the catalyst layer having a thickness of 5 to 3 nanometers The method for depositing the catalyst layer may be a vacuum thermal evaporation method or an electron beam conversion method. The material is optional, and the m-domain alloy is used. In this embodiment, the iron is used as the catalyst material, and the thickness of the deposition is 10 nm; the substrate of the TT catalyst layer is placed in the air, and the catalyst layer is oxidized, The shrinkage becomes a nano-sized catalyst particle. After the annealing is completed, the 1307958 substrate with the catalyst particles distributed is placed in the reaction chamber (not shown), and the carbon source gas and the protective gas nitrogen are introduced, and the catalyst is allowed to pass through the above-mentioned catalyst by using a low temperature and chemical deposition method. Rice bran, the formation of nano carbon official film 'disc source gas can also choose other gas containing steep gas, such as ethylene, stupid, mono-oxidation = n, when the stupid gas source, its protective gas should be hydrogen, with carbon monoxide As a carbon job, his ship, Qian Jitie (10). The carbon nanotubes produced by the present invention have a diameter of 2 to 1 G nanometer and a height of 2 G to 5 (10) nm. The growth temperature of the low temperature chemical vapor deposition method is 550 to 600 °C. What is the field effect transistor u of this embodiment? Channel metal oxide semiconductor field effect transistor] It is understood by those skilled in the art that the P-type seeding of the Xiao N-type carbon nanotube layer substrate can form a N 4 -type gold-ride compound semiconductor field effect transistor. . Similarly, the replacement of the conventional transistor by the semiconductor nano-T layer can also form a junction field effect transistor, an insulated gate field effect transistor and other field effect transistors. ~ The field effect transistor of the invention has the following advantages: its direct production of the carbon nanotube layer replaces the sole of the transmission of the transistor, and can be combined with the financial technology, which is suitable for large-scale production of money; 'The carbon nanotubes themselves have a very high number of lead years, reaching 40 (M_watt/m K ', which can effectively dissipate the heat generated by the operation of the transistor to solve the heat dissipation problem when the integration is improved; Thirdly, due to the use of nanometers and tubes as the substrate, the nano-level reinforcement can make the current (four) Q l3 micron process smaller, such as below 6G nanometers, so the size of each transistor also becomes Smaller, and ^ carbon atoms themselves than the scorpion, can achieve a small number of electronic secrets to complete the switching function of the transistor, which can reduce the generation of system heat. In summary, the invention meets the requirements of the invention patent爰 提出 提出 提出 提出 提出 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟Application The first figure is a schematic diagram of the method of fabricating the field effect transistor of the present invention. [Main component symbol description] 1307958 Field Effect transistor 11 Carbon nanotube layer 12 Source region 13 Source electrode 131 > and Polar region 14 Gate electrode 141 Insulating oxide layer 15 Gate electrode 151
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