CN108269802A - A kind of carbon nano-tube bundle fet array and its manufacturing method - Google Patents
A kind of carbon nano-tube bundle fet array and its manufacturing method Download PDFInfo
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- CN108269802A CN108269802A CN201710004518.6A CN201710004518A CN108269802A CN 108269802 A CN108269802 A CN 108269802A CN 201710004518 A CN201710004518 A CN 201710004518A CN 108269802 A CN108269802 A CN 108269802A
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 184
- 229910021393 carbon nanotube Inorganic materials 0.000 title claims abstract description 170
- 239000002041 carbon nanotube Substances 0.000 title claims abstract description 170
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
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- 229910052799 carbon Inorganic materials 0.000 claims description 14
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- 238000000034 method Methods 0.000 claims description 9
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- 238000000137 annealing Methods 0.000 claims description 7
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- 238000000926 separation method Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 230000005669 field effect Effects 0.000 description 8
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- 239000000956 alloy Substances 0.000 description 5
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- 229910052737 gold Inorganic materials 0.000 description 5
- 229910052741 iridium Inorganic materials 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 229910052707 ruthenium Inorganic materials 0.000 description 5
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
Abstract
The present invention provides a kind of carbon nano-tube bundle fet array and its manufacturing method, the carbon nano-tube bundle fet array include：Source electrode material layer, drain material layer and the carbon nano-tube bundle array being connected between the source electrode material layer and drain material layer；The carbon nano-tube bundle array includes the carbon nano-tube bundle unit of several discrete settings, wherein, the axial first end of the carbon nano-tube bundle unit is connect with the source electrode material layer, and the axial second end of the carbon nano-tube bundle unit is connect with the drain material layer；The carbon nano-tube bundle unit is surrounded by gate structure.The carbon nano-tube bundle fet array of the present invention is resistant to higher operation voltage and operation electric current, can be applied to high power device.And the present invention can improve manipulation ability of the grid to raceway groove using gate-all-around structure.The manufacturing method of the carbon nano-tube bundle fet array of the present invention has the characteristics that processing step is simple, advantageously reduces production cost.
Description
Technical field
The invention belongs to technical field of integrated circuits, are related to a kind of carbon nano-tube bundle fet array and its manufacture
Method.
Background technology
For carrier transport medium, vacuum is substantially better than solid, because it allows ballistic transport, and in semiconductor
In, carrier can be by optics and acoustic phonon scattering.Velocity of electrons in vacuum is theoretically 3 × 1010Cm/s, but partly leading
In body, velocity of electrons is only about 5 × 107cm/s.Some scientists think, in evacuated transistor, it appears that only electronics can be with
It flows between the electrodes, and hole cannot.Unless we learn to handle positive electron, otherwise would be impossible to do any complementary type electricity
Road, such as CMOS.Without complementary type circuit, power will be excessively high, and most possible limitation evacuated transistor, which enters, to segment market.Very
Hard to imagine, any large digital circuit can all use evacuated transistor.
At present evacuated transistor there are mainly four types of type (Jin-Woo Han, Jae Sub Oh and M.Meyyappan,
Vacuum Nanoelectronics:Back to the Future-Gate insulated nanoscale vacuum
channel transistor,APL,100,213505(2012))：(a) vertical field emission type, (b) plane transverse direction field emission type,
(c) MOSFET types, (d) insulated gate air channel transistor.
In recent years, it has had been reported that and has disclosed in the case where preferably enclosing grid geometric shape, carbon nanotube field-effect transistor
(CNTFET) self-aligning grid size can narrow down to 20 nanometers, and (IBM creates first 9nm carbon nanometer transistor, passes through
Gareth Halfacree were delivered on January 30th, 2012).Grid surround carbon nano-tube channel uniformity it is verified that,
And this process will not damage carbon nanotube.In addition, using suitable gate dielectric layer, N-type transistor or p-type can be realized
Transistor, wherein, utilize HfO2N-type transistor can be realized as gate dielectric layer, utilize Al2O3It can be real as gate dielectric layer
Existing P-type transistor (Aaron D.Franklin, Carbon Nanotube Complementary Wrap-Gate
Transistors, Nano Lett., 2013,13 (6), pp 2490-2495).These find not to be only to enclose grid carbon nanotube device
The further research of part provides a promising platform, and it is existing to show that the large scale digital switch using carbon nanotube possesses
Real Technology Potential.
However, it is still necessary to the potentiality and possibility of exploitation CNTFET, can be used for manufacture and possess high operation voltage
With the high power device of high driving current.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of carbon nano-tube bundle field-effect crystalline substances
Body pipe array and its manufacturing method may not apply to high-power device for solving carbon nanotube field-effect transistor in the prior art
The problem of part.
In order to achieve the above objects and other related objects, the present invention provides a kind of carbon nano-tube bundle field-effect transistor battle array
Row, including：
Source electrode material layer；
Drain material layer is formed in above the source electrode material layer；
Carbon nano-tube bundle array is connected between the source electrode material layer and the drain material layer；The carbon nanotube
Beam array includes the carbon nano-tube bundle unit of several discrete settings, wherein, the axial first end of the carbon nano-tube bundle unit with
The source electrode material layer connection, the axial second end of the carbon nano-tube bundle unit are connect with the drain material layer；
Gate structure is formed in the carbon nano-tube bundle array between each carbon nano-tube bundle unit, and the grid
By the first insulator separation between structure and the source electrode material layer, lead between the gate structure and the drain material layer
Cross second insulating layer isolation；Wherein, the gate structure includes gate dielectric layer and gate material layers, the gate dielectric layer packet
The lateral surface of the carbon nano-tube bundle unit is enclosed, the gate material layers surround the gate material layers lateral surface.
Optionally, the carbon nano-tube bundle fet array further includes substrate and be formed in the substrate
Three insulating layers, the source electrode material layer are formed on the third insulating layer.
Optionally, the angle between plane where the axial and source electrode material layer of the carbon nano-tube bundle unit is
80 °~100 °.
Optionally, the height of the carbon nano-tube bundle unit is more than 100 μm.
Optionally, the gate dielectric layer uses high K dielectric, and the gate material layers include metal material.
Optionally, the source electrode material layer includes metal material with drain material layer.
The present invention also provides a kind of manufacturing methods of carbon nano-tube bundle fet array, include the following steps：
S1：One substrate is provided, sequentially forms third insulating layer, source electrode material layer and the first insulating layer on the substrate；
S2：Through-hole array is formed in first insulating layer；The through-hole array includes the through-hole of several discrete settings,
The through-hole exposes the source electrode material layer upper surface；
S3：Carbon nano-tube bundle array is formed based on the through-hole array；The carbon nano-tube bundle array includes several and institute
The corresponding carbon nano-tube bundle unit of lead to the hole site is stated, wherein, axial first end and the source of the carbon nano-tube bundle unit
Pole material layer connection；
S4：Form the gate dielectric layer for covering the carbon nano-tube bundle unit lateral surface；
S5：Form the gate material layers for covering the gate dielectric layer lateral surface；
S6：Second insulating layer and drain material layer are sequentially formed, wherein, the axial second end of the carbon nano-tube bundle unit
It is connect with the drain material layer, between the gate dielectric layer and gate material layers and the drain material layer by second absolutely
Edge layer is isolated.
Optionally, in the step S3, under protective atmosphere, using catalyst and carbon source, pass through chemical vapor deposition
Area method forms the carbon nano-tube bundle array.
Optionally, the protective atmosphere includes N2、H2, it is one or more in Ar, the catalyst includes Fe, Ni, Co
In it is one or more, the growth temperature range of the carbon nano-tube bundle array is 500~740 DEG C.
Optionally, it is primarily based on the through-hole array and forms the catalyst in the source electrode material layer upper surface, then
Based on carbon nano-tube bundle array described in the catalyst growth.
Optionally, the solution comprising catalyst ion is applied to the source electrode material layer surface, and annealed, to increase
Add the bond strength of catalyst ion and the source electrode material layer.
Optionally, the temperature range of the annealing is 700~900 DEG C, and annealing time is 30~90min.
Optionally, the step of further including the catalyst ion for removing the second insulating layer excess surface.
Optionally, the catalyst ion of the second insulating layer excess surface is removed by wet etching.
Optionally, the angle between plane where the axial and source electrode material layer of the carbon nano-tube bundle unit is
80 °~100 °.
Optionally, the height of the carbon nano-tube bundle unit is more than 100 μm.
As described above, the carbon nano-tube bundle fet array and its manufacturing method of the present invention, have beneficial below
Effect：The carbon nano-tube bundle fet array of the present invention is using carbon nano-tube bundle as channel material, wherein carbon nanometer
Tube bundle unit only has external carbon nanotube to be surrounded by gate dielectric layer, and there is no by gate dielectric for internal carbon nanotube
Layer is surrounded, but due to the interaction between carbon nanotube each in carbon nano-tube bundle, inside carbon nano-tube bundle unit
Carbon nanotube remains able to play useful effect.The carbon nano-tube bundle fet array of the present invention is resistant to higher
Voltage and operation electric current are operated, can be applied to high power device.And the present invention can improve grid pair using gate-all-around structure
The manipulation ability of raceway groove.The manufacturing method of the carbon nano-tube bundle fet array of the present invention is simple with processing step
Feature advantageously reduces production cost.
Description of the drawings
Fig. 1 is shown as the structure diagram of the carbon nano-tube bundle fet array of the present invention.
Fig. 2 is shown as the manufacturing method of the carbon nano-tube bundle fet array of the present invention on the substrate successively
Form the schematic diagram of third insulating layer, source electrode material layer and the first insulating layer.
Fig. 3 is shown as the manufacturing method of the carbon nano-tube bundle fet array of the present invention in first insulating layer
The middle schematic diagram for forming through-hole array.
The manufacturing method that Fig. 4 is shown as the carbon nano-tube bundle fet array of the present invention is based on the through-hole array
The schematic diagram of the catalyst is formed in the source electrode material layer upper surface.
The manufacturing method that Fig. 5 is shown as the carbon nano-tube bundle fet array of the present invention is given birth to based on the catalyst
The schematic diagram of the long carbon nano-tube bundle array.
The manufacturing method formation covering carbon that Fig. 6 is shown as the carbon nano-tube bundle fet array of the present invention is received
The schematic diagram of the gate dielectric layer of rice tube bundle unit lateral surface.
The manufacturing method that Fig. 7 is shown as the carbon nano-tube bundle fet array of the present invention forms the covering grid
The schematic diagram of the gate material layers of dielectric layer lateral surface.
Fig. 8 is shown as the manufacturing method removal part of grid pole medium of the carbon nano-tube bundle fet array of the present invention
Layer and gate material layers, to expose the schematic diagram on carbon nano-tube bundle array top.
Fig. 9 be shown as the present invention carbon nano-tube bundle fet array manufacturing method formed second insulating layer and
The schematic diagram of drain material layer.
Component label instructions
101 substrates
102 third insulating layers
103 source electrode material layers
104 first insulating layers
105 carbon nano-tube bundle units
106 gate dielectric layers
107 gate material layers
108 second insulating layers
109 drain material layers
110 through-holes
111 catalyst
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
It please refers to Fig.1 to Fig. 9.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in schema then
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The present invention provides a kind of carbon nano-tube bundle fet array, referring to Fig. 1, being shown as the carbon nano-tube bundle
The structure diagram of fet array, including：
Source electrode material layer 103；
Drain material layer 109 is formed in 103 top of source electrode material layer；
Carbon nano-tube bundle array is connected between the source electrode material layer 103 and the drain material layer 109；The carbon
Nanotube bundle array includes the carbon nano-tube bundle unit 105 of several discrete settings, wherein, the carbon nano-tube bundle unit 105
Axial first end is connect with the source electrode material layer 103, axial second end and the drain electrode of the carbon nano-tube bundle unit 105
Material layer 109 connects；
Gate structure is formed in the carbon nano-tube bundle array between each carbon nano-tube bundle unit 105, and the grid
It is isolated between pole structure and the source electrode material layer 103 by the first insulating layer 104, the gate structure and the drain material
It is isolated between layer 109 by second insulating layer 108；Wherein, the gate structure includes gate dielectric layer 106 and gate material layers
107, the gate dielectric layer 106 surrounds the lateral surface of the carbon nano-tube bundle unit 105, and the gate material layers 107 are surrounded
The lateral surface of the gate material layers 107.
In the present embodiment, the carbon nano-tube bundle fet array further includes substrate 101 and is formed in the base
Third insulating layer 102 on bottom 101, the source electrode material layer 103 are formed on the third insulating layer 102.
Specifically, the substrate 101 includes but not limited to the conventional semiconductors substrate materials such as Si, Ge.The third insulation
Silica or other insulating materials can be used in layer 102, for the source electrode material layer 103 to be isolated with the substrate 101.
Specifically, each carbon nano-tube bundle 105 channel material as a field-effect transistor of unit, axial two
End is connect respectively with the source electrode material layer 103 and the drain material layer 109.The source electrode material layer 103 is used as carbon nanometer
Restrain the N+ type source electrodes of field-effect transistor, N+ type of the drain material layer 109 as carbon nano-tube bundle field-effect transistor
Drain electrode.
In the present embodiment, the height of the carbon nano-tube bundle unit 105 is more than 100 μm.The carbon nano-tube bundle unit 105
The axial angle between the 103 place plane of source electrode material layer be 80 °~100 °, preferably 90 °.In other words, institute
Axial direction and the 103 place plane of source electrode material layer for stating carbon nano-tube bundle unit 105 are vertical or substantially vertical.
Specifically, the carbon nano-tube bundle unit 105 is made of more carbon nanotubes, wherein, only positioned at carbon nanotube
The carbon nanotube of beam periphery is surrounded or all surrounded by 106 part of gate dielectric layer, and inside carbon nano-tube bundle
There is no surrounded, but due to the phase interaction between carbon nanotube each in carbon nano-tube bundle carbon nanotube by gate dielectric layer 106
With the carbon nanotube inside the carbon nano-tube bundle unit 105 remains able to play useful effect.It is received relative to single carbon
Mitron, as channel material, can cause carbon to receive as raceway groove, the present invention using the carbon nano-tube bundle comprising more carbon nanotubes
The higher operation voltage of mitron beam fet array tolerance and operation electric current, so as to be applied to high power device.
It is described since the gate dielectric layer 106 surrounds the lateral surface of the carbon nano-tube bundle unit 105 in the present invention
Gate material layers 107 surround the lateral surface of the gate material layers 107 so that the gate structure forms gate-all-around structure, can be with
Improve manipulation ability of the grid to carbon nano-tube bundle raceway groove.
As an example, in the gate structure, the gate dielectric layer 106 (is higher than Jie of silica using high K dielectric
Electric constant 3.9), for example, hafnium base oxide, HfO2, HfSiO, HfSiON, HfTaO, HfTiO etc. or other dielectric materials.Institute
Gate material layers 107 are stated using metal gate, including metal material, such as including Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al,
Any one in any one or its alloy in Co, W, Mo.
As an example, the source electrode material layer 103 and drain material layer 109 also include metal material, for example, including Ti,
Any one in any one or its alloy in Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo.
The carbon nano-tube bundle fet array of the present invention uses carbon nano-tube bundle as channel material, and using ring
Grid structure can not only be applied to high power device, and with stronger channel controllability.
Embodiment two
The present invention also provides a kind of manufacturing methods of carbon nano-tube bundle fet array, include the following steps：
Referring initially to Fig. 2, step S1 is performed：A substrate 101 is provided, it is exhausted to sequentially form third in the substrate 101
Edge layer 102,103 and first insulating layer 104 of source electrode material layer.
Specifically, the substrate 101 includes but not limited to the conventional semiconductors substrate materials such as Si, Ge.The third insulation
Layer 102 uses silica or other insulating materials, for the source electrode material layer 103 to be isolated with the substrate 101.The source
Pole material layer 103 includes metal material, such as including any one in Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo
Kind or its alloy in any one.First insulating layer 104 uses silica or other insulating materials.
Physical vaporous deposition or change can be used in the third insulating layer 102, source electrode material layer 103, the first insulating layer 104
Vapour deposition process is learned to be formed.
Referring next to Fig. 3, step S2 is performed：Through-hole array is formed in first insulating layer 104；The through-hole battle array
Row include the through-hole 110 of several discrete settings, and the through-hole 110 exposes 103 upper surface of source electrode material layer.
Specifically, form the through-hole array by processing steps such as photoetching, etchings.The shape of the through-hole 110 includes
But it is not limited to polygon, circle, ellipse etc..
Then Fig. 4-Fig. 5 is please referred to, performs step S3：Carbon nano-tube bundle array is formed based on the through-hole array；It is described
Carbon nano-tube bundle array includes several and corresponding carbon nano-tube bundle unit 105 in 110 position of through-hole, wherein, the carbon
The axial first end of nanotube bundle unit 105 is connect with the source electrode material layer 103.
Specifically, each through-hole 110 corresponds to a carbon nano-tube bundle unit 105, each carbon nano-tube bundle unit 105 is equal
Channel material as a field-effect transistor.
In the present embodiment, under protective atmosphere, using catalyst and carbon source, formed by chemical vapour deposition technique described
Carbon nano-tube bundle array.The protective atmosphere includes N2、H2, it is one or more in Ar, the carbon source includes but not limited to first
The carbonaceous gas such as alkane, acetylene, the catalyst include one or more, the life of the carbon nano-tube bundle array in Fe, Ni, Co
Long temperature range is 500~740 DEG C.
Specifically, as shown in figure 4, be primarily based on the through-hole array forms institute in 103 upper surface of source electrode material layer
State catalyst 111.As an example, the solution comprising catalyst ion is applied to 103 surface of source electrode material layer, to be formed
The catalyst 111.In the present embodiment, the step of row is annealed is further included, to increase catalyst ion and the source electrode material layer
103 bond strength.The temperature range of the annealing is 700~900 DEG C, and annealing time is 30~90min.
Further, after annealing, the step for the catalyst ion for removing 104 excess surface of second insulating layer is further included
Suddenly.As an example, the catalyst ion of 104 excess surface of second insulating layer is removed by wet etching.
As shown in figure 5, being then based on the catalyst 111 grows the carbon nano-tube bundle array.It is described in the present embodiment
The axial angle between the 103 place plane of source electrode material layer of carbon nano-tube bundle unit 105 is 80 °~100 °, preferably
It is 90 °.In other words, the axial direction of the carbon nano-tube bundle unit 105 it is vertical with the 103 place plane of source electrode material layer or
It is substantially vertical.
As an example, processed substrate is placed in reacting furnace, it is heated to 500 DEG C~740 under protective gas
DEG C, it then passes to carbon-source gas and reacts about 5~30 minutes, growth obtains carbon nano-tube bundle array, and it is micro- that height is more than 100
Rice.The pure nano-carbon tube beam that the carbon nano-tube bundle array is formed for multiple parallel to each other and perpendicular to substrate grown carbon nanotube
Array.The carbon nano-tube bundle and the via area are essentially identical.Pass through above-mentioned control growth conditions, the super in-line arrangement carbon nanotube
The impurity such as agraphitic carbon or remaining catalyst metal particles are substantially free of in beam array.
Again referring to Fig. 6, performing step S4：Form the gate dielectric for covering 105 lateral surface of carbon nano-tube bundle unit
Layer 106.
Specifically, taking advantage of the occasion sedimentation using physical vapor or chemical vapour deposition technique forms the gate dielectric layer 106.Make
For example, the gate dielectric layer 106 is using high K dielectric (dielectric constant 3.9 for being higher than silica), such as the oxidation of hafnium base
Object, HfO2, HfSiO, HfSiON, HfTaO, HfTiO etc. or other dielectric materials.
Again referring to Fig. 7, performing step S5：Form the gate material layers for covering 106 lateral surface of gate dielectric layer
107。
Specifically, taking advantage of the occasion sedimentation using physical vapor or chemical vapour deposition technique forms the gate material layers 107.Make
For example, the gate material layers 107 use metal gate, including metal material, such as including Ti, Ta, Hf, Ni, Ru, Ir,
Any one in any one or its alloy in Au, Pt, Al, Co, W, Mo.
Further, as shown in figure 8, the removal part gate material layers 107 and gate dielectric layer 106, expose institute
State carbon nano-tube bundle array top.Minimizing technology can be the suitable method such as wet etching or plasma etching.
Finally referring to Fig. 9, performing step S6：Second insulating layer 108 and drain material layer 109 are sequentially formed, wherein, institute
The axial second end for stating carbon nano-tube bundle unit 105 is connect with the drain material layer 109, the gate dielectric layer 106 and grid
It is isolated between pole material layer 107 and the drain material layer 109 by second insulating layer 108.
Specifically, the second insulating layer 108 uses silica or other insulating materials, the drain material layer 109 wraps
Metal material is included, such as including in any one in Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo or its alloy
Any one.
Specifically, 105 top of carbon nano-tube bundle unit is embedded in the drain material layer 109, the carbon can be increased
The firmness connected between nanotube bundle unit 105 and the drain material layer 109.
So far, manufacture completes the carbon nano-tube bundle fet array of the present invention.The carbon nano-tube bundle of the present invention
The manufacturing method of fet array has the characteristics that processing step is simple, advantageously reduces production cost.
In conclusion the carbon nano-tube bundle fet array of the present invention uses carbon nano-tube bundle as raceway groove material
Material, wherein carbon nano-tube bundle unit only have external carbon nanotube to be surrounded by gate dielectric layer, and internal carbon nanotube is simultaneously
It is not surrounded by gate dielectric layer, but due to the interaction between carbon nanotube each in carbon nano-tube bundle, in carbon nanometer
Carbon nanotube inside tube bundle unit remains able to play useful effect.The carbon nano-tube bundle fet array of the present invention
Higher operation voltage and operation electric current are resistant to, can be applied to high power device.And the present invention uses gate-all-around structure,
Manipulation ability of the grid to raceway groove can be improved.The manufacturing method of the carbon nano-tube bundle fet array of the present invention has
The characteristics of processing step is simple advantageously reduces production cost.So the present invention effectively overcome it is of the prior art it is various lack
It puts and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (16)
1. a kind of carbon nano-tube bundle fet array, which is characterized in that including：
Source electrode material layer；
Drain material layer is formed in above the source electrode material layer；
Carbon nano-tube bundle array is connected between the source electrode material layer and the drain material layer；The carbon nano-tube bundle battle array
Row include the carbon nano-tube bundle units of several discrete settings, wherein, the axial first end of the carbon nano-tube bundle unit with it is described
Source electrode material layer connects, and the axial second end of the carbon nano-tube bundle unit is connect with the drain material layer；
Gate structure is formed in the carbon nano-tube bundle array between each carbon nano-tube bundle unit, and the gate structure
By the first insulator separation between the source electrode material layer, pass through between the gate structure and the drain material layer
Two insulator separations；Wherein, the gate structure includes gate dielectric layer and gate material layers, and the gate dielectric layer surrounds institute
The lateral surface of carbon nano-tube bundle unit is stated, the gate material layers surround the gate material layers lateral surface.
2. carbon nano-tube bundle fet array according to claim 1, it is characterised in that：The carbon nano-tube bundle
The third insulating layer that fet array further includes substrate and is formed in the substrate, the source electrode material layer are formed in
On the third insulating layer.
3. carbon nano-tube bundle fet array according to claim 1, it is characterised in that：The carbon nano-tube bundle
Angle between plane where the axial and source electrode material layer of unit is 80 °~100 °.
4. carbon nano-tube bundle fet array according to claim 1, it is characterised in that：The carbon nano-tube bundle
The height of unit is more than 100 μm.
5. carbon nano-tube bundle fet array according to claim 1, it is characterised in that：The gate dielectric layer
Using high K dielectric, the gate material layers include metal material.
6. carbon nano-tube bundle fet array according to claim 1, it is characterised in that：The source electrode material layer
Include metal material with drain material layer.
7. a kind of manufacturing method of carbon nano-tube bundle fet array, which is characterized in that include the following steps：
S1：One substrate is provided, sequentially forms third insulating layer, source electrode material layer and the first insulating layer on the substrate；
S2：Through-hole array is formed in first insulating layer；The through-hole array includes the through-hole of several discrete settings, described
Through-hole exposes the source electrode material layer upper surface；
S3：Carbon nano-tube bundle array is formed based on the through-hole array；The carbon nano-tube bundle array includes several and described logical
The corresponding carbon nano-tube bundle unit in hole site, wherein, the axial first end of the carbon nano-tube bundle unit and the source electrode material
The bed of material connects；
S4：Form the gate dielectric layer for covering the carbon nano-tube bundle unit lateral surface；
S5：Form the gate material layers for covering the gate dielectric layer lateral surface；
S6：Second insulating layer and drain material layer are sequentially formed, wherein, the axial second end of the carbon nano-tube bundle unit and institute
Drain material layer connection is stated, passes through second insulating layer between the gate dielectric layer and gate material layers and the drain material layer
Isolation.
8. the manufacturing method of carbon nano-tube bundle fet array according to claim 7, it is characterised in that：In institute
It states in step S3, under protective atmosphere, using catalyst and carbon source, the carbon nanotube is formed by chemical vapour deposition technique
Beam array.
9. the manufacturing method of carbon nano-tube bundle fet array according to claim 8, it is characterised in that：It is described
Protective atmosphere includes N2、H2, it is one or more in Ar, the catalyst include it is one or more in Fe, Ni, Co, it is described
The growth temperature range of carbon nano-tube bundle array is 500~740 DEG C.
10. the manufacturing method of carbon nano-tube bundle fet array according to claim 8, it is characterised in that：It is first
The catalyst is first formed in the source electrode material layer upper surface based on the through-hole array, is then based on the catalyst growth
The carbon nano-tube bundle array.
11. the manufacturing method of carbon nano-tube bundle fet array according to claim 10, it is characterised in that：It will
Solution comprising catalyst ion is applied to the source electrode material layer surface, and anneals, to increase catalyst ion and institute
State the bond strength of source electrode material layer.
12. the manufacturing method of carbon nano-tube bundle fet array according to claim 11, it is characterised in that：Institute
The temperature range for stating annealing is 700~900 DEG C, and annealing time is 30~90min.
13. the manufacturing method of carbon nano-tube bundle fet array according to claim 11, it is characterised in that：Also
The step of catalyst ion including removing the second insulating layer excess surface.
14. the manufacturing method of carbon nano-tube bundle fet array according to claim 13, it is characterised in that：It is logical
Cross the catalyst ion of second insulating layer excess surface described in wet method erosion removal.
15. the manufacturing method of carbon nano-tube bundle fet array according to claim 7, it is characterised in that：Institute
Angle between plane where stating the axial and source electrode material layer of carbon nano-tube bundle unit is 80 °~100 °.
16. the manufacturing method of carbon nano-tube bundle fet array according to claim 1, it is characterised in that：Institute
The height for stating carbon nano-tube bundle unit is more than 100 μm.
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| US11417729B2 (en) * | 2019-08-29 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistors with channels formed of low-dimensional materials and method forming same |
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| CN1330412A (en) * | 2000-06-27 | 2002-01-09 | 三星电子株式会社 | Vertical nanometer size transistor using carbon monometer tube and manufacturing method thereof |
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| TWI222742B (en) * | 2003-05-05 | 2004-10-21 | Ind Tech Res Inst | Fabrication and structure of carbon nanotube-gate transistor |
| US7598516B2 (en) * | 2005-01-07 | 2009-10-06 | International Business Machines Corporation | Self-aligned process for nanotube/nanowire FETs |
| US20070155064A1 (en) * | 2005-12-29 | 2007-07-05 | Industrial Technology Research Institute | Method for manufacturing carbon nano-tube FET |
| CN105810748B (en) * | 2014-12-31 | 2018-12-21 | 清华大学 | N-type TFT |
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| CN1330412A (en) * | 2000-06-27 | 2002-01-09 | 三星电子株式会社 | Vertical nanometer size transistor using carbon monometer tube and manufacturing method thereof |
| US20020163079A1 (en) * | 2001-05-02 | 2002-11-07 | Fujitsu Limited | Integrated circuit device and method of producing the same |
| US20060011972A1 (en) * | 2002-10-31 | 2006-01-19 | Andrew Graham | Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell |
| CN1638066A (en) * | 2004-01-07 | 2005-07-13 | 国际商业机器公司 | Vertical carbon nanotube field effect transistor |
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| Publication number | Publication date |
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| TWI657041B (en) | 2019-04-21 |
| CN108269802B (en) | 2020-11-06 |
| TW201836970A (en) | 2018-10-16 |
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