CN108258053A - Trench MOSFET and its process - Google Patents
Trench MOSFET and its process Download PDFInfo
- Publication number
- CN108258053A CN108258053A CN201810025143.6A CN201810025143A CN108258053A CN 108258053 A CN108258053 A CN 108258053A CN 201810025143 A CN201810025143 A CN 201810025143A CN 108258053 A CN108258053 A CN 108258053A
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- Prior art keywords
- layer
- groove
- polysilicon
- trench mosfet
- gate oxide
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910003978 SiClx Inorganic materials 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 238000000605 extraction Methods 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of trench MOSFET, the extension comprising a substrate and substrate, outer Yanzhong has multiple grooves, has dielectric layer in the groove and fills polysilicon, also has body implanted layer in epitaxial layer, epitaxial surface has borophosphosilicate glass layer；It is metal layer on borophosphosilicate glass layer；Also there is source implanted layer in the body implanted layer of source region trench region；Metal layer contacts extraction by contact hole with body implanted layer；The dielectric layer of middle and lower part is successively comprising the gate oxide, silicon nitride layer and silicon oxide layer for being close to substrate in the groove.Process of the present invention controls the height of channel bottom thickness grid to the selective etch of different film quality by time quarter of polysilicon and wet method, makes it have preferable homogeneity, is conducive to improve the performance of device.
Description
Technical field
The present invention relates to semiconductor devices and manufacturing fields, particularly relate to a kind of trench MOSFET, the invention further relates to
The process of the trench MOSFET.
Background technology
With the growth of electric consumers demand, the demand of power MOSFET is increasing, such as disk drive, automobile
Electronics and power device etc. etc..Groove-shaped M0S (Trench M0S) is since the integrated level of its device is higher, conducting resistance
It is relatively low, there is relatively low gate-drain charge density, larger current capacity, thus have relatively low switching loss and open faster
Speed is closed, is widely used in low pressure and low power field.
Existing manufacturing process, which is included in extension, carries out etching groove, then whole to deposit one layer of silica as thick grid
Oxide layer；Then ensure that channel bottom there are enough photoresist residues by photoresist and development step；Then silica is carried out
Wet etching gets rid of whole silica more than photoresist；Then the photoresist in removal groove.With reference to figure 1~4.Again
Carry out subsequent filling polysilicon.
There is the factors for restricting its performance for existing above-mentioned manufacturing process flow.Channel bottom thick grating oxide layer is to pass through
The exposure focal length and energy of development step control photoresist residue come what is realized, are coated in actual process by photoresist
With the influence of the fluctuation of step of exposure, the formation inhomogeneity of thick grid is frequently can lead to, so as to influence device performance.
Invention content
The technical problems to be solved by the invention are to provide a kind of trench MOSFET, the technology of the invention also to be solved
The problem still exists in the process for providing the trench MOSFET.
To solve the above problems, a kind of trench MOSFET of the present invention, comprising：
The extension of one substrate and substrate, outer Yanzhong have multiple grooves, have dielectric layer in the groove and fill
Polysilicon also has body implanted layer in epitaxial layer, and epitaxial surface has borophosphosilicate glass layer；It is gold on borophosphosilicate glass layer
Belong to layer；Also there is source implanted layer in the body implanted layer of source region trench region；Metal layer is contacted by contact hole with body implanted layer to be drawn
Go out.
The dielectric layer of middle and lower part is successively comprising the gate oxide, silicon nitride layer and oxidation for being close to substrate in the groove
Silicon layer.
The thickness of the gate oxide isThe thickness of silicon nitride layer isSilicon oxide layer
Thickness be
To solve the above problems, the process of trench MOSFET of the present invention, includes following processing step：
The first step forms extension on substrate, and hard mask is formed in extension, coats photoresist patterned, passes through photoresist
Define trench region；
Second step performs etching hard mask, and photoetching agent pattern is transferred on hard mask, removes photoresist；
Third walks, and extension is performed etching, and leads to the pattern of hard mask, groove is etched in outer Yanzhong；
4th step removes hard mask；
5th step deposits gate oxide, also gate oxide while covering groove inner surface in entire epitaxial surface；
6th step again in entire device surface deposit silicon nitride layer, is covered in gate oxide surface；
7th step, again entire device surface silicon oxide deposition layer；
8th step carries out first time polysilicon deposition and returns to carve in the trench；
9th step is sequentially etched silicon oxide layer, silicon nitride layer；
Tenth step carries out second of polysilicon deposition and returns to carve；
11st step carries out the injection of body implanted layer, source implanted layer, deposits boron-phosphorosilicate glass dielectric layer；Complete contact work
Skill.
Further, the 5th step, gate oxide use thermal oxidation method, and the gate oxide thickness of formation is
Further, the 6th step, the silicon nitride layer thickness of formation are
Further, the 7th step, the silicon oxide layer thickness of formation are
Further, the 8th step, polysilicon are returned in the middle part of ditch slot, retain the polysilicon of groove middle and lower part.
Further, the 9th step removes more than polysilicon upper surface silicon oxide layer and silicon nitride layer in groove.
Further, the tenth step, groove is interior to carry out second of polysilicon deposition and returns to carve, and makes polysilicon filling completely ditch
Slot.
Trench MOSFET of the present invention, the dielectric layer of channel bottom are divided into gate oxide, silicon nitride layer, oxidation
The sandwich composite construction of silicon layer.Process of the present invention is carved with wet method by returning for polysilicon to different film quality
Selective etch controls the height of channel bottom thickness grid, makes it have preferable homogeneity, is conducive to improve the performance of device.
Description of the drawings
Fig. 1~4 are the step schematic diagrames that traditional handicraft forms gate oxide.
Fig. 5~15 are present invention process step schematic diagrams.
Figure 16 is present invention process flow chart.
Reference sign
1 is substrate, and 2 be extension, and 3 be silicon nitride, and 4 be gate oxide, and 5 be contact hole injection region, and 6 be source implanted layer, and 7 are
Contact hole tungsten plug, 8 be silica, and 9 be polysilicon, and 10 be body implanted layer, and 11 be boron-phosphorosilicate glass dielectric layer, and 12 be metal layer,
13 be photoresist, and 14 be hard mask.
Specific embodiment
Trench MOSFET of the present invention, as shown in figure 15, comprising：
The extension 2 of one substrate 1 and substrate has multiple grooves in extension 2, has dielectric layer in the groove and fills out
Polysilicon 9 is filled, also there is body implanted layer 10 in epitaxial layer, 2 surface of extension has borophosphosilicate glass layer 11；Borophosphosilicate glass layer
It is metal layer 12 on 11；Also there is source implanted layer 6 in the body implanted layer 10 of source region trench region；Metal layer 12 passes through contact hole
Tungsten plug 7 contacts extraction with body implanted layer 10.
The dielectric layer of middle and lower part is successively comprising the gate oxide 4, silicon nitride layer 3 and oxygen for being close to substrate in the groove
SiClx layer 8.
The process of trench MOSFET of the present invention corresponds to reference chart 5~15 respectively, is walked comprising following technique
Suddenly：
The first step forms extension 2 on substrate 1, and hard mask 14 is formed in extension 2, and coating photoresist 13 is patterned, passed through
Photoresist defines trench region.As shown in Figure 5.
As shown in fig. 6, being performed etching to hard mask 14, photoetching agent pattern is transferred on hard mask for second step, removes light
Photoresist.
Third walks, and extension 2 is performed etching, and leads to the pattern of hard mask, groove is etched in outer Yanzhong.
4th step removes hard mask 14.
5th step, as shown in figure 9, depositing gate oxide 4, also gate oxide 4 while covering groove in entire epitaxial surface
Inner surface；Gate oxide 4 uses thermal oxidation method, and the gate oxide thickness of formation is
6th step is again in entire device surface deposition thicknessSilicon nitride layer 3, be covered in 4 table of gate oxide
Face.
7th step is again in entire device surface deposition thicknessSilicon oxide layer 8.
8th step as shown in figure 12, carries out first time polysilicon deposition and returns to carve, polysilicon is returned in ditch slot in the trench
Portion retains the polysilicon 9 of groove middle and lower part.
9th step is sequentially etched silicon oxide layer 8, silicon nitride layer 3, removes oxygen more than 9 upper surface of polysilicon in groove
SiClx layer 8 and silicon nitride layer 3, as shown in figure 13.
Tenth step carries out second of polysilicon deposition and returns to carve, and makes the full groove of polysilicon filling, as shown in figure 14.
11st step, carries out the injection of body implanted layer, source implanted layer, and deposit boron-phosphorosilicate glass dielectric layer 11 completes contact
7 grade routines subsequent technique of hole tungsten plug, it is as shown in figure 15 to ultimately form device.
Above-mentioned technique is compared with conventional method, main compound Jie improved in the 4th step to the 8th step, i.e. sandwich structure
The formation of matter layer, subsequent technique are essentially identical with traditional handicraft.
It these are only the preferred embodiment of the present invention, be not intended to limit the present invention.Those skilled in the art is come
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, it is any modification for being made, equivalent
Replace, improve etc., it should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of trench MOSFET, the extension comprising a substrate and substrate, outer Yanzhong have multiple grooves, the groove
It is interior that there is dielectric layer and fill polysilicon, also there is body implanted layer in epitaxial layer, epitaxial surface has borophosphosilicate glass layer；Boron
It is metal layer on phosphorosilicate glass layer；Also there is source implanted layer in the body implanted layer of source region trench region；Metal layer passes through contact
The contact of Kong Yuti implanted layers is drawn；
It is characterized in that：The dielectric layer of middle and lower part is successively comprising gate oxide, the silicon nitride layer for being close to substrate in the groove
And silicon oxide layer.
2. trench MOSFET as described in claim 1, it is characterised in that：The thickness of the gate oxide isThe thickness of silicon nitride layer isThe thickness of silicon oxide layer is
3. the process of manufacture trench MOSFET as described in claim 1, it is characterised in that：It is walked comprising following technique
Suddenly：
The first step forms extension on substrate, and hard mask is formed in extension, coats photoresist patterned, is defined by photoresist
Go out trench region；
Second step performs etching hard mask, and photoetching agent pattern is transferred on hard mask, removes photoresist；
Third walks, and extension is performed etching, and leads to the pattern of hard mask, groove is etched in outer Yanzhong；
4th step removes hard mask；
5th step deposits gate oxide, also gate oxide while covering groove inner surface in entire epitaxial surface；
6th step again in entire device surface deposit silicon nitride layer, is covered in gate oxide surface；
7th step, again entire device surface silicon oxide deposition layer；
8th step carries out first time polysilicon deposition and returns to carve in the trench；
9th step is sequentially etched silicon oxide layer, silicon nitride layer；
Tenth step carries out second of polysilicon deposition and returns to carve；
11st step carries out the injection of body implanted layer, source implanted layer, deposits boron-phosphorosilicate glass dielectric layer, completes contact process.
4. the process of trench MOSFET as claimed in claim 3, it is characterised in that：5th step, gate oxide
Using thermal oxidation method, the gate oxide thickness of formation is
5. the process of trench MOSFET as claimed in claim 3, it is characterised in that：6th step, the nitrogen of formation
SiClx layer thickness is
6. the process of trench MOSFET as claimed in claim 3, it is characterised in that：7th step, the oxygen of formation
SiClx layer thickness is
7. the process of trench MOSFET as claimed in claim 3, it is characterised in that：8th step, polysilicon return
In the middle part of ditch slot, retain the polysilicon of groove middle and lower part.
8. the process of trench MOSFET as claimed in claim 3, it is characterised in that：9th step removes groove
More than interior polysilicon upper surface silicon oxide layer and silicon nitride layer.
9. the process of trench MOSFET as claimed in claim 3, it is characterised in that：Tenth step, in groove into
Second of polysilicon deposition of row simultaneously returns quarter, makes the full groove of polysilicon filling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810025143.6A CN108258053A (en) | 2018-01-11 | 2018-01-11 | Trench MOSFET and its process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810025143.6A CN108258053A (en) | 2018-01-11 | 2018-01-11 | Trench MOSFET and its process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108258053A true CN108258053A (en) | 2018-07-06 |
Family
ID=62726055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810025143.6A Pending CN108258053A (en) | 2018-01-11 | 2018-01-11 | Trench MOSFET and its process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108258053A (en) |
-
2018
- 2018-01-11 CN CN201810025143.6A patent/CN108258053A/en active Pending
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Application publication date: 20180706 |
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