CN108257075B - Dereferencing and assembling method for vertex array command - Google Patents
Dereferencing and assembling method for vertex array command Download PDFInfo
- Publication number
- CN108257075B CN108257075B CN201711280984.3A CN201711280984A CN108257075B CN 108257075 B CN108257075 B CN 108257075B CN 201711280984 A CN201711280984 A CN 201711280984A CN 108257075 B CN108257075 B CN 108257075B
- Authority
- CN
- China
- Prior art keywords
- vertex
- attribute
- command
- dereferencing
- turning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
Abstract
The invention belongs to the field of computer graphics, and relates to a method for dereferencing and assembling vertex array commands, which comprises the following steps: step 1, initial state of vertex array assembly; step 2, judging the type of the vertex array command; step 3, dereferencing the single vertex group class; step 4, dereferencing the multi-vertex group class; step 5, obtaining an attribute index address; step 6, calculating the storage address of the effective attribute; step 7, obtaining single-vertex effective attribute data; step 8, supporting the assembly of the attribute array with local disorder; 9, issuing a single-vertex effective attribute drawing command; step 10, completing a single vertex attribute command; step 11, inquiring the number of vertexes carried by the multi-vertex array command; step 12, completing a multi-vertex array command; and step 13, dereferencing and assembling the vertex array.
Description
Technical Field
The invention belongs to the field of computer graphics, and relates to a method for dereferencing and assembling vertex array commands.
Background
In the graphics processor, before the 3D engine receives the vertex group command, the 3D engine needs to perform dereferencing and assembling of the command, assembles the command into an agreed packet header and a format of each component attribute data, and then issues the packet header and the format into the 3D engine to execute a graphics drawing process, so that a simple and efficient vertex group command dereferencing and assembling mechanism has important influence on the graphics drawing efficiency of the graphics processor. The currently disclosed research is mostly directed to the research of the unified stainer kernel and the graphics processing algorithm, and no research on the dereferencing and assembling method of the vertex array command is found.
Disclosure of Invention
The purpose of the invention is:
the invention mainly provides a dereferencing and assembling method of vertex array commands, which is beneficial to reducing the number of graphics application programs, reducing the transmission number of graphics commands of a host and improving the graphics drawing efficiency.
The solution of the invention is:
a method for dereferencing and assembling vertex array commands, comprising:
step 2, judging the type of the vertex array command, judging that the current command needs to draw a single vertex and attribute information thereof or at least two vertexes and attributes according to the input command code, if the current command needs to draw a single vertex and attribute information thereof, turning to step 3, and if the current command does not need to draw a single vertex and attribute information thereof, turning to step 4;
step 3, dereferencing the single-vertex array class, dereferencing the packet head parts of at least two effective attribute drawing commands of a single vertex according to the input configuration information, and turning to step 6 if dereferencing is finished;
step 4, dereferencing the multi-vertex groups, dereferencing the packet head parts of at least two vertexes which have at least two effective attribute drawing commands according to the input configuration information, and turning to step 5 if dereferencing is completed;
step 5, acquiring an attribute index address, acquiring at least two vertex array commands from a defined storage space according to input configuration information, calculating the attribute index address required by each vertex in the vertex array commands, and turning to step 6 if an effective index address is acquired;
step 6, calculating the storage addresses of the effective attributes, calculating the storage address information of each effective attribute acquired from the defined attribute array according to the input configuration information, and turning to step 7 if the calculation is finished;
step 7, acquiring single-vertex effective attribute data, acquiring and caching each effective attribute data according to the storage address of each effective attribute, and then turning to step 8;
step 9, issuing a single-vertex effective attribute drawing command, counting and identifying attribute data assembly and issuing information of the same vertex, and turning to step 10 when all effective attributes of the same vertex are completely assembled and issued;
step 10, completing the single-vertex attribute command, if the single-vertex attribute command is a single-vertex array type command, turning to step 13, identifying that dereferencing and assembling of the single-vertex array are completed, and if the single-vertex attribute command is a multi-vertex array type command, turning to step 11;
step 11, inquiring the vertex number carried by the multi-vertex array command, inquiring whether the vertex needing to be drawn and the effective attribute thereof carried by the current command are acquired, cached, assembled and issued, if the vertex is not drawn, turning to step 5 to acquire an attribute index address, and if the assembly and the issue of all the current vertices are finished, turning to step 12;
step 12, completing the multi-vertex array command, identifying that the dereferencing and assembling of all vertex arrays carried by the command are completed, and turning to step 13;
and step 13, completing dereferencing and assembling of the vertex array, completing dereferencing and assembling processes of the identification vertex array class command, and turning to step 1.
The invention has the beneficial effects that: the method realizes the dereferencing and assembling of the input vertex group commands, and simultaneously uses the assembling method of local disorder and global sequence, thereby effectively improving the dereferencing and assembling efficiency of the commands, being beneficial to reducing the number of graphic application programs, reducing the transmission number of the graphic commands of the host and improving the graphic drawing efficiency.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1, a method for dereferencing and assembling vertex array commands,
step 2, judging the type of the vertex array command, judging that the current command needs to draw a single vertex and attribute information thereof or at least two vertexes and attributes according to the input command code, if the current command needs to draw a single vertex and attribute information thereof, turning to step 3, and if the current command does not need to draw a single vertex and attribute information thereof, turning to step 4;
step 3, dereferencing the single-vertex array class, dereferencing the packet head parts of at least two effective attribute drawing commands of a single vertex according to the input configuration information, and turning to step 6 if dereferencing is finished;
step 4, dereferencing the multi-vertex groups, dereferencing the packet head parts of at least two vertexes which have at least two effective attribute drawing commands according to the input configuration information, and turning to step 5 if dereferencing is completed;
step 5, acquiring an attribute index address, acquiring at least two vertex array commands from a defined storage space according to input configuration information, calculating the attribute index address required by each vertex in the vertex array commands, and turning to step 6 if an effective index address is acquired;
step 6, calculating the storage addresses of the effective attributes, calculating the storage address information of each effective attribute acquired from the defined attribute array according to the input configuration information, and turning to step 7 if the calculation is finished;
step 7, acquiring single-vertex effective attribute data, acquiring and caching each effective attribute data according to the storage address of each effective attribute, and then turning to step 8;
step 9, issuing a single-vertex effective attribute drawing command, counting and identifying attribute data assembly and issuing information of the same vertex, and turning to step 10 when all effective attributes of the same vertex are completely assembled and issued;
step 10, completing the single-vertex attribute command, if the single-vertex attribute command is a single-vertex array type command, turning to step 13, identifying that dereferencing and assembling of the single-vertex array are completed, and if the single-vertex attribute command is a multi-vertex array type command, turning to step 11;
step 11, inquiring the vertex number carried by the multi-vertex array command, inquiring whether the vertex needing to be drawn and the effective attribute thereof carried by the current command are acquired, cached, assembled and issued, if the vertex is not drawn, turning to step 5 to acquire an attribute index address, and if the assembly and the issue of all the current vertices are finished, turning to step 12;
step 12, completing the multi-vertex array command, identifying that the dereferencing and assembling of all vertex arrays carried by the command are completed, and turning to step 13;
and step 13, completing dereferencing and assembling of the vertex array, completing dereferencing and assembling processes of the identification vertex array class command, and turning to step 1.
Claims (1)
1. A method for dereferencing and assembling vertex array commands,
step 1, monitoring whether effective vertex array class command input is received or not in an initial state of vertex array assembly, and if the input command is effective, turning to step 2;
step 2, judging the type of the vertex array command, judging that the current command needs to draw a single vertex and attribute information thereof or at least two vertexes and attributes according to the input command code, if the current command needs to draw a single vertex and attribute information thereof, turning to step 3, and if the current command does not need to draw a single vertex and attribute information thereof, turning to step 4;
step 3, dereferencing the single-vertex array class, dereferencing the packet head parts of at least two effective attribute drawing commands of a single vertex according to the input configuration information, and turning to step 6 if dereferencing is finished;
step 4, dereferencing the multi-vertex groups, dereferencing the packet head parts of at least two vertexes which have at least two effective attribute drawing commands according to the input configuration information, and turning to step 5 if dereferencing is completed;
step 5, acquiring an attribute index address, acquiring at least two vertex array commands from a defined storage space according to input configuration information, calculating the attribute index address required by each vertex in the vertex array commands, and turning to step 6 if an effective index address is acquired;
step 6, calculating the storage addresses of the effective attributes, calculating the storage address information of each effective attribute acquired from the defined attribute array according to the input configuration information, and turning to step 7 if the calculation is finished;
step 7, acquiring single-vertex effective attribute data, acquiring and caching each effective attribute data according to the storage address of each effective attribute, and then turning to step 8;
step 8, supporting the assembly of the attribute array of the local disorder, assembling the obtained effective attribute data into an agreed packet header and each component attribute data format, in the assembly process, except for representing the attributes of the vertex coordinates, other attributes belonging to the same vertex can be assembled in a disorder manner but are only limited to the local disorder, the order is still maintained among the attributes belonging to different vertices, and the step 9 is switched to after the assembly is finished;
step 9, issuing a single-vertex effective attribute drawing command, counting and identifying attribute data assembly and issuing information of the same vertex, and turning to step 10 when all effective attributes of the same vertex are completely assembled and issued;
step 10, completing the single-vertex attribute command, if the single-vertex attribute command is a single-vertex array type command, turning to step 13, identifying that dereferencing and assembling of the single-vertex array are completed, and if the single-vertex attribute command is a multi-vertex array type command, turning to step 11;
step 11, inquiring the vertex number carried by the multi-vertex array command, inquiring whether the vertex needing to be drawn and the effective attribute thereof carried by the current command are acquired, cached, assembled and issued, if the vertex is not drawn, turning to step 5 to acquire an attribute index address, and if the assembly and the issue of all the current vertices are finished, turning to step 12;
step 12, completing the multi-vertex array command, identifying that the dereferencing and assembling of all vertex arrays carried by the command are completed, and turning to step 13;
and step 13, completing dereferencing and assembling of the vertex array, completing dereferencing and assembling processes of the identification vertex array class command, and turning to step 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201711280984.3A CN108257075B (en) | 2017-12-06 | 2017-12-06 | Dereferencing and assembling method for vertex array command |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201711280984.3A CN108257075B (en) | 2017-12-06 | 2017-12-06 | Dereferencing and assembling method for vertex array command |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108257075A CN108257075A (en) | 2018-07-06 |
CN108257075B true CN108257075B (en) | 2021-07-16 |
Family
ID=62721102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711280984.3A Active CN108257075B (en) | 2017-12-06 | 2017-12-06 | Dereferencing and assembling method for vertex array command |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN108257075B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111047503B (en) * | 2019-11-21 | 2023-06-13 | 中国航空工业集团公司西安航空计算技术研究所 | Attribute storage and assembly optimization circuit of vertex array class command |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102708537A (en) * | 2011-03-03 | 2012-10-03 | Arm有限公司 | Graphics processing |
CN103279974A (en) * | 2013-05-15 | 2013-09-04 | 中国科学院软件研究所 | High-accuracy high-resolution satellite imaging simulation engine and implementation method |
CN103700143A (en) * | 2013-12-30 | 2014-04-02 | 四川九洲电器集团有限责任公司 | Three-dimensional dynamic marine simulation method based on GPU (Graphics Processing Unit) multi-pass drawing |
CN105427353A (en) * | 2015-11-12 | 2016-03-23 | 小米科技有限责任公司 | Compression and drawing method and device of scalable vector graphic |
CN106651744A (en) * | 2016-12-12 | 2017-05-10 | 中国航空工业集团公司西安航空计算技术研究所 | Low power consumption GPU (Graphic Process Unit) staining task and uniform staining array task field mapping structure |
-
2017
- 2017-12-06 CN CN201711280984.3A patent/CN108257075B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102708537A (en) * | 2011-03-03 | 2012-10-03 | Arm有限公司 | Graphics processing |
CN103279974A (en) * | 2013-05-15 | 2013-09-04 | 中国科学院软件研究所 | High-accuracy high-resolution satellite imaging simulation engine and implementation method |
CN103700143A (en) * | 2013-12-30 | 2014-04-02 | 四川九洲电器集团有限责任公司 | Three-dimensional dynamic marine simulation method based on GPU (Graphics Processing Unit) multi-pass drawing |
CN105427353A (en) * | 2015-11-12 | 2016-03-23 | 小米科技有限责任公司 | Compression and drawing method and device of scalable vector graphic |
CN106651744A (en) * | 2016-12-12 | 2017-05-10 | 中国航空工业集团公司西安航空计算技术研究所 | Low power consumption GPU (Graphic Process Unit) staining task and uniform staining array task field mapping structure |
Non-Patent Citations (1)
Title |
---|
朱豪杰等."GPU命令处理器的存储管理单元设计".《西安邮电大学学报》.2013,第18卷(第1期), * |
Also Published As
Publication number | Publication date |
---|---|
CN108257075A (en) | 2018-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11656845B2 (en) | Dot product calculators and methods of operating the same | |
CN106874459B (en) | Streaming data storage method and device | |
US9928645B2 (en) | Raster-based mesh decimation | |
EP3483838A3 (en) | Systems and methods for rendering with ray tracing | |
CN108520489B (en) | Device and method for realizing command analysis and vertex acquisition parallel in GPU | |
CN103744935A (en) | Rapid mass data cluster processing method for computer | |
CN111047596A (en) | Three-dimensional point cloud instance segmentation method and system and electronic equipment | |
CN104267940A (en) | Quick map tile generation method based on CPU+GPU | |
CN104317899A (en) | Big-data analyzing and processing system and access method | |
CN105574808A (en) | Stream line texture mapping unit system structure | |
CN108257075B (en) | Dereferencing and assembling method for vertex array command | |
CN107945099B (en) | OpenGL-oriented attribute configuration optimization method | |
CN111737564A (en) | Information query method, device, equipment and medium | |
Stojanovic et al. | High performance processing and analysis of geospatial data using CUDA on GPU | |
CN105574917A (en) | Normal map reconstruction processing system and method for 3D models | |
CN104571946A (en) | Memory device supporting quick query of logical circuit and access method of memory device | |
CN108319604B (en) | Optimization method for association of large and small tables in hive | |
CN108345648B (en) | Method and device for acquiring log information based on columnar storage | |
CN106990913B (en) | A kind of distributed approach of extensive streaming collective data | |
CN116543134A (en) | Method, device, computer equipment and medium for constructing digital twin model | |
CN102495710B (en) | Method for processing data read-only accessing request | |
CN108122190B (en) | GPU unified dyeing array vertex dyeing task attribute data assembling method | |
CN110019448B (en) | Data interaction method and device | |
CN111062856B (en) | Optimized OpenGL graphic attribute arrangement method | |
CN104616332A (en) | Fast display method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |