CN108243003B

CN108243003B - Method for generating a data set on an integrated circuit, integrated circuit and method for manufacturing the same

Info

Publication number: CN108243003B
Application number: CN201710192398.7A
Authority: CN
Inventors: 曾柏皓; 许凯捷; 李峰旻; 林昱佑
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2016-12-27
Filing date: 2017-03-28
Publication date: 2020-10-20
Anticipated expiration: 2037-03-28
Also published as: TWI616885B; TW201824282A; CN108241807A; CN108241807B; CN108243003A; TW201835921A; TWI640005B

Abstract

A method of generating a data set on an integrated circuit including programmable resistive memory cells includes applying forming pulses to all members of a set of programmable resistive memory cells. The forming pulse has a forming pulse level characterized in that a resistance change from an initial resistance range to an intermediate resistance range is induced in a first subset of the set, while a second subset of the set has a resistance that falls outside the intermediate range after the forming pulse. The method includes applying programming pulses to the first subset and the second subset. The programming pulse has a programming pulse level characterized by inducing a resistance change of the first subset from the intermediate range to a first final range, and after the programming pulse, the second subset has a resistance in a second final range, the first subset and the second subset thereby storing the data set.

Description

Method for generating a data set on an integrated circuit, integrated circuit and method for manufacturing the same

Technical Field

The invention relates to an integrated circuit device having a data set (data set) generated using a physically unclonable function, and a method for generating such a data set.

Background

A Physical Unclonable Function (PUF) is a process that can be used to create a unique, random key for a physical entity, such as an integrated circuit. The use of PUFs is a solution to generate Identifiers (IDs) that support Hardware Intrinsic Security (HIS) technology. PUFs have been used in key creation for applications with high security requirements, such as portable and embedded devices. One example PUF is a ring oscillator PUF that uses manufacturing variability inherent to the circuit conduction delay of the gate. Another example PUF is a Static Random Access Memory (SRAM) PUF, in which the threshold voltages in the transistors are different so that the SRAM power is turned on at a logic "0" or a logic "1".

It is desirable to provide a physically unclonable function for creating data sets in a programmable resistive memory with low bit error rate and high reliability under process, voltage, temperature (PVT) conditions.

Disclosure of Invention

A method of generating a data set on an integrated circuit including a plurality of programmable resistive memory cells is provided.

The method includes applying a forming pulse (forming pulse) to all members of a set of the programmable resistive memory cells. The forming pulse has a forming pulse level characterized by inducing a resistance change from an initial resistance range to an intermediate resistance range in a first subset of the set of programmable resistive memory cells, and a second subset of the set of programmable resistive memory cells having a resistance that falls outside the intermediate range after the forming pulse. Membership in the first subset and the second subset is determined by a physical change in response to the formed pulse across the set.

The method includes applying a programming pulse to the first subset and the second subset of programmable resistive memory cells. The programming pulse has a programming pulse level characterized by inducing a first subset of resistance changes from the intermediate range to a first final resistance range. The programming pulse can cause the distribution of memory cells in the first and second subsets of a given set of programmable resistive memory cells to be more stable under a harsh environmental condition. In the embodiments described herein, the programming pulse can cause an increase in the sensing margin (margin) between the memory cells in the first subset and the memory cells in the second subset. After the programming pulse, the memory cells in the second subset of programmable resistive memory cells can be maintained in a resistance range that is close to the initial resistance range, and otherwise have a resistance in a second final resistance range that does not overlap the first final resistance range. The first and second subsets of the set of programmable memory cells, created by the combination of the forming pulse and the programming pulse, will vary according to the variations of the programmable resistive memory cells naturally caused by the natural properties of the material and the manufacturing process.

The method can include finding a forming pulse level by testing some of the programmable resistive memory cells on an integrated circuit prior to applying the forming pulse.

To find the forming pulse level, a test pulse having a test pulse level can be applied in an iterative manner to the programmable resistive memory cells on the same integrated circuit and preferably having the same structure as the memory cell bits to be used in creating the unique data set. For each iteration, a test set of programmable resistive memory cells different from the previously used test set can be used. A proportion of the memory cells in the test set having resistances in the intermediate resistance range can be determined. If the ratio is below a threshold, the test pulse level can then be updated, the operations of applying the test pulse and determining the ratio repeated until the determined ratio reaches the threshold, or more preferably falls within a specified range of about 50% (e.g., 40% to 60%), and the forming pulse level can be set based on the test pulse level in iterations that reach the threshold or fall within the specified range.

The data set can be used to form a response to a challenge (challenge), for example in the case of a security protocol. A method of using a data set includes sensing all or a portion of the data set using a read voltage for a resistance between a first final resistance range and a second final resistance range, wherein the first final resistance range and the second final resistance range are separated by a read limit. As mentioned previously, the read limit can be greater than the limit between the initial resistance range and the intermediate range.

The programmable resistive memory cell can include a plurality of programmable resistive memory elements. In one embodiment, the programmable resistive memory element can be characterized by an initial resistance in a high resistance range, wherein the intermediate resistance range is lower than the high resistance range, a first final resistance range is lower than the intermediate resistance range, and a second final resistance range is higher than the first final resistance range.

In another embodiment, the programmable resistive memory element can feature an initial resistance in a low resistance range, wherein the intermediate resistance range is higher than the low resistance range, the first final resistance range is higher than the intermediate resistance range, and the second final resistance range is lower than the first final resistance range.

Applying a forming pulse as described herein enables the formation of a conductive filament connecting the first and second electrodes of the memory cells in the first subset, and does not enable the formation of a conductive filament connecting the first and second electrodes of the memory cells in the second subset.

The programming pulse as described herein stabilizes and enhances the conductivity of the conductive filament of the memory cell in the first subset without causing a conductive filament of the memory cell in the second subset to form.

There is also provided a method of manufacturing an integrated circuit according to the method for generating a data set provided herein.

Also described is an apparatus comprising an integrated circuit having a memory that uses the PUF to create and store a unique data set. The apparatus in this aspect of the technology includes a controller configured to execute the PUF. The controller can comprise a state machine on the same integrated circuit as the memory, logic such as a computer program on a separate system that can be placed in communication with the memory or a combination of on-chip and off-chip logic.

Other aspects and advantages of the invention will become apparent from the following drawings and detailed description.

Drawings

Figure 1 is a simplified block diagram of a device including an integrated circuit having a memory that uses a PUF to create and store a unique data set.

FIG. 2 illustrates an exemplary flow chart for generating a data set on an integrated circuit including programmable resistive memory cells.

FIG. 3 illustrates an exemplary flow chart for finding a forming pulse level.

FIG. 4 depicts an example system for executing a physically unclonable function on an integrated circuit.

FIG. 5 shows a conductive filament and a non-conductive filament in a programmable resistive memory cell.

Fig. 6A and 6B illustrate resistance ranges in an operation to generate a data set.

7A, 7B, and 7C show probability plots of the resistance of a memory cell at various stages of a PUF process as described herein.

FIG. 8 shows different conditions for finding a forming pulse level.

FIGS. 9-13 illustrate operations for finding a forming pulse level.

FIG. 14 shows exemplary results of applying test pulses in a test set.

Fig. 15A and 15B illustrate the results of generating a first data set in a first PUF ID array and a second data set in a second PUF ID array.

FIG. 16 illustrates a read limit under high temperature bake conditions between the exemplary first and second final resistance ranges.

[ description of reference ]

100. 440, a step of: integrated circuit with a plurality of transistors

110: task function circuit

111. 116, 131, 141: bus line

115: question-asking control block

120: input/output interface

122: wiring

125: security logic

130: memory array

140: controller

210. 220, 230, 310, 320, 330, 340, 350: step (ii) of

410: system for controlling a power supply

420: PUF logic and driver

430: device handler/prober

500: memory cell

510: metal oxide memory element

610. 610b, 620b, 630b, 640b, 650b, 710, 720, 730, 740, 750, 940, 950, 1040, 1050, 1140, 1150, 1240, 1250, 1340, 1350, 1640, 1650, 1670: range of

705. 905: threshold value of resistance

725: limit of

745. 1660: read margin

Detailed Description

A detailed description of embodiments of the present technology is provided with reference to the accompanying drawings. It should be understood that there is no intention to limit the technology to the specifically disclosed structural embodiments and methods, but that the technology may be practiced using other features, elements, methods, and embodiments. The description of the preferred embodiments is intended to be illustrative of the technology and is not intended to limit the scope of the technology as defined by the claims. Those skilled in the art to which the invention pertains will recognize various equivalent variations to those set forth below. Like elements in the various embodiments are generally indicated by like reference numerals.

Fig. 1 is a simplified block diagram of an apparatus including a plurality of programmable resistive memory cells and a controller for executing a PUF to store a data set in the programmable resistive memory cells. In this example, the apparatus includes an integrated circuit 100 having a memory formed using programmable resistive memory cells that is programmed using PUF to create and store a unique data set that can be used, for example, as a unique chip ID, a key for an authentication or encryption protocol, or other type of secret or unique data value.

The integrated circuit 100 contains a mission function circuit (mission function circuit)110, which can include special purpose logic (sometimes referred to as application specific integrated circuit logic), data processor resources (such as used in microprocessors and digital signal processors), bulk memory (such as flash memory, Dynamic Random Access Memory (DRAM), programmable resistive memory), and a combination of various different types of circuits called a system-on-chip configuration. Integrated circuit 100 includes an input/output interface 120 that can include a wireless or wired port to provide access to other devices or networks. In this simplified illustration, an access control block 115 is provided between the input/output interface 120 and the task function circuitry 110. Access control block 115 is coupled to input/output interface 120 by bus 116 and to task function circuitry 110 by bus 111. An access control protocol is executed by the access control block 115 to enable or disable communication between the task function circuitry 110 and the input/output interface 120.

The security logic 125 is provided on-chip in this example, with the support of the access control block 115. The security logic 125 is coupled to a PUF programmed memory array 130 that stores a unique data set after execution of the PUF. The unique data set is accessible on bus 131 alongside security logic 125 via a PUF programming controller 140 and is used by the security logic in communication with access control block 115 across trace 122.

The PUF programmed memory array 130 includes programmable resistive memory cells that include programmable elements having a programmable resistance. The programmable element can comprise a metal oxide, such as tungsten oxide (WO)_x) Hafnium oxide (HfO)_x) Titanium oxide (TiO)_x) Tantalum oxide (TaO)_x) Titanium oxynitride (TiNO), nickel oxide (NiO)_x) Ytterbium oxide (YbO)_x) Aluminum oxide (AlO)_x) Niobium oxide (NbO)_x) Zinc oxide (ZnO)_x) Copper oxide (CuO)_x) Vanadium Oxide (VO)_x) Molybdenum oxide (MoO)_x) Ruthenium oxide (RuO)_x) Copper silicon oxide (CuSiO)_x) Silver zirconium oxide (AgZrO), aluminum nickel oxide (AlNiO), aluminum titanium oxide (AlTiO), gadolinium oxide (GdO)_x) Gallium oxide (GaO)_x) Zirconium oxide (ZrO)_x) Chromium doped SrZrO₃Chromium doped SrTiO₃PCMO, or LaCaMnO, and the like. In some cases, the programmable element of the memory cell can be a semiconductor oxide, such as silicon oxide (SiO)_x)。

In this example of a device, the PUF programming controller 140 is implemented as, for example, a state machine located on an integrated circuit having the programmable resistive memory cells, and the PUF programming controller 140 provides signals to control the application of the bias arrangement to provide voltages to perform PUF programming and other operations involving accessing the PUF programmed memory array 130 for a PUF and for reading a data set stored in the PUF programmed memory array 130. The controller 140 can be implemented using special purpose logic circuitry as is known in the art. In an alternative embodiment, the controller 140 comprises a general purpose processor, capable of being implemented on the same integrated circuit that executes a computer program to control the operation of the device. In yet other embodiments, a combination of special purpose logic circuitry and a general purpose processor can be used to implement controller 140.

In one embodiment, an apparatus includes an off-chip system (e.g., 410 in FIG. 4) and an integrated circuit (e.g., 440 in FIG. 4, 100 in FIG. 1). An off-chip system is used to control the execution of physically unclonable functions on an integrated circuit. For example, the off-chip system can operate a PUF programming controller (e.g., 140 in fig. 1) on the integrated circuit to perform some of all operations in applying the forming pulses, applying the programming pulses, and finding the forming pulse level. For example, the system can communicate a resistance threshold to the integrated circuit, which can be used to determine a forming pulse level. For example, the system can communicate a forming pulse level to the integrated circuit, which can be used in applying the forming pulse. For example, the system can generate a test set of memory cells for use in a memory array in an integrated circuit for use in finding the addresses that form the pulse level and communicating the addresses to an integrated circuit coupled to the system. In another embodiment, the PUF programming controller 140 on the integrated circuit contains all the logic necessary to apply the forming and programming pulses, and to find the forming pulse level. In this embodiment, PUF programming controller 140 is capable of executing logic in response to set commands from an external source without the control of the system for executing physically unclonable functions on an integrated circuit.

PUF programming controller 140 is configured to apply a forming pulse to all members of a set of programmable resistive memory cells in PUF programmed memory array 130 via a bus 141. The forming pulse has a forming pulse level characterized by inducing a resistance change from an initial resistance range to an intermediate resistance range in a first subset of the set of memory cells, and a second subset of the set of programmable resistive memory cells having resistances outside the intermediate range after the forming pulse.

PUF programming controller 140 is configured to apply a programming pulse to the first and second subsets of programmable resistive memory cells. The programming pulse has a programming pulse level characterized by inducing a first subset of resistance changes from the intermediate resistance range to a first final resistance range. The programming pulse can cause the sensing margin between the memory cells in the first subset and the memory cells in the second subset to increase. After the programming pulse, the memory cells in the second subset of programmable resistive memory cells can be maintained in a resistance range that is close to the initial resistance range, and otherwise have a resistance in a second final resistance range that does not overlap the first final resistance range. The first and second subsets of the set of programmable memory cells, created by the combination of the forming pulse and the programming pulse, will vary according to the variations of the programmable resistive memory cells naturally caused by the natural properties of the material and the manufacturing process.

The PUF programming controller 140 can be configured to find a forming pulse level by testing some of the programmable resistive memory cells on the integrated circuit before applying the forming pulse. The programmable resistive memory cells under test can be in a test set of the PUF programmed memory array 130. The test set of programmable resistive memory cells is on the same integrated circuit as the memory cell bits to be used in creating the unique data set. The test set can be placed in a block of memory cells in the PUF programmed memory array 130, or in a distributed location in the PUF programmed memory array 130, or elsewhere on the device. In some embodiments, the test set is part of the PUF programmed memory array 130, or is located adjacent to the memory array 130, and is formed using the same process as used to form the PUF circuit, such that they can be used to predict the behavior of the PUF circuit in response to the formation and programming processes described herein.

To find the forming pulse level, the PUF programming controller 140 can be configured to iteratively apply a test pulse having a test pulse level to a test set of a plurality of test sets of programmable resistive memory cells on the same integrated circuit and determine a proportion of memory cells in the test set having resistances in the intermediate resistance range, and, if the proportion is below a threshold, then update the test pulse level, repeat the operations of applying the test pulse and determining the proportion until the determined proportion reaches the threshold, and set the forming pulse level based on the test pulse level in the iteration that reached the threshold. For each iteration, a test set of programmable resistive memory cells different from the previously used test set can be used.

The PUF programming controller 140 can be configured to sense all or a portion of a data set in the programmed memory array 130 via the security circuit (e.g., 125 in fig. 1) using a read voltage that is used at a resistance between a first final resistance range and a second final resistance range, where the first range and the second range are separated by a read limit that is greater than a limit between the initial resistance range and the intermediate range.

The programmable resistive memory cell can include a programmable resistive memory element. In one embodiment, the programmable resistive memory element can be characterized by an initial resistance in a high resistance range, wherein the intermediate resistance range is lower than the high resistance range, a first final resistance range is lower than the intermediate resistance range, and a second final resistance range is higher than the first final resistance range.

FIG. 2 illustrates an exemplary flow chart for generating a data set on an integrated circuit including programmable resistive memory cells. In step 210, a forming pulse level is found by testing some of the programmable resistive memory cells on the integrated circuit. This step is further described with reference to fig. 3. In step 220, a forming pulse is applied to a set of programmable resistive memory cells on the integrated circuit. The forming pulse has the forming pulse level found at step 210. The forming pulse level is characterized by inducing a resistance change from an initial resistance range to an intermediate resistance range in a first subset of the set of memory cells, and a second subset of the set of programmable resistive memory cells having resistances outside the intermediate range after the forming pulse. For example, for a WO-based resistor having an initial resistance in a high resistance range_x(tungsten oxide) programmable resistive memory, an initial resistance range can be between about 2700kohm (kilo-ohm) and 3000kohm (FIG. 7A), and an intermediate resistance range can be at a threshold level of about 400kohmIn a range below, and which may be, for example, between about 100kohm and 400kohm (fig. 7B), a resistance of the second subset that falls outside of the intermediate range after the pulse is formed can be in a range that overlaps with the initial resistance range, otherwise maintained at a resistance above the intermediate resistance range. For example, the second subset can have a resistance above a threshold level of about 2700 kohm.

At step 230, a programming pulse is applied to the first and second subsets of programmable resistive memory cells that increases the read margin between the memory cells in the first subset and the memory cells in the second subset. The programming pulse has a programming pulse level characterized by inducing resistance changes in the first subset from the intermediate range to below a threshold level in the resistances of a first final resistance range. The programming pulse can cause the sensing margin between the memory cells in the first subset and the memory cells in the second subset to increase. After the programming pulse, the memory cells in the second subset of programmable resistive memory cells are able to remain in a resistance range, e.g., near the initial resistance range, above a threshold level that is much greater than the maximum level of the first final resistance range, and otherwise have resistances in a second final resistance range that does not overlap the first final resistance range. The first and second subsets of the set of programmable memory cells, created by the combination of the forming pulse and the programming pulse, will vary according to the variations of the programmable resistive memory cells naturally caused by the natural properties of the material and the manufacturing process. For example, for a WO-based resistor having an initial resistance in a high resistance range_xFor programmable resistive memory (fig. 7C) (tungsten oxide), a first final resistance range can be between about 0kohm and 100kohm, and a second final resistance range can be between about 2700kohm and 3000 kohm. The first final resistance range is separated from the second final resistance range by a read limit 745 that is greater than a limit 725 between the initial resistance range and the intermediate resistance range as shown and described with reference to fig. 7B and 7C.

Fig. 3 illustrates an exemplary flow chart for finding a forming pulse level, corresponding to step 210 in fig. 2. In step 310, a test pulse having a test pulse level is applied to a new test set of programmable resistive memory cells. The test set has a size smaller than the set of programmable resistive memory cells. For example, the test set can have a size of 64 bits, while the set can have a size of 1000 bits. The test set can be in a PUF programmed storage array (e.g., 130 in fig. 1). For each iteration, a new test set is used. As used herein, a programmable resistive memory cell in a new test set integrated circuit is different from a test set of any previously used test sets. Multiple test sets may be available on an integrated circuit, such as PUF programmed memory array 130 (fig. 1), for the purpose of finding a level to form a pulse. At step 320, a proportion of memory cells in the test set having resistances in the intermediate resistance range is determined.

If the ratio is below a threshold (e.g., 40% to 50%) at step 330, then the test pulse level is updated at step 340 and the test pulse applying step 310 and the ratio determining step 320 are repeated until the determined ratio reaches the threshold. In repeating

steps

310 and 320, a new test set is used. A new test set is used for each iteration in finding the forming pulse level, so that the forming pulse level can be decided using a different test set in the initial resistance range to be used with the set of programmable resistive memory cells in the same initial resistance range. A range of proportions of memory cells in different test sets having resistances in the intermediate resistance range can be determined corresponding to the updated test pulse levels. For example, for a WO-based resistor having an initial resistance in a high resistance range_x(tungsten oxide) programmable resistive memory (figures 9-13) having a range between 8% and 90% for updated test pulse levels corresponding to different word line voltages and bit line voltages applied to individual test sets, the proportion of memory cells in different test sets having resistances in the intermediate resistance range.

At step 350, a forming pulse level is set based on the test pulse level in the iteration that reaches the threshold.

Steps

310, 320, 330, 340, and 350 can be performed by PUF programming controller 140 as described with reference to integrated circuit 100 shown in fig. 1. The forming pulse level can be based on a particular test pulse level used at a particular iteration, the result of which is a proportion closer to the threshold value than other proportions in the range of proportions of memory cells having resistances in the intermediate resistance range in different test sets. For example, if the threshold is 50%, the forming pulse level can be based on the test pulse level in an iteration that results in 53% of the memory cells having resistances in the intermediate resistance range (fig. 11).

The processes of fig. 2 and 3 can be part of a process for manufacturing an integrated circuit that includes forming a plurality of programmable resistive memory cells on the integrated circuit, connecting the integrated circuit to a system configured to apply a physically unclonable function to the programmable resistive memory cells on the integrated circuit, and using the system to generate a data set in a set of programmable resistive memory cells in the programmable resistive memory cells by the processes described herein. One example of the inclusion of forming a plurality of programmable resistive memory cells in many known manufacturing processes in the art to which the present invention pertains is shown in U.S. patent application publication No. US 2016/0218146, entitled "RRAM PROCESS WITH roughhnesslingtestingtechrology," to Lee et al, which is incorporated herein by reference as if fully set forth herein.

FIG. 4 illustrates an example system for performing a physically unclonable function on an integrated circuit. A plurality of programmable resistive memory cells are formed on an integrated circuit. The integrated circuit is coupled to a system configured to apply a physical unclonable function to programmable resistive memory cells on the integrated circuit. With the system, a data set can be generated in a set of programmable resistive memory cells of the programmable resistive memory cells. The system can use, for example, the methods described with reference to the flow diagrams of fig. 2 and 3.

The method used by the system can include applying a forming pulse to all members of the set, wherein the forming pulse has a forming pulse level characterized by inducing a resistance change from an initial resistance range to an intermediate resistance range in a first subset of the set of programmable resistive memory cells, and a second subset of the set of programmable resistive memory cells having a resistance that falls outside the intermediate range after the forming pulse.

The method used by the system can include applying a programming pulse to the first subset and the second subset of programmable resistive memory cells, wherein the programming pulse has a programming pulse level characterized by causing a resistance change in the first subset from the intermediate resistance range to a first final resistance range. The programming pulse can cause the sensing margin between the memory cells in the first subset and the memory cells in the second subset to increase. After the programming pulse, the memory cells in the second subset of programmable resistive memory cells can be maintained in a resistance range that is close to the initial resistance range, and otherwise have a resistance in a second final resistance range that does not overlap the first final resistance range. The first and second subsets of the set of programmable memory cells, created by the combination of the forming pulse and the programming pulse, will vary according to the variations of the programmable resistive memory cells naturally caused by the natural properties of the material and the manufacturing process. The method used by the system can include finding the forming pulse level by testing different test sets of the programmable resistive memory cells on the integrated circuit before applying the forming pulse.

An exemplary system for executing a physically unclonable function on an integrated circuit can include a plurality of device testers, a plurality of device probes (probers), a plurality of device handlers, and a plurality of interface test adapters (interface adapters). The device tester may interact with the device prober to test integrated circuit chips in wafer form. The device tester may also interact with the device handler to test the packaged integrated circuit. As shown in fig. 4, an exemplary system 410 includes PUF logic and drivers 420, and a device handler/prober 430 coupled to the device tester (420). An integrated circuit 440, subject to PUF logic and drivers 420, is coupled to the device handler/prober 430. The integrated circuit 440 includes a security circuit. A PUF ID circuit in the security circuit includes a first subset and a second subset of a set of programmable resistive memory cells established by a combination of forming pulses and programming pulses applied to the system.

An exemplary integrated circuit in the system 410 may be the integrated circuit 100, as described with reference to FIG. 1. During the manufacture of integrated circuit 100, system 410 performs the actions identified in the flowcharts of fig. 2 and 3.

FIG. 5 shows a conductive filament and a non-conductive filament in a programmable resistive memory cell. Fig. 5 (a) shows a programmable resistive memory cell. A programmable resistive memory cell 500 includes a first electrode, a second electrode, and a programmable metal oxide memory element 510 disposed between the first electrode and the second electrode. The forming pulse can have a voltage high enough to generate a conductive portion in the programmable metal oxide memory element of the memory cell. In some metal oxide memory materials, the conductive portion can include oxygen vacancies that are initiated by an electric field across the material and align to provide a conductive path. The forming pulses applied to memory cells, such as memory cell 500 in the first and second subsets of the set of memory cells, can cause a conductive filament to be formed connecting the first and second electrodes of the memory cells in the first subset and not a conductive filament to be formed connecting the first and second electrodes of the memory cells in the second subset. Thus, the memory cells in the first subset can be in a low resistance state (fig. 5 (B)), while the memory cells in the second subset can be in a high resistance state (fig. 5 (C)). The low resistance state and the high resistance state can be used to indicate a logical "1" or "0" in the data set.

The programming pulses applied to the first and second subsets of programmable resistive memory cells after the forming pulse can stabilize and enhance the conductivity of the conductive filament of the memory cells in the first subset without causing a conductive filament of the memory cells in the second subset to form.

An exemplary conductive filament is shown in FIG. 5 (B), which connects the first and second electrodes of the memory cells in the first subset via two conductive paths formed by oxygen vacancies in the metal oxide memory element. An exemplary non-conductive filament is depicted in fig. 5 (C), wherein the oxygen vacancies do not form a path connecting the first and second electrodes of the memory cells in the second subset. Although fig. 5 depicts the programmable resistive memory cell as including a programmable metal oxide memory element, the techniques described herein can be applied to other types of programmable resistive memory materials.

Fig. 6A and 6B illustrate resistance ranges in an operation to generate a data set. All members of a set of programmable resistive memory cells are in an initial resistance range (e.g., ranges 610, 610b) before a forming pulse having a forming pulse level is applied to the set. After the forming pulse is applied to the set, the resistance in a first subset of the set of programmable resistive memory cells changes to an intermediate resistance range (e.g., ranges 620, 620b), while a second subset of the set of programmable resistive memory cells has a resistance that falls outside the intermediate range (e.g., ranges 630, 630 b). After the programming pulse is applied to the set, the resistance of the first subset changes from the intermediate range to a first final resistance range (e.g., ranges 640, 640b), while the second subset of programmable resistive memory cells has a resistance in a second final resistance range (e.g., ranges 650, 650b) that does not overlap with the first final resistance range.

In one embodiment as shown in FIG. 6A, the initial resistance range (e.g., 610) is a high resistance range, the intermediate resistance range (e.g., 620) is lower than the initial resistance range (e.g., 610), the first final resistance range (e.g., 640) is lower than the intermediate resistance range (e.g., 620), and the second final resistance range (e.g., 650) is higher than the first final resistance rangeAnd (e.g., 640). The programming pulse in this embodiment is referred to as a set pulse. The set pulse has a voltage high enough to reconnect a conductive path in a filament in the programmable resistive memory elements of the first subset of the set of memory cells so the programmable memory elements are in a low resistance state. The filaments are further described with reference to fig. 5. This embodiment is suitable for use in technologies where the memory cell has an initial resistance in a high resistance range and is then formed to a lower intermediate range, for example WO-based fabricated with an oxidation process that results in a high initial resistance_xThe programmable resistive memory of (1).

In another embodiment as shown in fig. 6B, the initial resistance range (e.g., 610B) is a low resistance range, the intermediate resistance range (e.g., 620B) is higher than the initial resistance range (e.g., 610B), the first final resistance range (e.g., 640B) is higher than the intermediate resistance range, and the second final resistance range (e.g., 650B) is lower than the first final resistance range (e.g., 640B). The programming pulse in this embodiment is referred to as a reset pulse. The reset pulse has a voltage high enough to break a conductive path in a filament in the programmable resistive memory elements of the first subset of the set of memory cells so that the programmable resistive memory elements are in a high resistance state. The filaments are further described with reference to FIG. 5. This embodiment is suitable for use in technologies where the memory cell has an initial resistance in a low resistance range and is then formed to a higher intermediate range, for example WO-based fabricated with a different oxidation process resulting in a low initial resistance_xThe programmable resistive memory of (1).

7A, 7B, and 7C show probability plots of the resistance of a memory cell at various stages of a PUF process as described herein. FIG. 7A shows that all members of the set are in an initial resistance range, such as between about 2700kohm and 3000kohm (e.g., range 710), before a forming pulse having a forming pulse level is applied to the set of programmable resistive memory cells.

FIG. 7B shows the result after applying a forming pulse to all members of the set of programmable resistive memory cells. The forming pulse has a forming pulse level characterized by inducing a resistance change in a first subset of the set of programmable resistive memory cells from an initial resistance range to an intermediate resistance range, such as between about 100kohm and 400kohm (e.g., range 720), and after the forming pulse, a second subset of the set of programmable resistive memory cells has a resistance that falls outside the intermediate range (e.g., range 730). Membership in the first subset and the second subset is determined by a physical change in response to the formed pulse across the set. The initial resistance range is separated from the intermediate resistance range by a read limit 725. A forming pulse level used for forming a pulse and a resistance threshold 705 for determining the forming pulse level are described with reference to fig. 9 to 13.

FIG. 7C shows the result after applying a programming pulse to the first and second subsets of programmable resistive memory cells. The programming pulse has a programming pulse level characterized by inducing a first subset of resistance changes from a middle range to a first final resistance range, for example, between about 0kohm and 100kohm (e.g., range 740). The programming pulse can cause the sensing margin between the memory cells in the first subset and the memory cells in the second subset to increase. After the programming pulse, the memory cells in the second subset of programmable resistive memory cells can be maintained in a resistance range that is close to the initial resistance range, and otherwise have a resistance in a second final resistance range (e.g., range 750) that does not overlap the first final resistance range. The first and second subsets of the set of programmable memory cells, created by the combination of the forming pulse and the programming pulse, will vary according to the variations of the programmable resistive memory cells naturally caused by the natural properties of the material and the manufacturing process. The first final resistance range is separated from the second final resistance range by a read limit 745 which is greater than a limit 725 between the initial resistance range and the intermediate resistance range shown in fig. 7B. Such read limits can be wide enough to ensure reliability of the first and second subsets of programmable resistive memory cells storing the data set under PVT (process, voltage, temperature) variations.

FIG. 8 illustrates different conditions for finding a forming pulse level that can then control the randomness of the data set. The condition can include a height of a voltage and/or current pulse applied to a set of programmable resistive memory cells used to generate the data set. The randomness of the data set is related to a proportion of the memory cells in the test set having resistances in the intermediate resistance range. As shown in the example of FIG. 8,

conditions

1, 2, 3, 4, and 5 result in data "0" corresponding to the intermediate resistance range having about 10%, about 30%, about 50%, about 80%, and about 90% of the memory cells in the test set, respectively. The level of the forming pulse can be adjusted according to the design specifications of the particular integrated circuit using the techniques described herein.

FIGS. 9-13 illustrate operations for finding a forming pulse level. To find the forming pulse level, a test pulse having a test pulse level can be applied in an iterative manner to a test set of programmable resistive memory cells on the same integrated circuit and preferably having the same structure as the memory cell bits to be used in creating the unique data set. For each iteration, a test set of programmable resistive memory cells different from the previously used test set can be used. A proportion of memory cells in the test set having resistances in the intermediate resistance range can be determined. If the ratio is below a threshold, the test pulse level may then be updated, the operations of applying the test pulse and determining the ratio are repeated until the determined ratio reaches the threshold and the forming pulse level can be set based on the test pulse level in the iteration that reached the threshold.

An empirically determined resistance threshold 905 can be used to determine whether a memory cell has a resistance below the resistance threshold and falling within the intermediate resistance range. As shown in the examples of fig. 9-13, the resistance threshold 905 is about 700 kohm. Because the first final resistance range is separated from the second final resistance range by a wide read limit 745 (FIG. 7C), the resistance threshold 905 can fall within the wide limit and be used for the purpose of determining which memory cells are in the intermediate resistance range. For example, instead of 700kohm, the resistance threshold can be 800kohm, 900kohm, and 1000 kohm. One advantage of having a wide margin is that the resistance of any memory cell may be less likely to cause reliability problems due to the drift of PVT (process, voltage, temperature) conditions across the margin.

Fig. 9 shows an exemplary condition 1 for finding the forming pulse level. Condition 1 includes applying a Word Line (WL) voltage of 5V, a Bit Line (BL) voltage of 5V, and a current of 41 μ Α to a test set of programmable resistive memory cells. Condition 1 causes 8% of the memory cells in the test set to be in the set state or to have a data "0" (e.g., range 940) and 92% of the memory cells in the test set to be in the initial resistance state or to have a data "1" (e.g., range 950).

Fig. 10 shows an exemplary condition 2 for finding the level of the forming pulse. Condition 2 includes applying a word line voltage of 2.5V and a bit line voltage of 4V to a test set of programmable resistive memory cells. Condition 2 causes 35% of the memory cells in the test set to be in a set state or to have a data "0" (e.g., range 1040) and 65% of the memory cells in the test set to be in an initial resistance state or to have a data "1" (e.g., range 1050).

Fig. 11 shows an exemplary condition 3 for finding the forming pulse level. Condition 3 includes applying a word line voltage of 4V and a bit line voltage of 4V to a test set of programmable resistive memory cells. Condition 3 causes 53% of the memory cells in the test set to be in a set state or to have a data "0" (e.g., range 1140) and 47% of the memory cells in the test set to be in an initial resistance state or to have a data "1" (e.g., range 1150).

Fig. 12 shows an exemplary condition 4 for finding the forming pulse level. Condition 4 includes applying a word line voltage of 2.5V and a bit line voltage of 4.5V to a test set of programmable resistive memory cells. Condition 4 causes 80% of the memory cells in the test set to be in the set state or to have a data "0" (e.g., range 1240) and 20% of the memory cells in the test set to be in the initial resistance state or to have a data "1" (e.g., range 1250).

Fig. 13 shows an exemplary condition 5 for finding the forming pulse level. Condition 5 includes applying a word line voltage of 3.5V and a bit line voltage of 4.5V to a test set of programmable resistive memory cells. Condition 5 causes 90% of the memory cells in the test set to be in a set state or to have a data "0" (e.g., range 1340) and 10% of the memory cells in the test set to be in an initial resistance state or to have a data "1" (e.g., range 1350).

For example, if the desired threshold for the proportion of memory cells in the test set is about 50%, or more preferably falls within a particular range of about 50% (e.g., 40% to 60%), the forming pulse level can be set based on the test pulse level used in the iteration that reached the threshold, or falls within that particular range (e.g., condition 3 in fig. 10), or more preferably based on the test pulse level used in the iteration that falls within that particular range.

FIG. 14 shows exemplary results of applying test pulses in a test set using condition 3 described with reference to FIG. 11. In the example of fig. 14 (a), the memory cells in the test set are in an initial resistance range of greater than 3 Mohm. In the example of fig. 14 (B), a first subset of the test set changes to an intermediate resistance range, or state of formation, after application of the test pulse corresponding to condition 3. In the example of fig. 14 (C), the first subset changes from the intermediate resistance range to a first final resistance range below 50kohm after the program/set pulse is applied.

Fig. 15A and 15B illustrate the results of generating a first data set (PUF-ID1) in a first PUF ID array and a second data set (PUF-ID2) in a second PUF ID array. As shown in fig. 15A and 15B, the present techniques exhibit highly unique and unpredictable characteristics between a first PUF ID array (e.g., array 01) and a second PUF ID array (e.g., array 02), wherein each PUF ID array comprises 1 kbits. In this example, the first and second PUF ID arrays have a WO-based profile_x(tungsten oxide) programmable resistive memory cell having resistance in a high resistance rangeThe initial resistance of (1).

Reliability tests have been performed on data sets generated by the present technique under various conditions (e.g., 0.25 hours of baking at 250 ℃, and 65 hours of baking at 250 ℃), respectively. The reliability test uses 1000 memory cells in a PUF ID array before baking, after baking at 250 ℃ for 0.25 hour, and after baking at 250 ℃ for 65 hours. In contrast, the resistance states of the 1000 memory cells in the PUF ID array after baking under two different conditions are identical to the resistance states of the 1000 memory cells in the PUF ID array before baking. Thus, the data set generated by the present technique exhibits a Bit Error Rate (BER) of 0.00% under high temperature (250 ℃) baking conditions, and can be applied to Internet of Things (IoT) products and security chips.

FIG. 16 depicts a read limit 1660 between a first final resistance range (e.g., range 1640) and a second final resistance range (e.g., range 1650) under high temperature baking conditions (e.g., 250 ℃). In this example, the read limit 1660 is between 400 and 1000kohm, i.e., supports a sense resistance threshold at 700kohm +/-300 kohm. Read limit 1660 is wide enough to separate the first final resistance range from the second final resistance range, even in the presence of a few bleed (tail) bits (e.g., range 1670) that may be induced under high temperature baking conditions (e.g., 250 ℃).

The present techniques can be implemented in devices in which the memory cell has an initial resistance in a high resistance range and is then formed to a lower intermediate range, including transition metal oxide devices (based on WO)_xBased on tantalum pentoxide (Ta)₂O₅) Based on hafnium oxide (HfO)₂) Programmable resistive memory, titanium oxynitride (TiON) -based programmable resistive memory, TiO-based programmable resistive memory_xProgrammable resistive memory of (g), conductive filament programmable resistive memory (copper-based, silver-based), phase change memory, and antifuse device (metal oxide semiconductor (MOS) orMetal-insulator-metal (MIM) structures, which act as anti-fuse memory cells with dielectric breakdown).

The present technique can be implemented in a memory cell in which the memory cell has an initial resistance in a low resistance range and is then formed to a higher intermediate range, including metal oxide memories of low initial resistance, such as WO_xProgrammable resistive memories, and fuse devices such as metal fuses, polysilicon fuses, and contact fuses.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of generating a data set on an integrated circuit, the integrated circuit comprising a plurality of programmable resistive memory cells, the method comprising:

applying a forming pulse to all members of a set of said programmable resistive memory cells, said forming pulse having a forming pulse level characterized by inducing a resistance change from an initial resistance range to an intermediate resistance range in a first subset of said set of said programmable resistive memory cells, and a second subset of said set of said programmable resistive memory cells having a resistance that falls outside said intermediate resistance range after said forming pulse; and

applying a programming pulse to the first and second subsets of the programmable resistive memory cells, the programming pulse having a programming pulse level characterized by inducing a resistance change in the first subset from the intermediate resistance range to a first final resistance range, and after the programming pulse, the second subset of the programmable resistive memory cells having a resistance in a second final resistance range, the second final resistance range being non-overlapping with the first final resistance range, the first and second subsets of the set of the programmable resistive memory cells thereby storing the data set.

2. The method of claim 1, comprising finding the forming pulse level by testing some of said programmable resistive memory cells on the integrated circuit prior to applying the forming pulse.

3. The method of claim 1, comprising, prior to applying the forming pulse, finding the forming pulse level by a method comprising:

iteratively applying a test pulse having a test pulse level to a test set of the programmable resistive memory cells and determining a proportion of the programmable resistive memory cells in the test set having resistances in the intermediate resistance range and, if the proportion is below a threshold, updating the test pulse level, repeating the applying the test pulse step and the determining step on a different test set until the determined proportion reaches the threshold, and setting the forming pulse level based on the test pulse level in an iteration of reaching the threshold.

4. The method of claim 1, comprising sensing the data set using a read voltage for resistances between the first final resistance range and the second final resistance range, wherein the first final resistance range and the second final resistance range are separated by a read limit that is greater than a limit between the initial resistance range and the intermediate resistance range.

5. The method of claim 1, wherein said programmable resistive memory cell comprises a plurality of programmable resistive memory elements characterized by an initial resistance in a high resistance range, wherein said intermediate resistance range is lower than said high resistance range, said first final resistance range is lower than said intermediate resistance range, and said second final resistance range is higher than said first final resistance range.

6. The method of claim 1, wherein the programmable resistive memory cell comprises a plurality of programmable resistive memory elements characterized by an initial resistance in a low resistance range, wherein the intermediate resistance range is higher than the low resistance range, the first final resistance range is higher than the intermediate resistance range, and the second final resistance range is lower than the first final resistance range.

7. The method of claim 1, wherein the programmable resistive memory cells include a plurality of programmable resistive memory elements, and wherein the applying the forming pulse forms a conductive filament connecting the first and second electrodes of the programmable resistive memory cells in the first subset and does not form a conductive filament connecting the first and second electrodes of the programmable resistive memory cells in the second subset.

8. The method of claim 7, wherein the programming pulse stabilizes and enhances conductivity of the conductive filament of the programmable resistive memory cells in the first subset without causing a conductive filament of the programmable resistive memory cells in the second subset to form.

9. A method of manufacturing an integrated circuit, comprising:

forming a plurality of programmable resistive memory cells on the integrated circuit;

connecting the integrated circuit to a system configured to apply a physical unclonable function to the programmable resistive memory cells on the integrated circuit; and

using the system to generate a data set in a set of the programmable resistive memory cells in the programmable resistive memory cells by:

applying a forming pulse to all members of the set, the forming pulse having a forming pulse level characterized by inducing a resistance change from an initial resistance range to an intermediate resistance range in a first subset of the set of the programmable resistive memory cells, and a second subset of the set of the programmable resistive memory cells having a resistance that falls outside the intermediate resistance range after the forming pulse; and

10. An integrated circuit device, comprising:

a plurality of programmable resistive memory cells; and

a controller configured to generate a data set in a set of the programmable resistive memory cells among the programmable resistive memory cells by a process comprising: