CN105932996A - Resistance voltage divider type DAC-PUF circuit - Google Patents

Abstract

The present invention discloses a resistance voltage divider type DAC-PUF circuit which comprises an input register, a bias voltage generation circuit, a voltage comparator, and a time sequence controller. The bias voltage generation circuit comprises a two resistance voltage divider type DACs with the same structure. Each of the resistance voltage divider type DACs comprises three 2-4 decoded with the same structure, an operational amplifier, and four resistance divider units with the same structure. The resistance divider units comprise 22 NMOS tubes and 17 resistors. The circuit has the advantages that a digital and analog mixing mode is employed, the mismatch of the resistance voltage divider type DAC resistors is used to generate a bias voltage signal, the output key change is realized, in the TSMC-LP 65nm CMOS process, a full customization mode is used to design the circuit layout of the invention, the resistance voltage divider type DAC-PUF circuit is tested, an experimental result shows that the uniqueness of the resistance voltage divider type DAC-PUF circuit is strong, the randomness and reliability in different working environments are larger than 99.1% and 97.8%, and the circuit can be widely applied to the fields of key generation and device authentication.

Description

A kind of electric resistance partial pressure type DAC-PUF circuit

Technical field

The present invention relates to a kind of PUF circuit, especially relate to a kind of electric resistance partial pressure type DAC-PUF circuit.

Background technology

Along with developing rapidly of information technology, information security is increasingly paid close attention to by people.The unclonable function of physics (Physical Unclonable Function, PUF) circuit provides a kind of information security that strengthens from hardware texture characteristic The concept of approach .PUF is proposed by research people such as Pappu the earliest, and it is integrated circuit fields " DNA characteristics identification technology ".Mesh Before silica-based PUF circuit be a topmost research direction, it utilize structure and the identical element circuit of design parameter it Between the small process deviation (show and vary in size for voltage, electric current, time delay etc. on electrology characteristic) that exists, produce and have uniquely Property, randomness and the response of nonclonability.Uniqueness refers to that a given PUF circuit has unique function performance, i.e. Satisfied unique excitation identifying himself can be produced and tackle (Challenge Response Pairs, CRPs) mutually；Randomness Refer to that PUF circuit output logical zero and the probability of logic 1 are essentially identical and have random distribution characteristic；Physics nonclonability is Refer to that the above-mentioned three big characteristics replicating a PUF circuit difficulty very big .PUF circuit with same functions function make it protect at IP Protect, the field such as device authentication and key generation has broad application prospects.

Physics nonclonability is the build-in attribute of PUF circuit, therefore should consider emphatically defeated in the design of PUF circuit Go out uniqueness, randomness and the reliability of response, and these attributes depend primarily on the size of PUF circuit deviations signal and divide Cloth, and it is limited to the sensitivity of comparator.Traditional PUF circuit utilizes the geometric scale deviation (width of MOSFET in digital circuit Degree and length variation) and technological parameter deviation (doping content, oxidated layer thickness, diffusion depth etc.) come design deviation signal generation Circuit, such as the delay unit in Arbiter-PUF circuit, the cross coupling inverter in SRAM-PUF circuit and RO-PUF electricity Ring oscillator etc. in road.Compared with digital circuit, analog circuit is more sensitive to device technology deviation, therefore may utilize mould Intend device design deviation signal generating circuit.In standard CMOS process, diffusion region, well region and polysilicon etc. can be adopted to system Make resistance, yet with factors such as resistive edge effect, electron mobility and resistance thickness change at random so that actual resistance Deviation theory value, and resistance physical dimension the least resistance deviation range is the biggest.

In view of this, utilize the random process deviation of resistance to design PUF circuit, respond only for improving the output of PUF circuit One property, randomness and reliability are significant.

Summary of the invention

The technical problem to be solved is to provide a kind of electric resistance partial pressure type DAC-PUF circuit, and this PUF circuit utilizes Electric resistance partial pressure type digital to analog converter (Digital to Analog Converter, DAC) design deviation voltage generation circuit, by This output producing PUF circuit by the random process deviation of resistance responds, and makes the output response of PUF circuit have higher Uniqueness, randomness and reliability.

The present invention solves the technical scheme that above-mentioned technical problem used: a kind of electric resistance partial pressure type DAC-PUF circuit, bag Include input register, deviation voltage produces circuit, voltage comparator and time schedule controller, and described input register has clock End, input, the first outfan, the second outfan, the 3rd outfan and the 4th outfan, when described voltage comparator has Zhong Duan, first input end, the second input and outfan, described time schedule controller respectively with described input register time The clock end of Zhong Duan and described voltage comparator connects, and described deviation voltage produces circuit and includes two electricity that structure is identical Resistance dividing potential drop type DAC, described electric resistance partial pressure type DAC includes 2-4 decoder, operational amplifier and four knots that three structures are identical The electric resistance partial pressure unit that structure is identical, described 2-4 decoder have clock end, input, the first outfan, the second outfan, 3rd outfan and the 4th outfan, described operational amplifier has normal phase input end, inverting input and an outfan, three Described 2-4 decoder is respectively a 2-4 decoder, the 2nd 2-4 decoder and the 3rd 2-4 decoder, four described electricity Resistance partial pressure unit is respectively the first electric resistance partial pressure unit, the second electric resistance partial pressure unit, the 3rd electric resistance partial pressure unit and the 4th resistance Partial pressure unit；Described electric resistance partial pressure unit include the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, Five NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS Pipe, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS tube, the 22nd NMOS tube, first Resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance, Tenth resistance, the 11st resistance, the 12nd resistance, the 13rd resistance, the 14th resistance, the 15th resistance, the 16th resistance and 17th resistance；The grid of the first described NMOS tube, the grid of the second described NMOS tube, the grid of the 3rd described NMOS tube The grid of pole and the 4th described NMOS tube connects and it connects the first row input that end is described electric resistance partial pressure unit, institute The grid of the 5th NMOS tube stated, the grid of the 6th described NMOS tube, the grid of the 7th described NMOS tube and described The grid of eight NMOS tube connects and it connects the secondary series input that end is described electric resistance partial pressure unit, the 9th described NMOS The grid of pipe, the grid of the tenth described NMOS tube, the grid of the 11st described NMOS tube and the 12nd described NMOS tube Grid connect and its to connect end be the 3rd row input of described electric resistance partial pressure unit, the grid of the 13rd described NMOS tube Pole, the grid of the 14th described NMOS tube, the grid of the 15th described NMOS tube and the grid of the 16th described NMOS tube Pole connects and it connects the 4th row input that end is described electric resistance partial pressure unit, the source electrode of the first described NMOS tube, institute The one end of the first resistance stated and one end of the second described resistance connect, and the other end ground connection of the first described resistance is described One end of the source electrode of the second NMOS tube, the other end of the second described resistance and the 3rd described resistance connect, described the One end of the source electrode of three NMOS tube, the other end of the 3rd described resistance and the 4th described resistance connects, described the 4th One end of the source electrode of NMOS tube, the other end of the 4th described resistance and the 5th described resistance connects, the 5th described NMOS One end of the drain electrode of pipe, the other end of the 5th described resistance and the 6th described resistance connects, the 6th described NMOS tube One end of drain electrode, the other end of described 6th resistance and the 7th described resistance connects, the drain electrode of the 7th described NMOS tube, One end of the other end of the 7th described resistance and the 8th described resistance connects, the drain electrode of the 8th described NMOS tube, described The other end of the 8th resistance and one end of the 9th described resistance connect, the source electrode of the 9th described NMOS tube, described the One end of the other end of nine resistance and the tenth described resistance connects, the described source electrode of the tenth NMOS tube, the described the tenth electricity The other end of resistance and one end of the 11st described resistance connect, the described source electrode of the 11st NMOS tube, the described the 11st One end of the other end of resistance and the 12nd described resistance connects, the described source electrode of the 12nd NMOS tube, the described the tenth One end of the other end of two resistance and the 13rd described resistance connects, the drain electrode of the 13rd described NMOS tube, described the One end of the other end of 13 resistance and the 14th described resistance connects, the drain electrode of the 14th described NMOS tube, described One end of the other end of the 14th resistance and the 15th described resistance connects, the drain electrode of the 15th described NMOS tube, described The other end of the 15th resistance and one end of the 16th described resistance connect, the described drain electrode of the 16th NMOS tube, institute One end of the other end of the 16th resistance stated and the 17th described resistance connects, the other end of the 17th described resistance and The source electrode of the 17th described NMOS tube connects, the ginseng that drain electrode is described electric resistance partial pressure unit of the 17th described NMOS tube Examining voltage input end, the grid of the 17th described NMOS tube and the grid of the 22nd described NMOS tube connect and it connects The input that end is described electric resistance partial pressure unit, the drain electrode of the first described NMOS tube, the source electrode of the 8th described NMOS tube, The drain electrode of the drain electrode of the 9th described NMOS tube, the source electrode of the 16th described NMOS tube and the 18th described NMOS tube is even Connect, the drain electrode of the second described NMOS tube, the source electrode of the 7th described NMOS tube, the drain electrode of the tenth described NMOS tube, described The source electrode of the 15th NMOS tube and the drain electrode of the 19th described NMOS tube connect, the described drain electrode of the 3rd NMOS tube, institute The source electrode of the 6th NMOS tube stated, the drain electrode of the 11st described NMOS tube, the source electrode of the 14th described NMOS tube and described The drain electrode of the 20th NMOS tube connect, the drain electrode of the 4th described NMOS tube, the source electrode of the 5th described NMOS tube, described The drain electrode of the drain electrode of the 12nd NMOS tube, the source electrode of the 13rd described NMOS tube and the 21st described NMOS tube connects, The first row input that grid is described electric resistance partial pressure unit of the 18th described NMOS tube, the 19th described NMOS tube The second row input that grid is described electric resistance partial pressure unit, the grid of the 20th described NMOS tube is described resistance The third line input of partial pressure unit, the fourth line that grid is described electric resistance partial pressure unit of the 21st described NMOS tube Input, the source electrode of the 18th described NMOS tube, the source electrode of the 19th described NMOS tube, the 20th described NMOS tube The drain electrode of source electrode, the source electrode of the 21st described NMOS tube and the 22nd described NMOS tube connects, described the 20th The source electrode of two NMOS tube is the outfan of described electric resistance partial pressure unit；The first row input of the first described electric resistance partial pressure unit End, the described the first row input of the second electric resistance partial pressure unit, the first row input of the 3rd described electric resistance partial pressure unit, The first row input of the 4th described electric resistance partial pressure unit and the first outfan of a described 2-4 decoder connect, institute Second row input of the first electric resistance partial pressure unit stated, the second row input of the second described electric resistance partial pressure unit, described The second row input of the 3rd electric resistance partial pressure unit, the second row input of the 4th described electric resistance partial pressure unit and described Second outfan of the oneth 2-4 decoder connects, described the third line input of the first electric resistance partial pressure unit, described second The third line input of electric resistance partial pressure unit, described the third line input of the 3rd electric resistance partial pressure unit, the described the 4th electricity The third line input of resistance partial pressure unit and the 3rd outfan of a described 2-4 decoder connect, the first described resistance The fourth line input of partial pressure unit, the fourth line input of the second described electric resistance partial pressure unit, the 3rd described resistance divide The pressure fourth line input of unit, the fourth line input of the 4th described electric resistance partial pressure unit and a described 2-4 decoding 4th outfan of device connects, the first row input of the first described electric resistance partial pressure unit, the second described electric resistance partial pressure list The first row input of unit, the first row input of the 3rd described electric resistance partial pressure unit, the 4th described electric resistance partial pressure unit First row input and the 2nd described 2-4 decoder first outfan connect, the first described electric resistance partial pressure unit Secondary series input, the secondary series input of the second described electric resistance partial pressure unit, the of the 3rd described electric resistance partial pressure unit The second of two row inputs, the secondary series input of the 4th described electric resistance partial pressure unit and the 2nd described 2-4 decoder is defeated Go out end to connect, the 3rd row input of the first described electric resistance partial pressure unit, the 3rd row of the second described electric resistance partial pressure unit Input, described the 3rd row input of the 3rd electric resistance partial pressure unit, the 4th described electric resistance partial pressure unit the 3rd row defeated The 3rd outfan entering end and the 2nd described 2-4 decoder connects, the 4th row input of the first described electric resistance partial pressure unit End, described 4th row input of the second electric resistance partial pressure unit, the 4th row input of the 3rd described electric resistance partial pressure unit, 4th row input of the 4th described electric resistance partial pressure unit and the 4th outfan of the 2nd described 2-4 decoder connect, institute The input of the first electric resistance partial pressure unit stated and the first outfan of the 3rd described 2-4 decoder connect, described second The input of electric resistance partial pressure unit and the second outfan of the 3rd described 2-4 decoder connect, the 3rd described electric resistance partial pressure 3rd outfan of the input of unit and the 3rd described 2-4 decoder connects, the 4th described electric resistance partial pressure unit defeated The 4th outfan entering end and described the 3rd 2-4 decoder connects, the outfan of the first described electric resistance partial pressure unit, described The outfan of the second electric resistance partial pressure unit, the outfan of the 3rd described electric resistance partial pressure unit, the 4th described electric resistance partial pressure The normal phase input end of the outfan of unit and described operational amplifier connects, the inverting input of described operational amplifier and The outfan of described operational amplifier connects and it connects the outfan that end is described electric resistance partial pressure type DAC, and described the The input of one 2-4 decoder is the first input end of described electric resistance partial pressure type DAC, the 2nd described 2-4 decoder defeated Entering the end the second input for described electric resistance partial pressure type DAC, the input of the 3rd described 2-4 decoder is described resistance 3rd input of dividing potential drop type DAC, the clock end of a described 2-4 decoder, the clock end of the 2nd described 2-4 decoder Connect with the clock end of the 3rd described 2-4 decoder and it connects the clock end that end is described electric resistance partial pressure type DAC, described The reference voltage input terminal of the first electric resistance partial pressure unit, the described reference voltage input terminal of the second electric resistance partial pressure unit, institute The reference voltage input terminal of the 3rd electric resistance partial pressure unit stated and the reference voltage input terminal of the 4th described electric resistance partial pressure unit Connect and it connects the reference voltage input terminal that end is described electric resistance partial pressure type DAC；The first of described input register is defeated The 3rd input going out end and the first described electric resistance partial pressure type DAC connects, and the second outfan of described input register divides The first input end of the first other and described electric resistance partial pressure type DAC and the first input end of the second described electric resistance partial pressure type DAC Connect, the 3rd outfan of described input register respectively with the second input of the first described electric resistance partial pressure type DAC and Second input of the second described electric resistance partial pressure type DAC connects, the 4th outfan of described input register and described Second electric resistance partial pressure type DAC the 3rd input connect, described time schedule controller respectively with the first described electric resistance partial pressure type The clock end of the clock end of DAC and the second described electric resistance partial pressure type DAC connects, the first described electric resistance partial pressure type DAC defeated The first input end going out end and described voltage comparator connects, the outfan of the second described electric resistance partial pressure type DAC and described Voltage comparator second input connect.

Described voltage comparator include the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, second 13 NMOS tube, the 24th NMOS tube, the 25th NMOS tube, the 26th NMOS tube, the 27th NMOS tube, the 20th Eight NMOS tube and RS latch；Described RS latch includes the one or two input nand gate and the two or two input nand gate, described The one or two input nand gate and the two or two described input nand gate be respectively provided with first input end, the second input and output End；The source electrode of the first described PMOS, the source electrode of the second described PMOS, the source electrode of the 3rd described PMOS and described The source electrode of the 4th PMOS all access power supply, the grid of the first described PMOS, the grid of the 23rd described NMOS tube The grid of pole, the grid of the 24th described NMOS tube and the 4th described PMOS connects and its connection end is described electricity The clock end of pressure comparator, the drain electrode of the first described PMOS, the drain electrode of the second described PMOS, the 3rd described PMOS The first input end of the grid of pipe, the drain electrode of the 23rd described NMOS tube and the one or two described input nand gate connects, The drain electrode of the 3rd described PMOS, the grid of the second described PMOS, the drain electrode of the 4th described PMOS, described The drain electrode of 24 NMOS tube and the second input of the two or two described input nand gate connect, the 23rd described NMOS The source electrode of pipe, the drain electrode of the 25th described NMOS tube, the drain electrode and the described the 20th of the 26th described NMOS tube The grid of seven NMOS tube connects, the source electrode of the 24th described NMOS tube, the grid of the 26th described NMOS tube, described The drain electrode of the 27th NMOS tube and the drain electrode of described the 28th NMOS tube connect, the 25th described NMOS tube Source electrode, the source electrode of the 26th described NMOS tube, the source electrode and the described the 28th of the 27th described NMOS tube The source grounding of NMOS tube, the first input end that grid is described voltage comparator of the 25th described NMOS tube, Second input that grid is described voltage comparator of the 28th described NMOS tube, the one or two described input is with non- Second input of door and the outfan of the two or two described input nand gate connect, the of the two or two described input nand gate The outfan of one input and the one or two described input nand gate connects and its connection end is the defeated of described voltage comparator Go out end.This circuit is high to deviation voltage detectivity, and judgement output valve can keep the advantage such as constant in pre-charging stage.

Described time schedule controller includes the one or two input and door, the two or two inputs and door, the first phase inverter, second anti-phase Device, the 3rd phase inverter and the 4th phase inverter；Described one or two input and door and the described the 2nd 2 input and door are respectively provided with the One input, the second input and outfan, the one or two described input is described sequencing contro with the first input end of door First Enable Pin of device, is used for accessing input register and enables signal, the second input of the one or two described input and door and The two or two described input is connected with the first input end of door and it connects the clock end that end is described time schedule controller, is used for Incoming clock signal, the two or two described input and second Enable Pin that the second input is described time schedule controller of door, Signal is enabled, described one or two input and the outfan of door and the first described phase inverter defeated for accessing voltage comparator Entering end to connect, the outfan of the first described phase inverter and the input of the second described phase inverter connect, and described second is anti- The outfan of phase device is the first outfan of described time schedule controller, the first outfan of described time schedule controller and described The clock end of input register connect, the outfan of described two or two input and door and the input of the 3rd described phase inverter End connects, and the outfan of the 3rd described phase inverter and the input of the 4th described phase inverter connect, and described the 4th is anti-phase The outfan of device is the second outfan of described time schedule controller, the second outfan of described time schedule controller respectively with institute The clock end of the voltage comparator stated, the clock end of the first described electric resistance partial pressure type DAC and the second described electric resistance partial pressure type The clock end of DAC connects.This circuit can ensure that whole PUF circuit is operated under orderly clock: when decoder input data, Voltage comparator is in pre-charging stage；When decoder latches, voltage comparator is in the evaluation stage.

Described input register include the first d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop and the 8th d type flip flop；Described the first d type flip flop, described second D type flip flop, described 3d flip-flop, described four d flip-flop, the 5th described d type flip flop, the 6th described D trigger Device, the 7th described d type flip flop and the 8th described d type flip flop are respectively provided with input, clock end and outfan；Described first The clock end of d type flip flop, the clock end of the second described d type flip flop, the clock end of described 3d flip-flop, described The clock end of four d flip-flop, the clock end of the 5th described d type flip flop, the clock end of the 6th described d type flip flop, described The clock end of the 7th d type flip flop and the clock end of the 8th described d type flip flop connect and it connects the input that end is described and deposits The clock end of device, the input of the first described d type flip flop, the input of the second described d type flip flop, the 3rd described D touch Send out the input of device, the input of described four d flip-flop, the input of the 5th described d type flip flop, the 6th described D The clock end of the input of trigger, the input of the 7th described d type flip flop and the 8th described d type flip flop connects and it connects Connect the input that end is described input register, the outfan of the first described d type flip flop and the second described d type flip flop Outfan connects and it connects the first outfan that end is described input register, the outfan of described 3d flip-flop Connect with the outfan of described four d flip-flop and it connects the second outfan that end is described input register, described The outfan of the 5th d type flip flop and the outfan of the 6th described d type flip flop connects and it connects the input that end is described and posts 3rd outfan of storage, the outfan of the 7th described d type flip flop and the outfan of the 8th described d type flip flop connect and it Connect the 4th outfan that end is described input register.This circuit can ensure that the pumping signal that PUF circuit inputs synchronizes, and keeps away Exempt from the impact output response of nonsynchronous pumping signal.

Compared with prior art, it is an advantage of the current invention that to produce circuit, voltage ratio by input register, deviation voltage Relatively device and time schedule controller build electric resistance partial pressure type DAC-PUF circuit, and deviation voltage generation circuit includes two that structure is identical Electric resistance partial pressure type DAC, electric resistance partial pressure type DAC includes 2-4 decoder, operational amplifier and four the structure phases that three structures are identical With electric resistance partial pressure unit, electric resistance partial pressure unit include the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS Pipe, the 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS tube, the 22nd NMOS tube, First resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th Resistance, the tenth resistance, the 11st resistance, the 12nd resistance, the 13rd resistance, the 14th resistance, the 15th resistance, the 16th electricity Resistance and the 17th resistance；Thus use numerical model analysis mode, utilize the mismatch of electric resistance partial pressure type DAC resistance to produce deviation voltage Signal, it is achieved output cipher key change, under TSMC-LP 65nmCMOS technique, uses full custom mode to design the circuit of the present invention Domain, tests the present invention, test result indicate that uniqueness of the present invention is strong, and randomness and can under different operating environment It is respectively greater than 99.1% and 97.8% by property, can be widely applied to the fields such as key generation and device authentication.

Accompanying drawing explanation

Fig. 1 is the structure chart of the electric resistance partial pressure type DAC-PUF circuit of the present invention；

Fig. 2 is the structure chart of electric resistance partial pressure type DAC of the electric resistance partial pressure type DAC-PUF circuit of the present invention；

Fig. 3 is the circuit diagram of the electric resistance partial pressure unit of the electric resistance partial pressure type DAC-PUF circuit of the present invention；

Fig. 4 is the circuit diagram of the voltage comparator of the electric resistance partial pressure type DAC-PUF circuit of the present invention；

Fig. 5 is the circuit diagram of the time schedule controller of the electric resistance partial pressure type DAC-PUF circuit of the present invention；

Fig. 6 is the circuit diagram of the input register of the electric resistance partial pressure type DAC-PUF circuit of the present invention；

Fig. 7 is that the electric resistance partial pressure type DAC-PUF circuit of the present invention exports Hamming distance statistical result figure between the sheet responded；

Fig. 8 is the randomness statistical result figure of the electric resistance partial pressure type DAC-PUF circuit output response of the present invention；

Fig. 9 (a) is the reliability variation with temperature figure of the electric resistance partial pressure type DAC-PUF circuit of the present invention；

Fig. 9 (b) is the reliability variation diagram with voltage of the electric resistance partial pressure type DAC-PUF circuit of the present invention.

Detailed description of the invention

Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.

Embodiment one: as shown in FIG. 1 to 3, a kind of electric resistance partial pressure type DAC-PUF circuit, including input register, deviation Voltage generation circuit, voltage comparator and time schedule controller, input register have clock end, input, the first outfan, Two outfans, the 3rd outfan and the 4th outfan, voltage comparator have clock end, first input end, the second input and Outfan, time schedule controller is connected with the clock end of input register and the clock end of voltage comparator respectively, and deviation voltage produces Raw circuit includes two electric resistance partial pressure types DAC that structure is identical, and electric resistance partial pressure type DAC includes the 2-4 decoding that three structures are identical The electric resistance partial pressure unit that device, operational amplifier and four structures are identical, 2-4 decoder has clock end, input, the first output End, the second outfan, the 3rd outfan and the 4th outfan, operational amplifier has normal phase input end, inverting input and defeated Going out end, three 2-4 decoders are respectively a 2-4 decoder, the 2nd 2-4 decoder and the 3rd 2-4 decoder, and four resistance divide Pressure unit is respectively the first electric resistance partial pressure unit cell1, the second electric resistance partial pressure unit cell2, the 3rd electric resistance partial pressure unit cell3 With the 4th electric resistance partial pressure unit cell4；Electric resistance partial pressure unit includes the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5, the 6th NMOS tube N6, the 7th NMOS tube N7, the 8th NMOS tube N8, the 9th NMOS Pipe N9, the tenth NMOS tube N10, the 11st NMOS tube N11, the 12nd NMOS tube N12, the 13rd NMOS tube N13, the 14th NMOS Pipe N14, the 15th NMOS tube N15, the 16th NMOS tube N16, the 17th NMOS tube N17, the 18th NMOS tube N18, the 19th NMOS tube N19, the 20th NMOS tube N20, the 21st NMOS tube N21, the 22nd NMOS tube N22, the first resistance R1, second Resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th Resistance R9, the tenth resistance R10, the 11st resistance R11, the 12nd resistance R12, the 13rd resistance R13, the 14th resistance R14, 15 resistance R15, the 16th resistance R16 and the 17th resistance R17；The grid of the first NMOS tube N1, the grid of the second NMOS tube N2 The grid of pole, the grid of the 3rd NMOS tube N3 and the 4th NMOS tube N4 connects and it connects the first row that end is electric resistance partial pressure unit Input, the grid of the 5th NMOS tube N5, the grid of the 6th NMOS tube N6, the grid of the 7th NMOS tube N7 and the 8th NMOS tube N8 Grid connect and its to connect end be the secondary series input of electric resistance partial pressure unit, the grid of the 9th NMOS tube N9, the tenth NMOS The grid of the grid of pipe N10, the grid of the 11st NMOS tube N11 and the 12nd NMOS tube N12 connects and its connection end is resistance 3rd row input of partial pressure unit, the grid of the 13rd NMOS tube N13, the grid of the 14th NMOS tube N14, the 15th NMOS The grid of pipe N15 and the grid of the 16th NMOS tube N16 connect and it connects the 4th row input that end is electric resistance partial pressure unit, One end of the source electrode of the first NMOS tube N1, one end of the first resistance R1 and the second resistance R2 connects, the other end of the first resistance R1 Ground connection, one end of the source electrode of the second NMOS tube N2, the other end of the second resistance R2 and the 3rd resistance R3 connects, the 3rd NMOS tube N3 Source electrode, the other end of the 3rd resistance R3 and the 4th resistance R4 one end connect, the source electrode of the 4th NMOS tube N4, the 4th resistance R4 The other end and the 5th resistance R5 one end connect, the drain electrode of the 5th NMOS tube N5, the other end of the 5th resistance R5 and the 6th electricity One end of resistance R6 connects, and one end of the drain electrode of the 6th NMOS tube N6, the other end of the 6th resistance R6 and the 7th resistance R7 connects, the One end of the drain electrode of seven NMOS tube N7, the other end of the 7th resistance R7 and the 8th resistance R8 connects, the drain electrode of the 8th NMOS tube N8, One end of the other end of the 8th resistance R8 and the 9th resistance R9 connects, the source electrode of the 9th NMOS tube N9, the 9th resistance R9 another One end of end and the tenth resistance R10 connects, the source electrode of the tenth NMOS tube N10, the other end of the tenth resistance R10 and the 11st resistance One end of R11 connects, the source electrode of the 11st NMOS tube N11, the other end of the 11st resistance R11 and the one of the 12nd resistance R12 End connects, and one end of the source electrode of the 12nd NMOS tube N12, the other end of the 12nd resistance R12 and the 13rd resistance R13 connects, One end of the drain electrode of the 13rd NMOS tube N13, the other end of the 13rd resistance R13 and the 14th resistance R14 connects, and the 14th One end of the drain electrode of NMOS tube N14, the other end of the 14th resistance R14 and the 15th resistance R15 connects, the 15th NMOS tube One end of the drain electrode of N15, the other end of the 15th resistance R15 and the 16th resistance R16 connects, the leakage of the 16th NMOS tube N16 One end of pole, the other end of the 16th resistance R16 and the 17th resistance R17 connects, the other end and the tenth of the 17th resistance R17 The source electrode of seven NMOS tube N17 connects, the reference voltage input terminal that drain electrode is electric resistance partial pressure unit of the 17th NMOS tube N17, the The grid of 17 NMOS tube N17 and the grid of the 22nd NMOS tube N22 connect and its connection end is the defeated of electric resistance partial pressure unit Enter end, the drain electrode of the first NMOS tube N1, the source electrode of the 8th NMOS tube N8, the drain electrode of the 9th NMOS tube N9, the 16th NMOS tube N16 Source electrode and the 18th NMOS tube N18 drain electrode connect, the drain electrode of the second NMOS tube N2, the source electrode of the 7th NMOS tube N7, the tenth The drain electrode of the drain electrode of NMOS tube N10, the source electrode of the 15th NMOS tube N15 and the 19th NMOS tube N19 connects, the 3rd NMOS tube N3 Drain electrode, the source electrode of the 6th NMOS tube N6, the drain electrode of the 11st NMOS tube N11, the source electrode and the 20th of the 14th NMOS tube N14 The drain electrode of NMOS tube N20 connects, the drain electrode of the 4th NMOS tube N4, the source electrode of the 5th NMOS tube N5, the leakage of the 12nd NMOS tube N12 The drain electrode of pole, the source electrode of the 13rd NMOS tube N13 and the 21st NMOS tube N21 connects, and the grid of the 18th NMOS tube N18 is The first row input of electric resistance partial pressure unit, the second row input that grid is electric resistance partial pressure unit of the 19th NMOS tube N19, The third line input that grid is electric resistance partial pressure unit of the 20th NMOS tube N20, the grid of the 21st NMOS tube N21 is electricity Resistance partial pressure unit fourth line input, the source electrode of the 18th NMOS tube N18, the source electrode of the 19th NMOS tube N19, the 20th The drain electrode of the source electrode of NMOS tube N20, the source electrode of the 21st NMOS tube N21 and the 22nd NMOS tube N22 connects, and the 22nd The source electrode of NMOS tube N22 is the outfan of electric resistance partial pressure unit；The first row input of the first electric resistance partial pressure unit cell1, The first row input of two electric resistance partial pressure unit cell2, the first row input of the 3rd electric resistance partial pressure unit cell3, the 4th electricity The first row input of resistance partial pressure unit cell4 and the first outfan of a 2-4 decoder connect, the first electric resistance partial pressure unit The second row input of cell1, the second row input of the second electric resistance partial pressure unit cell2, the 3rd electric resistance partial pressure unit cell3 The second row input, the second row input of the 4th electric resistance partial pressure unit cell4 and the second outfan of a 2-4 decoder Connect, the third line input of the first electric resistance partial pressure unit cell1, the third line input of the second electric resistance partial pressure unit cell2, The third line input of the 3rd electric resistance partial pressure unit cell3, the third line input and first of the 4th electric resistance partial pressure unit cell4 3rd outfan of 2-4 decoder connects, the fourth line input of the first electric resistance partial pressure unit cell1, the second electric resistance partial pressure list Unit the fourth line input of cell2, the fourth line input of the 3rd electric resistance partial pressure unit cell3, the 4th electric resistance partial pressure unit 4th outfan of the fourth line input of cell4 and a 2-4 decoder connects, the of the first electric resistance partial pressure unit cell1 String input, the first row input of the second electric resistance partial pressure unit cell2, the first row of the 3rd electric resistance partial pressure unit cell3 First outfan of input, the first row input of the 4th electric resistance partial pressure unit cell4 and the 2nd 2-4 decoder connects, the The secondary series input of one electric resistance partial pressure unit cell1, the secondary series input of the second electric resistance partial pressure unit cell2, the 3rd electricity The resistance secondary series input of partial pressure unit cell3, the secondary series input of the 4th electric resistance partial pressure unit cell4 and the 2nd 2-4 translate Second outfan of code device connects, the 3rd row input of the first electric resistance partial pressure unit cell1, the second electric resistance partial pressure unit The 3rd row input of cell2, the 3rd row input of the 3rd electric resistance partial pressure unit cell3, the 4th electric resistance partial pressure unit cell4 The 3rd row input and the 2nd 2-4 decoder the 3rd outfan connect, the first electric resistance partial pressure unit cell1 the 4th row defeated Enter end, the 4th row input of the second electric resistance partial pressure unit cell2, the 4th row input of the 3rd electric resistance partial pressure unit cell3, The 4th row input of the 4th electric resistance partial pressure unit cell4 and the 4th outfan of the 2nd 2-4 decoder connect, and the first resistance divides The input of pressure unit cell1 and the first outfan of the 3rd 2-4 decoder connect, and the second electric resistance partial pressure unit cell2's is defeated The second outfan entering end and the 3rd 2-4 decoder connects, and input and the 3rd 2-4 of the 3rd electric resistance partial pressure unit cell3 translate 3rd outfan of code device connects, the input of the 4th electric resistance partial pressure unit cell4 and the 4th outfan of the 3rd 2-4 decoder Connect, the outfan of the first electric resistance partial pressure unit cell1, the outfan of the second electric resistance partial pressure unit cell2, the 3rd electric resistance partial pressure The normal phase input end of the outfan of unit cell3, the outfan of the 4th electric resistance partial pressure unit cell4 and operational amplifier OA is even Connecing, the inverting input of operational amplifier and the outfan of operational amplifier connect and its connection end is electric resistance partial pressure type DAC Outfan, the first input end that input is electric resistance partial pressure type DAC of a 2-4 decoder, the input of the 2nd 2-4 decoder For the second input of electric resistance partial pressure type DAC, the 3rd input that input is electric resistance partial pressure type DAC of the 3rd 2-4 decoder, The clock end of the clock end of the oneth 2-4 decoder, the clock end of the 2nd 2-4 decoder and the 3rd 2-4 decoder connects and it connects Connecing the end clock end for electric resistance partial pressure type DAC, the reference voltage input terminal of the first electric resistance partial pressure unit cell1, the second resistance divide The pressure reference voltage input terminal of unit cell2, the reference voltage input terminal of the 3rd electric resistance partial pressure unit cell3 and the 4th resistance divide The reference voltage input terminal of pressure unit cell4 connects and it connects the reference voltage input terminal that end is electric resistance partial pressure type DAC；Input First outfan of depositor and the 3rd input of the first electric resistance partial pressure type DAC connect, the second outfan of input register Being connected with the first input end of the first electric resistance partial pressure type DAC and the first input end of the second electric resistance partial pressure type DAC respectively, input is posted 3rd outfan of storage respectively with second input and the second of the second electric resistance partial pressure type DAC of the first electric resistance partial pressure type DAC Input connects, and the 4th outfan of input register and the 3rd input of the second electric resistance partial pressure type DAC connect, sequencing contro Device is connected with the clock end of the first electric resistance partial pressure type DAC and the clock end of the second electric resistance partial pressure type DAC respectively, the first electric resistance partial pressure The outfan of type DAC and the first input end of voltage comparator connect, and the outfan of the second electric resistance partial pressure type DAC and voltage ratio are relatively Second input of device connects；The reference voltage input terminal of the first electric resistance partial pressure type DAC and the reference of the second electric resistance partial pressure type DAC Voltage input end all accesses reference voltage V_ref, V_refSize is 1.2V.

Embodiment two: as shown in FIG. 1 to 3, a kind of electric resistance partial pressure type DAC-PUF circuit, including input register, deviation Voltage generation circuit, voltage comparator and time schedule controller, input register have clock end, input, the first outfan, Two outfans, the 3rd outfan and the 4th outfan, voltage comparator have clock end, first input end, the second input and Outfan, time schedule controller is connected with the clock end of input register and the clock end of voltage comparator respectively, and deviation voltage produces Raw circuit includes two electric resistance partial pressure types DAC that structure is identical, and electric resistance partial pressure type DAC includes the 2-4 decoding that three structures are identical The electric resistance partial pressure unit that device, operational amplifier and four structures are identical, 2-4 decoder has clock end, input, the first output End, the second outfan, the 3rd outfan and the 4th outfan, operational amplifier has normal phase input end, inverting input and defeated Going out end, three 2-4 decoders are respectively a 2-4 decoder, the 2nd 2-4 decoder and the 3rd 2-4 decoder, and four resistance divide Pressure unit is respectively the first electric resistance partial pressure unit cell1, the second electric resistance partial pressure unit cell2, the 3rd electric resistance partial pressure unit cell3 With the 4th electric resistance partial pressure unit cell4；Electric resistance partial pressure unit includes the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5, the 6th NMOS tube N6, the 7th NMOS tube N7, the 8th NMOS tube N8, the 9th NMOS Pipe N9, the tenth NMOS tube N10, the 11st NMOS tube N11, the 12nd NMOS tube N12, the 13rd NMOS tube N13, the 14th NMOS Pipe N14, the 15th NMOS tube N15, the 16th NMOS tube N16, the 17th NMOS tube N17, the 18th NMOS tube N18, the 19th NMOS tube N19, the 20th NMOS tube N20, the 21st NMOS tube N21, the 22nd NMOS tube N22, the first resistance R1, second Resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th Resistance R9, the tenth resistance R10, the 11st resistance R11, the 12nd resistance R12, the 13rd resistance R13, the 14th resistance R14, 15 resistance R15, the 16th resistance R16 and the 17th resistance R17；The grid of the first NMOS tube N1, the grid of the second NMOS tube N2 The grid of pole, the grid of the 3rd NMOS tube N3 and the 4th NMOS tube N4 connects and it connects the first row that end is electric resistance partial pressure unit Input, the grid of the 5th NMOS tube N5, the grid of the 6th NMOS tube N6, the grid of the 7th NMOS tube N7 and the 8th NMOS tube N8 Grid connect and its to connect end be the secondary series input of electric resistance partial pressure unit, the grid of the 9th NMOS tube N9, the tenth NMOS The grid of the grid of pipe N10, the grid of the 11st NMOS tube N11 and the 12nd NMOS tube N12 connects and its connection end is resistance 3rd row input of partial pressure unit, the grid of the 13rd NMOS tube N13, the grid of the 14th NMOS tube N14, the 15th NMOS The grid of pipe N15 and the grid of the 16th NMOS tube N16 connect and it connects the 4th row input that end is electric resistance partial pressure unit, One end of the source electrode of the first NMOS tube N1, one end of the first resistance R1 and the second resistance R2 connects, the other end of the first resistance R1 Ground connection, one end of the source electrode of the second NMOS tube N2, the other end of the second resistance R2 and the 3rd resistance R3 connects, the 3rd NMOS tube N3 Source electrode, the other end of the 3rd resistance R3 and the 4th resistance R4 one end connect, the source electrode of the 4th NMOS tube N4, the 4th resistance R4 The other end and the 5th resistance R5 one end connect, the drain electrode of the 5th NMOS tube N5, the other end of the 5th resistance R5 and the 6th electricity One end of resistance R6 connects, and one end of the drain electrode of the 6th NMOS tube N6, the other end of the 6th resistance R6 and the 7th resistance R7 connects, the One end of the drain electrode of seven NMOS tube N7, the other end of the 7th resistance R7 and the 8th resistance R8 connects, the drain electrode of the 8th NMOS tube N8, One end of the other end of the 8th resistance R8 and the 9th resistance R9 connects, the source electrode of the 9th NMOS tube N9, the 9th resistance R9 another One end of end and the tenth resistance R10 connects, the source electrode of the tenth NMOS tube N10, the other end of the tenth resistance R10 and the 11st resistance One end of R11 connects, the source electrode of the 11st NMOS tube N11, the other end of the 11st resistance R11 and the one of the 12nd resistance R12 End connects, and one end of the source electrode of the 12nd NMOS tube N12, the other end of the 12nd resistance R12 and the 13rd resistance R13 connects, One end of the drain electrode of the 13rd NMOS tube N13, the other end of the 13rd resistance R13 and the 14th resistance R14 connects, and the 14th One end of the drain electrode of NMOS tube N14, the other end of the 14th resistance R14 and the 15th resistance R15 connects, the 15th NMOS tube One end of the drain electrode of N15, the other end of the 15th resistance R15 and the 16th resistance R16 connects, the leakage of the 16th NMOS tube N16 One end of pole, the other end of the 16th resistance R16 and the 17th resistance R17 connects, the other end and the tenth of the 17th resistance R17 The source electrode of seven NMOS tube N17 connects, the reference voltage input terminal that drain electrode is electric resistance partial pressure unit of the 17th NMOS tube N17, the The grid of 17 NMOS tube N17 and the grid of the 22nd NMOS tube N22 connect and its connection end is the defeated of electric resistance partial pressure unit Enter end, the drain electrode of the first NMOS tube N1, the source electrode of the 8th NMOS tube N8, the drain electrode of the 9th NMOS tube N9, the 16th NMOS tube N16 Source electrode and the 18th NMOS tube N18 drain electrode connect, the drain electrode of the second NMOS tube N2, the source electrode of the 7th NMOS tube N7, the tenth The drain electrode of the drain electrode of NMOS tube N10, the source electrode of the 15th NMOS tube N15 and the 19th NMOS tube N19 connects, the 3rd NMOS tube N3 Drain electrode, the source electrode of the 6th NMOS tube N6, the drain electrode of the 11st NMOS tube N11, the source electrode and the 20th of the 14th NMOS tube N14 The drain electrode of NMOS tube N20 connects, the drain electrode of the 4th NMOS tube N4, the source electrode of the 5th NMOS tube N5, the leakage of the 12nd NMOS tube N12 The drain electrode of pole, the source electrode of the 13rd NMOS tube N13 and the 21st NMOS tube N21 connects, and the grid of the 18th NMOS tube N18 is The first row input of electric resistance partial pressure unit, the second row input that grid is electric resistance partial pressure unit of the 19th NMOS tube N19, The third line input that grid is electric resistance partial pressure unit of the 20th NMOS tube N20, the grid of the 21st NMOS tube N21 is electricity Resistance partial pressure unit fourth line input, the source electrode of the 18th NMOS tube N18, the source electrode of the 19th NMOS tube N19, the 20th The drain electrode of the source electrode of NMOS tube N20, the source electrode of the 21st NMOS tube N21 and the 22nd NMOS tube N22 connects, and the 22nd The source electrode of NMOS tube N22 is the outfan of electric resistance partial pressure unit；The first row input of the first electric resistance partial pressure unit cell1, The first row input of two electric resistance partial pressure unit cell2, the first row input of the 3rd electric resistance partial pressure unit cell3, the 4th electricity The first row input of resistance partial pressure unit cell4 and the first outfan of a 2-4 decoder connect, the first electric resistance partial pressure unit The second row input of cell1, the second row input of the second electric resistance partial pressure unit cell2, the 3rd electric resistance partial pressure unit cell3 The second row input, the second row input of the 4th electric resistance partial pressure unit cell4 and the second outfan of a 2-4 decoder Connect, the third line input of the first electric resistance partial pressure unit cell1, the third line input of the second electric resistance partial pressure unit cell2, The third line input of the 3rd electric resistance partial pressure unit cell3, the third line input and first of the 4th electric resistance partial pressure unit cell4 3rd outfan of 2-4 decoder connects, the fourth line input of the first electric resistance partial pressure unit cell1, the second electric resistance partial pressure list Unit the fourth line input of cell2, the fourth line input of the 3rd electric resistance partial pressure unit cell3, the 4th electric resistance partial pressure unit 4th outfan of the fourth line input of cell4 and a 2-4 decoder connects, the of the first electric resistance partial pressure unit cell1 String input, the first row input of the second electric resistance partial pressure unit cell2, the first row of the 3rd electric resistance partial pressure unit cell3 First outfan of input, the first row input of the 4th electric resistance partial pressure unit cell4 and the 2nd 2-4 decoder connects, the The secondary series input of one electric resistance partial pressure unit cell1, the secondary series input of the second electric resistance partial pressure unit cell2, the 3rd electricity The resistance secondary series input of partial pressure unit cell3, the secondary series input of the 4th electric resistance partial pressure unit cell4 and the 2nd 2-4 translate Second outfan of code device connects, the 3rd row input of the first electric resistance partial pressure unit cell1, the second electric resistance partial pressure unit The 3rd row input of cell2, the 3rd row input of the 3rd electric resistance partial pressure unit cell3, the 4th electric resistance partial pressure unit cell4 The 3rd row input and the 2nd 2-4 decoder the 3rd outfan connect, the first electric resistance partial pressure unit cell1 the 4th row defeated Enter end, the 4th row input of the second electric resistance partial pressure unit cell2, the 4th row input of the 3rd electric resistance partial pressure unit cell3, The 4th row input of the 4th electric resistance partial pressure unit cell4 and the 4th outfan of the 2nd 2-4 decoder connect, and the first resistance divides The input of pressure unit cell1 and the first outfan of the 3rd 2-4 decoder connect, and the second electric resistance partial pressure unit cell2's is defeated The second outfan entering end and the 3rd 2-4 decoder connects, and input and the 3rd 2-4 of the 3rd electric resistance partial pressure unit cell3 translate 3rd outfan of code device connects, the input of the 4th electric resistance partial pressure unit cell4 and the 4th outfan of the 3rd 2-4 decoder Connect, the outfan of the first electric resistance partial pressure unit cell1, the outfan of the second electric resistance partial pressure unit cell2, the 3rd electric resistance partial pressure The normal phase input end of the outfan of unit cell3, the outfan of the 4th electric resistance partial pressure unit cell4 and operational amplifier connects, The inverting input of operational amplifier and the outfan of operational amplifier connect and it connects the output that end is electric resistance partial pressure type DAC End, the first input end that input is electric resistance partial pressure type DAC of a 2-4 decoder, the input of the 2nd 2-4 decoder is electricity Second input of resistance dividing potential drop type DAC, the 3rd input that input is electric resistance partial pressure type DAC of the 3rd 2-4 decoder, first The clock end of the clock end of 2-4 decoder, the clock end of the 2nd 2-4 decoder and the 3rd 2-4 decoder connects and it connects end For the clock end of electric resistance partial pressure type DAC, the reference voltage input terminal of the first electric resistance partial pressure unit cell1, the second electric resistance partial pressure list Unit's reference voltage input terminal of cell2, the reference voltage input terminal of the 3rd electric resistance partial pressure unit cell3 and the 4th electric resistance partial pressure list The reference voltage input terminal of unit cell4 connects and it connects the reference voltage input terminal that end is electric resistance partial pressure type DAC；Input is deposited First outfan of device and the 3rd input of the first electric resistance partial pressure type DAC connect, and the second outfan of input register is respectively It is connected with the first input end of the first electric resistance partial pressure type DAC and the first input end of the second electric resistance partial pressure type DAC, input register The 3rd outfan respectively with the second input of the first electric resistance partial pressure type DAC and the second input of the second electric resistance partial pressure type DAC End connects, and the 4th outfan of input register and the 3rd input of the second electric resistance partial pressure type DAC connect, and time schedule controller divides It is not connected with the clock end of the first electric resistance partial pressure type DAC and the clock end of the second electric resistance partial pressure type DAC, the first electric resistance partial pressure type The outfan of DAC and the first input end of voltage comparator connect, the outfan of the second electric resistance partial pressure type DAC and voltage comparator Second input connect；The reference voltage input terminal of the first electric resistance partial pressure type DAC and the reference electricity of the second electric resistance partial pressure type DAC Pressure input all accesses reference voltage V_ref, V_refSize is 1.2V.

As shown in Figure 4, in the present embodiment, voltage comparator includes the first PMOS P1, the second PMOS P2, the 3rd PMOS Pipe P3, the 4th PMOS P4, the 23rd NMOS tube N23, the 24th NMOS tube N24, the 25th NMOS tube N25, second 16 NMOS tube N26, the 27th NMOS tube N27, the 28th NMOS tube N28 and RS latch；RS latch includes first Two input nand gate T1 and the two or two input nand gate T2, the one or two input nand gate T1 and the two or two input nand gate T2 all have There are first input end, the second input and outfan；The source electrode of the first PMOS P1, the source electrode of the second PMOS P2, the 3rd The source electrode of PMOS P3 and the source electrode of the 4th PMOS P4 all access power supply, the grid of the first PMOS P1, the 23rd NMOS The grid of the grid of pipe N23, the grid of the 24th NMOS tube N24 and the 4th PMOS P4 connects and its connection end is voltage ratio The clock end of relatively device, the drain electrode of the first PMOS P1, the drain electrode of the second PMOS P2, the grid of the 3rd PMOS P3, the 20th The drain electrode of three NMOS tube N23 and the first input end of the one or two input nand gate T1 connect, the drain electrode of the 3rd PMOS P3, second The grid of PMOS P2, the drain electrode of the 4th PMOS P4, the drain electrode of the 24th NMOS tube N24 and the two or two input nand gate T2 Second input connect, the source electrode of the 23rd NMOS tube N23, the drain electrode of the 25th NMOS tube N25, the 26th NMOS The drain electrode of pipe N26 and the grid of the 27th NMOS tube N27 connect, the source electrode of the 24th NMOS tube N24, the 26th NMOS The drain electrode of the grid of pipe N26, the drain electrode of the 27th NMOS tube N27 and the 28th NMOS tube N28 connects, the 25th NMOS The source electrode of pipe N25, the source electrode of the 26th NMOS tube N26, the source electrode of the 27th NMOS tube N27 and the 28th NMOS tube The source grounding of N28, the first input end that grid is voltage comparator of the 25th NMOS tube N25, the 28th NMOS The grid of pipe N28 is the second input of voltage comparator, second input of the one or two input nand gate T1 and the two or two defeated The outfan entering NAND gate T2 connects, and the first input end of the two or two input nand gate T2 and the one or two input nand gate T1's is defeated Go out end connection and its connection end is the outfan of voltage comparator.

As it is shown in figure 5, in the present embodiment, time schedule controller includes the one or two input and door AND1, the two or two input and door AND2, the first phase inverter A1, the second phase inverter A2, the 3rd phase inverter A3 and the 4th phase inverter A4；One or two input and door AND1 Being respectively provided with first input end, the second input and outfan with the two or two input with door AND2, the one or two input is with door AND1's First input end is the first Enable Pin of time schedule controller, is used for accessing input register and enables signal, the one or two input and door Second input of AND1 and the two or two input are connected with the first input end of door AND2 and its connection end is time schedule controller Clock end, for incoming clock signal, the two or two input enables with the second input is time schedule controller the second of door AND2 End, is used for accessing voltage comparator and enables signal, the one or two input and the outfan of door AND1 and the input of the first phase inverter A1 End connects, and the outfan of the first phase inverter A1 and the input of the second phase inverter A2 connect, and the outfan of the second phase inverter A2 is First outfan of time schedule controller, the first outfan of time schedule controller and the clock end of input register connect, and the two or two Input is connected with the outfan of door AND2 and the input of the 3rd phase inverter A3, the outfan of the 3rd phase inverter A3 and the 4th anti-phase The input of device A4 connects, second outfan that outfan is time schedule controller of the 4th phase inverter A4, the of time schedule controller Two outfans respectively with clock end, the clock end of the first electric resistance partial pressure type DAC and second electric resistance partial pressure type DAC of voltage comparator Clock end connect.

As shown in Figure 6, in the present embodiment, input register includes the first d type flip flop D1, the second d type flip flop D2, the 3rd D Trigger D3, four d flip-flop D4, the 5th d type flip flop D5, the 6th d type flip flop D6, the 7th d type flip flop D7 and the 8th d type flip flop D8；First d type flip flop D1, the second d type flip flop D2,3d flip-flop D3, four d flip-flop D4, the 5th d type flip flop D5, the 6th D type flip flop D6, the 7th d type flip flop D7 and the 8th d type flip flop D8 are respectively provided with input, clock end and outfan；First d type flip flop The clock end of D1, the clock end of the second d type flip flop D2, the clock end of 3d flip-flop D3, the clock end of four d flip-flop D4, The clock end of the 5th d type flip flop D5, the clock end of the 6th d type flip flop D6, the clock end of the 7th d type flip flop D7 and the 8th D trigger The clock end of device D8 connects and it connects the clock end that end is input register, and the input of the first d type flip flop D1, the 2nd D touch Send out the input of device D2, the input of 3d flip-flop D3, the input of four d flip-flop D4, the 5th d type flip flop D5 defeated Enter end, the input of the 6th d type flip flop D6, the input of the 7th d type flip flop D7 and the 8th d type flip flop D8 clock end connect and It connects end is the input of input register, and the outfan of the first d type flip flop D1 and the outfan of the second d type flip flop D2 connect And it connects the first outfan that end is input register, the outfan of 3d flip-flop D3 and the output of four d flip-flop D4 End connects and it connects the second outfan that end is input register, the outfan of the 5th d type flip flop D5 and the 6th d type flip flop D6 Outfan connect and its to connect end be the 3rd outfan of input register, the outfan of the 7th d type flip flop D7 and the 8th D touch Send out the 4th outfan that outfan connects and its connection end is input register of device D8.

Full custom mode is used to make electric resistance partial pressure type DAC-PUF of the present invention under TSMC-LP 65nm CMOS technology Circuit.Utilize Spectre that the electric resistance partial pressure type DAC-PUF circuit of the present invention is carried out Computer Simulation, test its output respectively Uniqueness, randomness and the reliability of response.

Uniqueness characterizes the PUF circuit any individual of same structure and the discrimination of other individualities, i.e. produces unique mark The ability of self digital information. generally use under statistics the same terms, Hamming distance between the output response of same PUF circuit Different Individual Mode from (Hamming Distance, HD) is weighed, and ideally its value is 50%.For the accuracy tested, choose 256 groups of differences excitation (often group encourages a length of 8 bits, does not repeats), electric resistance partial pressure type to the present invention under each group of excitation DAC-PUF circuit carries out 10000 Monte Carlo emulation, then obtains the output response of 10000 a length of 256 bits, Calculate the HD between each response.Hamming distance statistical result figure such as Fig. 7 institute between the sheet of the electric resistance partial pressure type DAC-PUF circuit of the present invention Show.As shown in Figure 7, the bell-like distribution of HD between the electric resistance partial pressure type DAC-PUF circuit Different Individual output response of the present invention, E (HD_inter) it is 51.3%, close to ideal value.

Randomness characterizes logical zero and the distribution situation of logic 1 in PUF circuit output data.Ideally, PUF circuit Output logical zero is identical with the probability of logic 1, and now randomness is 100%.The randomness of PUF circuit output data can pass through formula (1) calculate:

Randomness=(1-| 2P (r=1)-1) × 100% (1)

Wherein, the probability of logic 1 during P (r=1) represents output data.

Choose the excitation that 8 groups of Hamming weights (Hamming Weight, HW) gradually add 1, to it at different temperatures and voltage Lower carry out 10000 Monte Carlo emulation respectively, seek under every kind of environment the meansigma methods of logic 1 in response, and by formula (1) Calculate randomness.Statistical result is as shown in Figure 8. and carried PUF circuit is in different temperatures (voltage is 1.2V) and work Under voltage (temperature is 25 DEG C), randomness is all higher than 99.1%.

Reliability is as the important performance indexes of PUF circuit, for PUF circuit property in different operating environment is described Energy. under m contrast_environment, the reliability of PUF circuit can be passed through formula (2) and weigh.

$\mathrm{Re}liability=1-E\left({\mathrm{HD}}_{\mathrm{int}ra}\right)=(1-\frac{1}{m}\underset{l=1}{\overset{m}{\Σ}}\frac{HD(r_0,r_l)}{n})\×100\%---\left(2\right)$

Wherein, E (HD_intra) represent Hamming distance in average sheet, r₀And r_lIt is illustrated respectively under ideal operation environment The output response of a length of n-bit under (1.2V/25 DEG C) and other contrast_environments.

First, under the conditions of 1.2V/25 DEG C, circuit applies 256 groups of difference excitations, and (often group encourages a length of 8 bits, no Repeat), thus obtain the output of 256 bit long, in this, as reference response. then, make circuit be operated in different temperature and Under voltage, apply the excitation identical with reference response, add up the figure place that its output response changes relative to reference response, and pass through Formula (2) calculates reliability.Shown in statistical result such as Fig. 9 (a) and Fig. 9 (b), Fig. 9 (a) represents electric resistance partial pressure type DAC-of the present invention The reliability variation with temperature situation of PUF circuit, Fig. 9 (b) represents the reliable of the electric resistance partial pressure type DAC-PUF circuit of the present invention Property is with the situation of change of voltage, it is seen that carried PUF circuit be operated in different temperatures (-40～125 DEG C) and voltage (1.08～ Reliability under 1.32V) is respectively 98.5% and 97.8%.

The electric resistance partial pressure type DAC-PUF circuit of the present invention is contrasted with other types PUF circuit performance, its performance comparison number According to as shown in table 1.

Table 1 dissimilar PUF circuit performance contrast table

Analytical table 1 understands, the electric resistance partial pressure type DAC-PUF circuit of the present invention in the case of bigger temperature and change in voltage, Still ensure that higher reliability.

Test result indicate that, the electric resistance partial pressure type DAC-PUF circuit uniqueness of the present invention is strong, and under different operating environment Randomness and reliability are respectively greater than 99.1% and 97.8%, can be widely applied to the fields such as key generation and device authentication.

Claims (4)

1. an electric resistance partial pressure type DAC-PUF circuit, including input register, deviation voltage produce circuit, voltage comparator and Time schedule controller, described input register has clock end, input, the first outfan, the second outfan, the 3rd outfan With the 4th outfan, described voltage comparator has clock end, first input end, the second input and outfan, described Time schedule controller is connected with the clock end of described input register and the clock end of described voltage comparator respectively, its feature It is that described deviation voltage produces circuit and includes two electric resistance partial pressure types DAC that structure is identical, described electric resistance partial pressure type DAC Including the electric resistance partial pressure unit that 2-4 decoder, operational amplifier and four structures that three structures are identical are identical, described 2-4 Decoder has clock end, input, the first outfan, the second outfan, the 3rd outfan and the 4th outfan, described fortune Calculating amplifier and have normal phase input end, inverting input and outfan, three described 2-4 decoder the respectively the oneth 2-4 translate Code device, the 2nd 2-4 decoder and the 3rd 2-4 decoder, four described electric resistance partial pressure unit are respectively the first electric resistance partial pressure list Unit, the second electric resistance partial pressure unit, the 3rd electric resistance partial pressure unit and the 4th electric resistance partial pressure unit；

Described electric resistance partial pressure unit include the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, 12 NMOS tube, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS tube, the 22nd NMOS tube, the first electricity Resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance, Ten resistance, the 11st resistance, the 12nd resistance, the 13rd resistance, the 14th resistance, the 15th resistance, the 16th resistance and 17 resistance；The grid of the first described NMOS tube, the grid of the second described NMOS tube, the grid of the 3rd described NMOS tube Connect with the grid of the 4th described NMOS tube and it connects the first row input that end is described electric resistance partial pressure unit, described The grid of the 5th NMOS tube, the grid of the 6th described NMOS tube, the grid and the described the 8th of the 7th described NMOS tube The grid of NMOS tube connects and it connects the secondary series input that end is described electric resistance partial pressure unit, the 9th described NMOS tube Grid, the grid of the tenth described NMOS tube, the grid of the 11st described NMOS tube and the 12nd described NMOS tube Grid connects and it connects the 3rd row input that end is described electric resistance partial pressure unit, the grid of the 13rd described NMOS tube Pole, the grid of the 14th described NMOS tube, the grid of the 15th described NMOS tube and the grid of the 16th described NMOS tube Pole connects and it connects the 4th row input that end is described electric resistance partial pressure unit, the source electrode of the first described NMOS tube, institute The one end of the first resistance stated and one end of the second described resistance connect, and the other end ground connection of the first described resistance is described One end of the source electrode of the second NMOS tube, the other end of the second described resistance and the 3rd described resistance connect, described the One end of the source electrode of three NMOS tube, the other end of the 3rd described resistance and the 4th described resistance connects, described the 4th One end of the source electrode of NMOS tube, the other end of the 4th described resistance and the 5th described resistance connects, the 5th described NMOS One end of the drain electrode of pipe, the other end of the 5th described resistance and the 6th described resistance connects, the 6th described NMOS tube One end of drain electrode, the other end of described 6th resistance and the 7th described resistance connects, the drain electrode of the 7th described NMOS tube, One end of the other end of the 7th described resistance and the 8th described resistance connects, the drain electrode of the 8th described NMOS tube, described The other end of the 8th resistance and one end of the 9th described resistance connect, the source electrode of the 9th described NMOS tube, described the One end of the other end of nine resistance and the tenth described resistance connects, the described source electrode of the tenth NMOS tube, the described the tenth electricity The other end of resistance and one end of the 11st described resistance connect, the described source electrode of the 11st NMOS tube, the described the 11st One end of the other end of resistance and the 12nd described resistance connects, the described source electrode of the 12nd NMOS tube, the described the tenth One end of the other end of two resistance and the 13rd described resistance connects, the drain electrode of the 13rd described NMOS tube, described the One end of the other end of 13 resistance and the 14th described resistance connects, the drain electrode of the 14th described NMOS tube, described One end of the other end of the 14th resistance and the 15th described resistance connects, the drain electrode of the 15th described NMOS tube, described The other end of the 15th resistance and one end of the 16th described resistance connect, the described drain electrode of the 16th NMOS tube, institute One end of the other end of the 16th resistance stated and the 17th described resistance connects, the other end of the 17th described resistance and The source electrode of the 17th described NMOS tube connects, the ginseng that drain electrode is described electric resistance partial pressure unit of the 17th described NMOS tube Examining voltage input end, the grid of the 17th described NMOS tube and the grid of the 22nd described NMOS tube connect and it connects The input that end is described electric resistance partial pressure unit, the drain electrode of the first described NMOS tube, the source electrode of the 8th described NMOS tube, The drain electrode of the drain electrode of the 9th described NMOS tube, the source electrode of the 16th described NMOS tube and the 18th described NMOS tube is even Connect, the drain electrode of the second described NMOS tube, the source electrode of the 7th described NMOS tube, the drain electrode of the tenth described NMOS tube, described The source electrode of the 15th NMOS tube and the drain electrode of the 19th described NMOS tube connect, the described drain electrode of the 3rd NMOS tube, institute The source electrode of the 6th NMOS tube stated, the drain electrode of the 11st described NMOS tube, the source electrode of the 14th described NMOS tube and described The drain electrode of the 20th NMOS tube connect, the drain electrode of the 4th described NMOS tube, the source electrode of the 5th described NMOS tube, described The drain electrode of the drain electrode of the 12nd NMOS tube, the source electrode of the 13rd described NMOS tube and the 21st described NMOS tube connects, The first row input that grid is described electric resistance partial pressure unit of the 18th described NMOS tube, the 19th described NMOS tube The second row input that grid is described electric resistance partial pressure unit, the grid of the 20th described NMOS tube is described resistance The third line input of partial pressure unit, the fourth line that grid is described electric resistance partial pressure unit of the 21st described NMOS tube Input, the source electrode of the 18th described NMOS tube, the source electrode of the 19th described NMOS tube, the 20th described NMOS tube The drain electrode of source electrode, the source electrode of the 21st described NMOS tube and the 22nd described NMOS tube connects, described the 20th The source electrode of two NMOS tube is the outfan of described electric resistance partial pressure unit；

The first row input of the first described electric resistance partial pressure unit, the first row input of the second described electric resistance partial pressure unit End, the described the first row input of the 3rd electric resistance partial pressure unit, the first row input of the 4th described electric resistance partial pressure unit Connect with the first outfan of a described 2-4 decoder, the second row input of the first described electric resistance partial pressure unit, institute Second row input of the second electric resistance partial pressure unit stated, the second row input of the 3rd described electric resistance partial pressure unit, described The second row input of the 4th electric resistance partial pressure unit and the second outfan of a described 2-4 decoder connect, described The third line input of the first electric resistance partial pressure unit, the third line input of the second described electric resistance partial pressure unit, described The third line input of three electric resistance partial pressure unit, the third line input and described first of the 4th described electric resistance partial pressure unit 3rd outfan of 2-4 decoder connects, the fourth line input of the first described electric resistance partial pressure unit, the second described resistance The fourth line input of partial pressure unit, the fourth line input of the 3rd described electric resistance partial pressure unit, the 4th described resistance divide The fourth line input of pressure unit and the 4th outfan of a described 2-4 decoder connect, the first described electric resistance partial pressure The first row input of unit, the first row input of the second described electric resistance partial pressure unit, the 3rd described electric resistance partial pressure list First row input, the first row input of the 4th described electric resistance partial pressure unit and the 2nd described 2-4 decoder of unit First outfan connects, the secondary series input of the first described electric resistance partial pressure unit, the second described electric resistance partial pressure unit Secondary series input, the secondary series input of the 3rd described electric resistance partial pressure unit, the of the 4th described electric resistance partial pressure unit Second outfan of two row inputs and the 2nd described 2-4 decoder connects, the 3rd of the first described electric resistance partial pressure unit Row input, described the 3rd row input of the second electric resistance partial pressure unit, the 3rd row of the 3rd described electric resistance partial pressure unit Input, the 3rd row input of the 4th described electric resistance partial pressure unit and the 3rd outfan of the 2nd described 2-4 decoder Connect, the 4th row input of the first described electric resistance partial pressure unit, the 4th row input of the second described electric resistance partial pressure unit End, described the 4th row input of the 3rd electric resistance partial pressure unit, the 4th row input of the 4th described electric resistance partial pressure unit Connect with the 4th outfan of the 2nd described 2-4 decoder, the input of the first described electric resistance partial pressure unit and described First outfan of the 3rd 2-4 decoder connects, and input and the 3rd described 2-4 of the second described electric resistance partial pressure unit translate Second outfan of code device connects, the of the input of the 3rd described electric resistance partial pressure unit and the 3rd described 2-4 decoder Three outfans connect, the input of the 4th described electric resistance partial pressure unit and the 4th outfan of the 3rd described 2-4 decoder Connect, the outfan of the first described electric resistance partial pressure unit, the described outfan of the second electric resistance partial pressure unit, the described the 3rd The positive of the outfan of electric resistance partial pressure unit, the outfan of the 4th described electric resistance partial pressure unit and described operational amplifier is defeated Entering end to connect, the inverting input of described operational amplifier and the outfan of described operational amplifier connect and it connects end For the outfan of described electric resistance partial pressure type DAC, the input of a described 2-4 decoder is described electric resistance partial pressure type The first input end of DAC, second input that input is described electric resistance partial pressure type DAC of the 2nd described 2-4 decoder, The 3rd input that input is described electric resistance partial pressure type DAC of the 3rd described 2-4 decoder, a described 2-4 translates The clock end of the code clock end of device, the clock end of the 2nd described 2-4 decoder and the 3rd described 2-4 decoder connects and it Connecting end is the clock end of described electric resistance partial pressure type DAC, the described reference voltage input terminal of the first electric resistance partial pressure unit, institute The reference voltage input terminal of the second electric resistance partial pressure unit stated, the reference voltage input terminal of the 3rd described electric resistance partial pressure unit and The reference voltage input terminal of the 4th described electric resistance partial pressure unit connects and it connects the ginseng that end is described electric resistance partial pressure type DAC Examine voltage input end；

First outfan of described input register and the 3rd input of the first described electric resistance partial pressure type DAC connect, institute Second outfan of the input register stated respectively with the first input end of the first described electric resistance partial pressure type DAC and described The first input end of two electric resistance partial pressure types DAC connects, and the 3rd outfan of described input register is respectively with described first Second input of electric resistance partial pressure type DAC and the second input of the second described electric resistance partial pressure type DAC connect, described input 4th outfan of depositor and the 3rd input of the second described electric resistance partial pressure type DAC connect, described time schedule controller Clock end with the clock end of the first described electric resistance partial pressure type DAC and the second described electric resistance partial pressure type DAC is connected respectively, institute The outfan of the first electric resistance partial pressure type DAC stated and the first input end of described voltage comparator connect, the second described electricity The outfan of resistance dividing potential drop type DAC and the second input of described voltage comparator connect.

A kind of electric resistance partial pressure type DAC-PUF circuit the most according to claim 1, it is characterised in that described voltage comparator Including the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the 23rd NMOS tube, the 24th NMOS Pipe, the 25th NMOS tube, the 26th NMOS tube, the 27th NMOS tube, the 28th NMOS tube and RS latch；Described RS latch include the one or two input nand gate and the two or two input nand gate, the one or two described input nand gate and described The two or two input nand gate be respectively provided with first input end, the second input and outfan；

The source electrode of the first described PMOS, the source electrode of the second described PMOS, the source electrode of the 3rd described PMOS and institute The source electrode of the 4th PMOS stated all accesses power supply, the grid of the first described PMOS, the 23rd described NMOS tube The grid of grid, the grid of the 24th described NMOS tube and the 4th described PMOS connects and its connection end is described The clock end of voltage comparator, the drain electrode of the first described PMOS, the drain electrode of the second described PMOS, the described the 3rd The first input end of the grid of PMOS, the drain electrode of the 23rd described NMOS tube and the one or two described input nand gate is even Connect, the drain electrode of the 3rd described PMOS, the grid of the second described PMOS, the drain electrode of the 4th described PMOS, described The drain electrode of the 24th NMOS tube and the second input of described the two or two input nand gate connect, described the 23rd The source electrode of NMOS tube, the drain electrode of the 25th described NMOS tube, the drain electrode of the 26th described NMOS tube and described The grid of 27 NMOS tube connects, the source electrode of the 24th described NMOS tube, the grid of the 26th described NMOS tube, The drain electrode of the 27th described NMOS tube and the drain electrode of the 28th described NMOS tube connect, the 25th described NMOS The source electrode of pipe, the source electrode of the 26th described NMOS tube, the source electrode and the described the 20th of the 27th described NMOS tube The source grounding of eight NMOS tube, the grid is described voltage comparator first input of the 25th described NMOS tube End, second input that grid is described voltage comparator of the 28th described NMOS tube, the one or two described input Second input of NAND gate and the outfan of the two or two described input nand gate connect, the two or two described input nand gate First input end and the one or two described input nand gate outfan connect and its connect end be described voltage comparator Outfan.

A kind of electric resistance partial pressure type DAC-PUF circuit the most according to claim 1, it is characterised in that described time schedule controller Including the one or two input with door, the two or two input anti-phase with door, the first phase inverter, the second phase inverter, the 3rd phase inverter and the 4th Device；

Described one or two input and door and the described the 2nd 2 input and are respectively provided with first input end, the second input and defeated with door Go out end, the one or two described input and first Enable Pin that first input end is described time schedule controller of door, be used for accessing Input register enables signal, the of the second input of described one or two input and door and the described the 2nd 2 input and door One input connects and it connects the clock end that end is described time schedule controller, for incoming clock signal, described second Two inputs and second Enable Pin that the second input is described time schedule controller of door, be used for accessing voltage comparator and enable letter Number, the one or two described input is connected with the input of the outfan of door and the first described phase inverter, and described first is anti-phase The outfan of device and the input of the second described phase inverter connect, and the outfan of the second described phase inverter is described sequential First outfan of controller, the first outfan of described time schedule controller and the clock end of described input register are even Connecing, the two or two described input is connected with the input of the outfan of door and the 3rd described phase inverter, and described the 3rd is anti-phase The outfan of device and the input of the 4th described phase inverter connect, and the outfan of the 4th described phase inverter is described sequential Second outfan of controller, the second outfan of described time schedule controller respectively with the clock of described voltage comparator The clock end of end, the clock end of the first described electric resistance partial pressure type DAC and the second described electric resistance partial pressure type DAC connects.

A kind of electric resistance partial pressure type DAC-PUF circuit the most according to claim 1, it is characterised in that described input register Including the first d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, 7th d type flip flop and the 8th d type flip flop；The first described d type flip flop, the second described d type flip flop, the 3rd described D trigger Device, described four d flip-flop, the 5th described d type flip flop, the 6th described d type flip flop, the 7th described d type flip flop and The 8th described d type flip flop is respectively provided with input, clock end and outfan；

The clock end of the first described d type flip flop, the clock end of the second described d type flip flop, described 3d flip-flop time Zhong Duan, the clock end of described four d flip-flop, the clock end of the 5th described d type flip flop, the 6th described d type flip flop The clock end of clock end, the clock end of the 7th described d type flip flop and the 8th described d type flip flop connects and its connection end is institute The clock end of the input register stated, the input of the first described d type flip flop, the input of the second described d type flip flop, institute The input of the 3d flip-flop stated, the input of described four d flip-flop, the input of the 5th described d type flip flop, The input of the 6th described d type flip flop, the input of the 7th described d type flip flop and the clock of the 8th described d type flip flop End connect and its to connect end be the input of described input register, the outfan of the first described d type flip flop and described The outfan of the second d type flip flop connects and it connects the first outfan that end is described input register, and the 3rd described D touches The outfan of the outfan and described four d flip-flop of sending out device connects and its connection end is the second of described input register Outfan, the outfan of the 5th described d type flip flop and the outfan of the 6th described d type flip flop connect and its connection end is institute 3rd outfan of the input register stated, the outfan of the 7th described d type flip flop and the output of the 8th described d type flip flop End connects and it connects the 4th outfan that end is described input register.