TWI627555B - method for physically unclonable function-identification generation AND apparatus of THE SAME - Google Patents

Abstract

A method for generating a PUF-ID, comprising: providing a PUF array, including a plurality of programmable resistive memories; performing a forming process and a stylizing program on all programmable resistive memories of the PUF array; Estimating the program to estimate the turmoil of the PUF array by comparing a reference current of a base unit with a sum of currents through one of all programmable resistive memories to obtain a PUF disorder; determining according to an estimation procedure A turbidity setting result; and a PUF-ID is generated according to the ambiguity setting result.

Description

Method for generating physical non-reproducible function identification and device for generating same

The present invention relates to a physical unclonable function (PUF) identification (ID) generation method and a device for generating a PUF-ID, and particularly relates to an estimation and determination of PUF disorder (randomness) A method of generating a PUF-ID and an apparatus therefor.

Physically unclonable function (PUF) is a hardware intrinsic security (HIS) that generates a wafer "fingerprint" to construct a secure authentication mechanism. Applying PUF avoids physical attacks that attempt to steal digital information from the chip. Static Random Access Memory (SRAM) is one of the common implementations of PUF applications that utilizes a threshold voltage difference in a power supply state to generate a wafer identification code. However, the construction of the SRAM PUF (for example, including six transistors) occupies a large size, which may affect the size of the PUF array to be reduced. Furthermore, the SRAM PUF is susceptible to environmental factors such as the SRAM PUF being quite sensitive to interference caused by temperature variations and voltage level variations (eg, supply voltage V _DD ). The hamming distances between the SRAM PUFs increase with increasing temperature, resulting in an increase in the bit error rate (BER). Therefore, although SRAM PUF can provide PUF applications with irregularity and uniqueness, the lack of reliability due to the noise induced instability is one of the main concerns of SRAM PUF applications. . Therefore, for a PUF application with good performance, the bit error rate of the PUF identification (PUF-ID) required to be generated is lowered, and high uniqueness is also required in the recognition degree.

Moreover, an ideal degree of disorder of the digital information "0" of a PUF array relative to the digital information "1" (which indicates a low resistance state and a high resistance state of the PUF array) is about 50% relative to 50%, This ideal chaos provides a highly specific PUF-ID in recognition. Traditionally, the resistance of a PUF array's memory is checked by one bit and then one bit to determine its resistance state. It is very time consuming and is not suitable for large PUF arrays (eg 64 bits, 256 bits). Resistance check of bit, 1k bit, etc.).

The present invention relates to a method for generating a physically unclonable function identification (PUF-ID) and a device for generating a PUF-ID. According to the method of the embodiment, the resistance state of the programmable resistance memory cells of a PUF array can be quickly and simply determined.

According to an embodiment, a PUF-ID generation method is provided, including: providing a PUF array (PUF array), including a plurality of programmable resistive memories; performing a programmable resistive memory on the PUF array Forming procedure and a programming procedure; performing an estimation procedure to estimate the disorder of the PUF array by using a reference current (I _Ref ) of a base unit Comparing with a total current (I _Total ) of all programmable resistive memories to obtain a PUF randomness; determining a turbidity setting result according to the estimation procedure; The PUG-ID is generated by setting the result in disorder.

According to an embodiment, a device having a PUF-ID is further provided, comprising: a programmable memory array disposed in a PUF region of a substrate; a program controller disposed on the substrate And coupled to the programmable memory array; and a security logic unit is disposed on the substrate and coupled to the program controller. The program controller performs the following steps: performing a forming process and a stylizing program on all of the plurality of programmable resistive memories included in the programmable memory array, wherein the programmable memory array is executable after the program is executed Generate one or more data sets; perform an estimation procedure to estimate the turbulence of the PUF array by passing a reference current of one of the base cells with a current through one of all programmable resistive memories The sum is compared to obtain a PUF randomness; a turbidity setting result is determined according to the estimation procedure; and a PUF-ID is generated according to the ambiguity setting result. The security logic unit stores the PUF-ID.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings.

According to an embodiment of the present disclosure, a method for generating a physical unclonable function (PUF) identification (ID) and a device for generating a PUF-ID are proposed. According to the method of the embodiment, a disorder of the resistance state of the programmable resistance memory cells of a PUF array can be quickly and simply determined, and whether the PUF array is needed can be determined. The programmable resistive memory again performs a forming procedure and a programming procedure (such as a setup (SET) procedure) to bring the PUF array ambiguity to near an ideal PUF disorder (eg, 50%) The digital information "0" is relative to 50% of the digital information "1"). Therefore, with the PUF-ID generation method proposed by the present disclosure, the time required for the PUF array of the application to generate a PUF-ID can be greatly shortened.

The embodiments of the present disclosure are described below with reference to the accompanying drawings to describe related procedures and apparatus. Related structural details such as the PUF array and program examples are as described in the following embodiments, and an example of a PUF-ID for generating an application embodiment is taken as an example. However, the disclosure is not limited to the content and aspects, and the disclosure does not show all possible embodiments. In the embodiments, the same or similar reference numerals are used to designate the same or similar parts, and the present disclosure may also be applied to other embodiments that are not proposed. Variations and modifications of the structure of the embodiments can be made in the relevant embodiments without departing from the spirit and scope of the disclosure. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

Furthermore, the use of ordinal numbers such as "first", "second", ..., etc., as used in the specification and claims, to modify the elements of the claim, is not intended to be The ordinal does not represent the order of a request element and another request element, or the order of the manufacturing method. The use of these ordinals is only used to make a request element with a certain name have the same named request. Components can be clearly distinguished.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simplified pictorial illustration of an apparatus in accordance with an embodiment. The device proposed in the embodiment includes a substrate 10 having a main functional area A _C and a sub-function region such as a PUF region A _PUF . In one embodiment, a programmable memory array (eg, a PUF array) is disposed in the PUF area A _PUF , and a main function circuit (ie task function circuit) is disposed in the main function area A _C . In one embodiment, a PUF array includes, for example, a plurality of programmable resistance memory cells having a transistor, such as a PUF-gold oxide half field effect transistor (PUF-MOSFET (1T)).

A programmable resistive memory generally includes a first electrode, a second electrode, and a programmable metal oxide memory element between the first electrode and the second electrode ( Programmable metal oxide memory element). In a forming procedure, the forming pulse can have a voltage high enough to generate a conductive portion in the programmable metal oxide memory device of the memory. In some metal oxide memory materials, the conductive portion can include oxygen vacancies that are initiated and arranged across the electrical location of the material to provide a conductive path. The formation pulse applied to the programmable resistive memory enables the first subset of the programmable resistance memory cells to form a conductive filament connected to the first electrode And the second electrode, and the memory of the second subset does not form a conductive filament connectable to the first electrode and the second electrode. Thus, the memory in the first subset can be in a low resistance state (LRS), while the memory in the second subset can be in a high resistance state (HRS). After the program is formed, during a stylized program (such as a setup (SET) program), the programming pulse applied to the programmable subset of the first subset and the second subset can be stabilized. And enhancing the conductivity of the conductive filaments of the first subset of memory (ie LRS memory), and the memory of the second subset remains in a high resistance state after the stylization procedure (ie, the conductive thin is still not formed) wire). The low resistance state and the high resistance state can be used to indicate the digital information "1" or "0" in the data set.

FIG. 2 is a schematic diagram of bit-mapping generated by a PUF array including 8×8 programmable resistive memories in an application according to an embodiment of the present invention. According to an embodiment, a programmable resistive memory having an open transistor (ie a memory in a low resistance state and a large amount of current can pass through the memories) provides digital information "0" with a closed transistor The programmable resistive memory (ie memory in a high-resistance state with no or very small current flowing through the memory) provides digital information "1", so in the power-up state (power-up state) The combination of irregular digital information caused by an array (such as one of the digital information combinations shown in Figure 2) can be used as a special chip fingerprint (chip "fingerprint") in practical applications.

After the formation of the program and the stylized program (for example, the setup (SET) program), it is necessary to check the disorder of the digital information "0" of the programmable resistive memory of the PUF array with respect to the digital information "1". The ideal information of the digital information “0” relative to the digital information “1” (which indicates the low resistance state and the high resistance state of the PUF array) is about 50% relative to 50%, and the ideal chaos can be provided in the identification. A highly specific PUF-ID. If the checked turmity is not within the acceptable ambiguity range, then all of the memory of the PUF array will be subjected to the formation procedure and stylization procedure as described above. The method of the embodiment provides a simple and fast way to estimate the turbulence of the PUF array.

FIG. 3A is a flow chart of a method for generating a physical non-reproducible function according to an embodiment of the present disclosure. In one embodiment, a PUF array (PUF array) including a plurality of programmable resistance memory cells is provided (step 301). A forming procedure and a programming procedure (e.g., a setup (SET) procedure) are performed on all of the programmable resistive memories of the PUF array (step 302). Then, an estimation process is performed to estimate the disorder of the PUF array by estimating a reference current (I _Ref ) by a base unit (for example, a MOSFET without ReRAM). And comparing with a total current (I _Total ) of all programmable resistive memories to obtain a PUF randomness (step 303). After the estimation procedure, a setting result of randomness is determined according to the estimation procedure (step 304). A PUF-ID is generated based on the result of the disorder setting (step 305). In an example, the generated PUF-ID may be, but is not limited to, a set of data consisting of digit values "0" and "1", such as "00010101", "01001001101", ..., and the like.

Furthermore, the formation procedure, the stylized (ex: SET) procedure, and the estimation procedure are repeated until the resulting PUF disorder falls within a pre-determined ideal range of randomness. In one example, the predetermined ideal range of ambiguity is a range of digital information "0" close to an ideal PUF ambiguity, such as 50%, relative to 50% of the digital information "1". FIG. 3B is a flow chart of determining an ambiguity setting result according to an estimation program according to an example in an embodiment. In step 3031, the PUF chaos is compared to a predetermined ideal chaos range. If the estimated PUF disorder falls within a predetermined desired degree of ambiguity, a garbled setting result is determined (step 304). If the estimated PUF disorder falls outside the predetermined ideal degree of chaos, then all the programmable resistive memory is again subjected to the forming process and the stylized program (ie, step 302 is performed again), and then the estimating process is performed (step 303) Obtain a re-created PUF randomness.

The estimation procedure according to one of the embodiments is used to calculate the disorder of a PUF array. The disorder of a PUF array (as described in step 303) can be compared to one of the reference cells (reference current, I _Ref ) and one of all programmable resistive memories by comparing a base cell (eg, a MOSFET without ReRAM) The total current (I _Total ) is obtained. An example is presented below to describe a reference current for one of the base cells, a calculation of the sum of the currents of one of the PUF arrays, and a PUF disorder of one of the PUF arrays. Furthermore, the programmable resistive memory system of a PUF array of the following example is arranged in a 3 ́3 array (the IE PUF array includes 9 programmable resistive memories).

FIG. 4 is a schematic diagram of a PUF array and related units electrically connected to the PUF array according to an embodiment of the disclosure. The PUF array includes a total of nine programmable resistive memories arranged in a 3 ́3 array, wherein one bit line BL is connected to the same row of memory, and one word line WL is connected to the same column of memory, one source line. SL also connects to the same line of memory. The associated unit of the PUF array includes a first control unit 41 electrically connected to the word lines of the memory, and a second controlling unit 42 electrically connected to the memory. The bit lines and a third controlling unit 43 are electrically connected to the source lines of the memory. In an embodiment, the first control unit 41, the second control unit 42, and the third control unit 43 are, for example, data multiplexers that control the voltages applied to the word lines, the bit lines, and the source lines. The related unit electrically connected to the PUF array further includes a first sensing amplifier SA1, a second sensing amplifier SA2 and a third sensing amplifier. SA3 to sense the current through the memory of the first row, the second row, and the third row, respectively. When the estimation procedure is performed, all of the programmable resistive memories are selected by applying a predetermined voltage, and then a total current is read, for example, the sum of the currents through the respective rows of memories as shown in FIG. The sum of the currents can be calculated and obtained by a processing unit 46 (disposed at a program controller 640 as shown in Fig. 6 below), and a switch unit 45 is set. The program unit 46 (and the protection program controller 640) is protected between the program unit 46 and the sense amplifiers (ie, SA1, SA2 and SA3). For one of the high resistance states (HRS), the resistive memory can be programmed, and only a small current is passed through the HRS memory and can be ignored in the sum of the sensed currents. For one of the low resistance states (LRS), the resistive memory can be programmed. After the voltage is supplied, the current passes through the LRS memory. This current is approximately equal to passing through a base unit (for example, without ReRAM). One of the currents of the MOSFET). Therefore, the greater the sum of the sensed currents, the greater the percentage of the number of LRS memories in the PUF array.

Figure 5 illustrates a current-voltage characteristic (I-V curves) of a base unit without ReRAM as an example of one of the embodiments. 6A-6C illustrate three combinations of LRS and HRS memory for a PUF array in an example according to an embodiment. Please also refer to Figure 5 and Figure 6A-6C.

In this example, during the estimation procedure, a MOSFET without a ReRAM (gate width = 0.42 μm, gate length = 0.18 μm) is used as a basic unit. As shown in Fig. 5, five curves are applied to the word line at different voltages (ie gate voltage V _g =0V, 1V, 2V, 3V, 4V), where V _D is applied to the bit line Read voltage. In the example, a reference current (I _Ref ) can be determined according to the IV characteristic curve of a basic unit. As shown in Figure 5, a reference current can be set to 450 μÅ (at gate voltage V _g = 4V and read voltage V _D = 1V).

After the formation and stylization (ex: SET) procedures, each programmable resistive memory (labeled "ReRAM-PUF") in the PUF array may be in a low resistance state (LRS) or a high resistance state. (HRS). The number of HRS memory and LRS memory in the PUF array as shown in Figure 6A (/6B/6C) is unknown prior to the estimation procedure. According to one of the estimation procedures of the embodiment, the current sum of one of the graphs of FIG. 6A is about 450 μÅ, by applying 4 V to the word line and 1 V to the bit line for all the programmable resistive memories in the PUF array. Obtained (0V at the source line). According to the estimation method of the embodiment, the number of programmable resistive memories in a low resistance state (LRS) is determined by the ratio of the sum of currents (I _Total ) to the reference current (I _Ref ). (take the nearest integer value). That is, I _Tata /I _Ref . Therefore, the ratio of the current sum (I _Total ) 450 μÅ to the reference current (I _Ref ) of 450 μÅ is equal to 1. This means that the PUF array of Figure 6A has a low resistance state (LRS) programmable resistive memory, and the percentage of the LRS memory is about 11%. Therefore, the PUF turbulence of the PUF array of Fig. 6A is 11% (low resistance) versus 89% (high resistance), and the result is far from an ideal degree of chaos (ie 50% to 50%). Therefore, these programmable resistive memories need to be re-formed and programmed (ex: SET) programs (by modifying the operating conditions of the change forming program and the stylized program) to create LRS memory and HRS memory. An additional combination (ie re-establishes the conductive filaments in the memory), and then an estimation procedure is performed to check for post-reconstruction updated PUF turmoil (ie performing steps 3031, 302, and 303 as shown in Figure 3B). The PUF array of Fig. 6A was re-examined in a memory-by-memory manner, and the results showed that the PUF array of Fig. 6A has 8 HRS memories and 1 LRS memory, which is in agreement with the results of the estimation method of the embodiment. Therefore, the PUF disorder of the PUF array can be quickly and simply judged by the estimation procedure of the embodiment, and the embodiment provides a time-saving estimation method.

Similarly, according to one of the estimation procedures, the current sum of one of the graphs of FIG. 6B is about 1800 (=450*4) μÅ, which is obtained by all the programmable resistive memories in the PUF array of FIG. 6B. Apply 4V to the word line and 1V to the bit line (0V to the source line). The ratio of the current sum (I _Total ) of 1800 μÅ to the reference current (I _Ref ) of 450 μÅ (Fig. 5) is equal to four. This means that the PUF array of Figure 6B has four low resistance state (LRS) programmable resistive memories, and the percentage of LRS memory is about 44%. . Therefore, the PUF turbulence of the PUF array of Figure 6B is 44% (low resistance) versus 56% (high resistance).

Similarly, according to one of the estimation procedures of the embodiment, the current sum of one of the 6C graphs is about 3150 (=450*7) μÅ, which is obtained by all the programmable resistive memories in the PUF array of FIG. 6C. Apply 4V to the word line and 1V to the bit line (0V to the source line). The ratio of the current sum (I _Total ) of 3150 μÅ to the reference current (I _Ref ) of 450 μÅ (Fig. 5) is equal to 7. This means that the PUF array of Figure 6B has seven low resistance state (LRS) programmable resistive memories, and the percentage of LRS memory is about 78%. . Therefore, the PUF turbulence of the PUF array of Figure 6B is 78% (low resistance) versus 22% (high resistance), which will fall outside the predetermined ideal ambiguity range.

In one example, if the number of programmable resistive memories in a low resistance state (LRS) is 40%-60% of the total number of all programmable resistive memories of the PUF array, it is regarded as PUF. When an acceptable range of turbulence is reached, "40% - 60% (LR) versus 60% - 40% (HR)" can be selected as a predetermined desired range of ambiguity. If the PUF disorder (for example, 44% (LR) vs. 56% (HR) in Figure 6B) falls within the predetermined ideal degree of ambiguity, the setting result of randomness can be determined (as in Figure 3B). Step 304), and generating a PUF-ID according to the result of the disorder setting (step 305 of FIG. 3A, and the generated PUF-ID is, for example, stored in the security logic unit 625 described later).

Therefore, the voltages applied to the wires of a base unit and a PUF array (e.g., word lines and bit lines) must be the same to obtain a reference current for the base unit to be compared and a current sum of the PUF array. In an example, this can also be expressed as a reference current (I _{Ref of the} embodiment) by applying a first voltage and a second voltage to a gate and a drain of the transistor of the base unit. And summing a current by applying the first voltage and the second voltage to the word line (WL) and the bit line (BL) of all programmable resistive memories of the PUF array, respectively (I _Total ). Furthermore, if the PUF array includes a total of Q programmable resistive memories, and the number of programmable resistive memories in a low resistance state is X (determined according to the ratio of I _Total /I _Ref described above), Then the PUF disorder can be expressed as: (X/Q) ́100% pairs ((QX)/Q) ́100%, where X and Q are both positive integers. By comparing the PUF chaos with a predetermined ideal chaos range, selecting a chaos setting result according to the estimating procedure (ex: step 304) or repeating the forming program, the stylizing program, and the estimating program (ex: as shown in FIG. 3B Steps 3031, 302, and 303), etc., can all be determined.

Although the PUF array illustrated in Fig. 4 (or Fig. 6A-6C) is a 3 ́3 array, the actual application is not limited to this array of numbers and arrangements. One of the PUF arrays may include an array of m ́n (m rows and n columns, total memory m ́n) matrix type of programmable memory, or other memory alignment patterns. The method proposed in the examples is applicable to many different memory arrangement types, and is not limited to arrays of matrix types. Furthermore, the reference current (I _Ref ) 450 μ Å obtained by the above-mentioned base unit at a reading voltage of 1 V is an exemplary value, which is only used to exemplify the estimation procedure of the embodiment, and is not intended to limit the disclosure. The read voltage (V _D ) can be lowered to reduce the sum of the resulting currents (I _total ). For example, when the read voltage drops to 0.01V, the reference current (I _Ref ) of the base unit can be reduced to, for example, about 1 uA. For a 1K-bit PUF array with the best ambiguity (50% low-resistance memory, 50% high-resistance memory), the sum of the currents obtained when the read voltage is 0.01V is 500uA. . Therefore, the use of an appropriate read voltage in a current-reading application is advantageous in obtaining a proper sum of currents and avoiding metal line migration problems.

Figure 7 is a block diagram of an apparatus having a PUF-ID in accordance with an embodiment of an application.

In this application example, a device includes an integrated circuit 600 having a programmable memory array 630 (eg, a PUF array including a plurality of programmable resistive memories disposed in a PUF region of a substrate) and A controller (e.g., a program controller 640), the programmable memory array 630 can generate one or more data sets. You can select one of the data (such as digital information "0" and "1" chaos close to 50% and 50%) as an optimum data set (ie PUF-ID) as the "fingerprint of the wafer"". According to an embodiment, the program controller 640 (disposed on the substrate and coupled to the programmable memory array 630 by, for example, the bus bar 641) performs the following steps: including all programmable resistive memories of the programmable memory array The body performs a forming procedure and a stylized (ex: SET) program (step 302 of FIG. 3A), wherein the programmable memory array can generate one or more sets of data after executing the stylized program (one Or more data sets); an estimation process is performed to estimate the turbulence of the PUF array by using a reference current (I _Ref ) of one of the base cells (ex: no ReRAM MOSFET) and all programmable Comparing the sum of the currents of the resistive memory (I _Total ) to obtain a PUF randomness (step 303 of the 3A, 3B diagram); determining a turbidity setting result according to the estimation procedure (Step 304 of Figures 3A, 3B); and generating a PUF-ID based on the result of the ambiguity setting (step 305 of Figure 3A).

In the device of this example, the program controller 640 can provide signals to control the application of bias arrangement supply voltages, and perform program formation and programming on the memory cells of the programmable memory array. (ex: SET) program (step 302 of FIG. 3A) and other operations associated with accessing programmable memory array 630, and program controller 640 also reads one or more generated after execution of the stylized program Group the data and perform the estimation process.

The integrated circuit 600 includes a mission function circuit 610, which may include special purpose logic circuits (sometimes referred to as special application integrated circuits), such as data processing sources for microprocessors and digital signal processors. Large memory such as flash memory, dynamic random access memory, programmable resistive memory, and combinations of various morphological circuits that are conventionally applicable in a wafer. The integrated circuit 600 includes an input/output (I/O) interface 620 that has wireless or wired access to other components or networks. In this example, an access control unit 615 is disposed between the input/output interface 620 and the main function circuit 610. The access control unit 615 is coupled to the input/output interface 620 by the bus bar 616 and coupled to the main function circuit 610 by the bus bar 611. The access control unit 615 can perform an access control protocol to cause or deny communication between the input/output interface 620 and the main function circuit 610.

To assist the access control unit 615, the example further includes a security logic unit 625 disposed in the wafer. The security logic unit 625 is electrically coupled to the programmable memory array 630, and the security logic unit 625 can select to store a unique data set as one PUF-ID from one or more sets of data. The security logic unit 625 can obtain the special data set (ie the PUF-ID) through the program controller 640 (for example, a PUF program controller) and the bus bar 631, and the security logic unit 625 utilizes the special data group (stored in the security logic). Unit 625) communicates with access control unit 615 via bus 622.

According to the above, a method for generating a physical non-reproducible function identification (PUF-ID) and a device for generating a PUF-ID are proposed. According to the method of the embodiment, a disorder of the resistance state of the programmable resistive memory of a PUF array can be quickly judged in a simple manner. Therefore, it is possible to quickly determine whether a program and a program (such as a setup program) need to be executed again on the programmable resistive memory of the PUF array to regain a new combination of low resistance and high resistance states. Accordingly, by using the method of the embodiment, a highly specific PUF-ID can be generated (the PUF array disorder is brought close to an ideal PUF disorder, for example, 50% of the digital information "0" is relative to the 50% digit. The time required for information "1" can be greatly reduced. Moreover, according to the method of the embodiment, the randomness estimation of a PUF array can be accurately estimated, and the resistance related information of the PUF array can be correctly obtained. Therefore, the PUF-ID generation method according to the embodiment not only greatly saves the time required for PUF disorder estimation, but also provides one PUF-ID which is indeed highly specific in nature.

Other embodiments, such as known arrangements of components/devices, may have different arrangements and arrangements, and may be applied, depending on the actual needs and conditions of the application, and may be appropriately adjusted or varied. Therefore, the structures shown in the specification and drawings are for illustrative purposes only and are not intended to limit the scope of the disclosure. Further, it will be apparent to those skilled in the art that the shapes and positions of the constituent members and the details of the method steps in the embodiments are not limited to those illustrated in the drawings, and are not in accordance with the needs and/or manufacturing steps of the actual application. It can be adjusted accordingly in the case of the spirit of this disclosure.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

A _PUF ‧‧‧PUF area
A _C ‧‧‧ main function area
10‧‧‧Substrate
201‧‧‧ substrate surface
301-305, 3031‧‧‧ steps
41‧‧‧First Control Unit
42‧‧‧Second control unit
43‧‧‧ third control unit
SA1‧‧‧First sense amplifier
SA2‧‧‧Second Sense Amplifier
SA3‧‧‧ Third sense amplifier
45‧‧‧Switch unit
46‧‧‧Program unit
600‧‧‧Integrated circuit
610‧‧‧ main function circuit
615‧‧‧Access Control Unit
620‧‧‧Input/output interface
625‧‧‧Safe Logic Unit
630‧‧‧Programmable memory array
640‧‧‧Program Controller
616, 622, 631, 641‧‧ ‧ busbars
WL‧‧‧ character line
BL‧‧‧ bit line
SL‧‧‧ source line

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simplified pictorial illustration of an apparatus in accordance with an embodiment. FIG. 2 is a schematic diagram of bit-mapping generated by a PUF array including 8×8 programmable resistive memories in an application according to an embodiment of the present invention. FIG. 3A is a flow chart of a method for generating a physical non-reproducible function according to an embodiment of the present disclosure. FIG. 3B is a flow chart of determining an ambiguity setting result according to an estimation program according to an example in an embodiment. FIG. 4 is a schematic diagram of a PUF array and related units electrically connected to the PUF array according to an embodiment of the disclosure. Figure 5 is a graph showing the current-voltage characteristic of a base unit without ReRAM as a base unit as an example of an embodiment. 6A-6C illustrate three combinations of LRS and HRS memory for a PUF array in an example according to an embodiment. Figure 7 is a block diagram of an apparatus having a PUF-ID in accordance with an embodiment of an application.

Claims (10)

A method for generating a physical unclonable function identification (PUF-ID), comprising: providing a PUF array, comprising a plurality of programmable resistance memory cells; All of the programmable resistive memories of the PUF array are subjected to a forming procedure and a programming procedure; an estimation procedure is performed to estimate the disorder of the PUF array by A reference current (I _Ref ) of one of the base units is compared with a total current (I _Total ) of all of the programmable resistive memories to obtain a PUF disorder. (PUF randomness); determining a turbidity setting result according to the estimation procedure; and generating a PUF-ID according to the ambiguity setting result. The method for generating a PUF-ID according to claim 1, wherein the number of the programmable resistive memories in a low resistance state (LRS) is determined by the sum of the currents. The ratio of one of the reference currents is determined. The method for generating a PUF-ID according to the second aspect of the invention, wherein the PUF array comprises Q of the programmable resistive memories, and the programmable resistive memories in the low resistance state The number is determined to be X, then the PUF disorder is: (X/Q) ́100% vs. ((QX)/Q) ́100%, where X and Q are positive integers, where The PUF disorder is in the range of 40%-60% to 60%-40%, and the result of the disorder setting is determined. The method for generating a PUF-ID according to claim 1, wherein a first voltage and a second voltage are respectively applied to a gate and a drain of the transistor of the base unit. The reference current (I _Ref ) is obtained. The method for generating a PUF-ID according to claim 4, wherein the first voltage and the second voltage are respectively applied to the word lines (WL) of all the programmable resistive memories. And the bit line (BL), and get the sum of the currents (I _Total ). The method for generating a PUF-ID according to claim 1, further comprising: comparing the PUF disorder to a pre-determined ideal range of randomness, wherein the PUF disorder If the degree falls within the predetermined ideal degree of chaos, the result of the disorder setting is determined; if the PUF disorder falls outside the predetermined ideal degree of chaos, all of the programmable resistive memories are again performed. Form the program and the stylized program. The method for generating a PUF-ID according to claim 1, wherein the forming procedure, the stylizing program, and the estimating procedure are repeated until the obtained PUF disorder falls within a predetermined ideal degree of confusion. until. The method for generating a PUF-ID according to claim 1, wherein the number of the programmable resistive memories in a low resistance state (LRS) is the programmable of the PUF array. When the total number of resistive memories is 40%-60%, the result of the disorder setting is determined. A device having a physical non-reproducible function identification (PUF-ID), comprising: a programmable memory array disposed in a PUF region of a substrate; a program controller disposed on the substrate And coupled to the programmable memory array, the program controller performs the following steps: performing a forming procedure and a forming process on all of the plurality of programmable resistive memories included in the programmable memory array a programming procedure, wherein the executable memory array can generate one or more data sets after executing the stylized program; performing an estimation procedure to estimate the disorder of the PUF array, By comparing a reference current (I _Ref ) of a base unit with a total current (I _Total ) through all of the programmable resistive memories, Obtaining a PUF randomness; determining a turbidity setting result according to the estimating procedure; and generating a PUF-ID according to the ambiguity setting result; A security logic unit is disposed on the substrate and coupled to the program controller, wherein the security logic unit stores the PUF-ID. The device of claim 9, wherein the number of the programmable resistive memories in a low resistance state is determined by a ratio of the sum of the currents to the reference current, wherein the The program memory array includes Q of the programmable resistive memories, and the number of the programmable resistive memories in the low resistance state is determined as X, and the PUF disorder is: X/Q) ́100% Pair ((QX)/Q) ́100%, where X and Q are both positive integers.