JP2020102827A - Nonvolatile memory device and challenge-response method - Google Patents

Abstract

To provide a nonvolatile memory device having high tamper resistance.SOLUTION: A nonvolatile memory device 10 includes a data generation circuit and a reconstruction processing circuit. The data generation circuit is configured so that, after generating the first response data, the reconstruction processing circuit executes a reconstruction writing; and when a piece of challenge data of a first type is acquired again after the reconstruction writing is executed, a third response data that is different from the first response data is generated (PUF registration mode); after generating the second response data, the reconstruction processing circuit executes a reconstruction writing, and when the challenge data of the second type is acquired again after the reconstruction writing has been performed, a piece of fourth response data which is the same as the second response data is generated (permanent PUF registration mode).SELECTED DRAWING: Figure 19

Description

The present disclosure relates to a nonvolatile memory device having a plurality of resistance change type nonvolatile memory cells and having tamper resistance, and a challenge/response method using the nonvolatile memory device.

The market for electronic commerce services provided via the Internet such as online banking and online shopping is expanding rapidly. Electronic money is used as a payment method at this time, and the use of IC (Integrated Circuit) cards and smartphone terminals used as a medium thereof is also expanding. These services require a higher level of security technology for mutual authentication in communication and encryption of communication data for security at the time of payment.

With regard to software technology, encryption technology for program processing centering on advanced encryption algorithms has been accumulated, and sufficient security has been achieved. However, due to technological progress, there is a growing concern that the information inside the circuit may be directly read by hardware from the outside.

JP, 2016-105585, A International Publication No. 2014/119329 US Pat. No. 8446250 International Publication No. 2010/100015

Georgios Selimis, et al. "Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for Secure Key Generation in Wireless Sensor Nodes" An Chen, "Comprehensive Assessment of RRAM (registered trademark)-based PUF for Hardware Security Applications" IEDM2015. P. H. Tseng, et al. "Error Free Physically Unclonable Function (PUF) with Programmed ReRAM using Reliable Resistence States by Novel ID-Generation Method" SSDM2017 Klaus Kurasaswe, “Reconfigurable Physical Unclonable Functions-Enabling Technology for Tamper-Resistant Storage”

The present disclosure provides a non-volatile memory device having high tamper resistance and a challenge-response method.

A non-volatile memory device according to an aspect of the present disclosure is a non-volatile memory device that uses a memory cell array including a plurality of resistance change type memory cells and the memory cell array when challenge data is acquired. The data generation circuit includes a data generation circuit that generates response data, and a reconfiguration processing circuit that executes reconfiguration writing by applying a voltage pulse to the memory cell array at least once. Unique challenge data that is unique to each non-volatile memory device is generated when the challenge data is acquired, and unique unique data that is unique to each non-volatile memory device is obtained when the second type of challenge data is acquired. 2 response data is generated, the first response data is generated, the reconfiguration writing is executed by the reconfiguration processing circuit, and the first type of the reconfiguration writing is performed after the reconfiguration writing is executed. When the challenge data is obtained again, the third response data different from the first response data is generated, the second response data is generated, and then the reconfiguration writing is executed by the reconfiguration processing circuit. If the second type of challenge data is acquired again after the reconfiguration write is executed, the same fourth response data as the second response data is generated.

A challenge-response method according to an aspect of the present disclosure is a challenge-response method in which response data corresponding to challenge data is generated by a nonvolatile memory device including a memory cell array including a plurality of resistance-change memory cells. , A data generation step of generating response data using the memory cell array when the challenge data is obtained, and a reconfiguration processing of executing reconfiguration writing by applying a voltage pulse to the memory cell array at least once. In the data generation step, when the first type of challenge data is acquired, unique non-volatile memory device-specific first response data is generated and the second type of challenge data is generated. When it is acquired, the unique second response data that is different for each nonvolatile memory device is generated, and after the first response data is generated, the reconfiguration writing is executed by the reconfiguration processing step, and When the challenge data of the first type is acquired after the reconfiguration writing is executed, the third response data different from the first response data is generated, and the second response data is generated. After that, when the reconfiguration write is executed by the reconfiguration processing step and the second type challenge data is acquired after the reconfiguration write is executed, the same first response data as the second response data is acquired. 4 response data is generated.

The present disclosure provides a non-volatile memory device having a high tamper resistance and a challenge/response method.

FIG. 1 is a block diagram showing an example of a schematic configuration of a variable resistance nonvolatile memory device according to an embodiment. FIG. 2 is a cross-sectional view showing an example of a schematic configuration of a memory cell included in the variable resistance nonvolatile memory device shown in FIG. FIG. 3 is a plot of the relationship between the normalized resistance value in the low resistance state obtained by actual measurement for a certain memory cell array and the deviation of the standard normal distribution regarding the variation. FIG. 4 is a diagram plotting the relationship between the normalized resistance value and the deviation of the standard normal distribution regarding the variation when reconfiguring writing is performed 100 times on a certain 3-bit memory cell. FIG. 5 is a flowchart of reconfiguration writing by the non-volatile memory device shown in FIG. FIG. 6 is a block diagram showing a specific configuration example of the nonvolatile memory device according to the embodiment. FIG. 7 is a diagram showing a configuration example of a read circuit included in the nonvolatile memory device shown in FIG. FIG. 8 is a circuit diagram showing a more detailed configuration example of one bit of the read circuit shown in FIG. FIG. 9 is a timing chart when reading a selected memory cell in the nonvolatile memory device shown in FIG. FIG. 10 is a flowchart showing an operation example when PUF data is registered by the nonvolatile memory device according to the embodiment. FIG. 11 is a data flow diagram showing a method of generating helper data generated when PUF data is registered by the nonvolatile memory device according to the embodiment. FIG. 12 is a flowchart showing an operation at the time of reproducing PUF data by the nonvolatile memory device according to the embodiment. FIG. 13 is a data flow diagram showing a process of reproducing correct PUF data at the time of registration by the nonvolatile memory device according to the embodiment. FIG. 14 is a flowchart showing an operation example of the PUF reconfiguration mode by the nonvolatile memory device according to the embodiment. FIG. 15 is a graph showing the Hamming distance between the PUF data and the normalized frequency at each number of times generated when the reconfigurable writing of FIG. 14 is executed 100 times. FIG. 16 is a flowchart showing an operation example of the permanent PUF data registration mode by the nonvolatile memory device according to the embodiment. FIG. 17 is a diagram in which a description regarding the permanent PUF data registration mode is added to FIG. FIG. 18 is a diagram showing a specific example of data used for generating permanent PUF data by the nonvolatile memory device according to the embodiment. FIG. 19 is a flowchart showing an operation example of the permanent PUF data reproduction mode by the nonvolatile memory device according to the embodiment. FIG. 20 is a diagram showing an example of generation of permanent PUF data by the nonvolatile memory device according to the embodiment.

(Knowledge forming the basis of the present disclosure)
Generally, in an IC with enhanced security, secret information is encrypted by using an encryption key (also referred to as “secret key”) mounted inside to prevent leakage of information. In this case, it is essential that the information of the encryption key held inside is not leaked to the outside.

In recent years, a new hardware technology called a PUF (Physical Duplication Function; Physically Unclonable Function) has been proposed. The PUF technology is a technology that utilizes manufacturing variations to generate unique individual identification information that differs for each IC. Hereinafter, in the present specification, individual identification information generated by the PUF technique will be referred to as “PUF data”. The PUF data is unique data unique to each device and is associated with the variation in the physical characteristics of the IC. Since slight variations in the physical characteristics are used, it is difficult to perform physical analysis and the physical characteristics of each IC are artificially changed. It is difficult to reproduce and can be used as data that is difficult to physically copy.

An SRAM PUF as in Non-Patent Document 1 can be illustrated as a specific prior example. In this example, the PUF uses the initial value immediately after the power is turned on, which determines whether the data is "0" data or "1" data in the threshold variation (operating voltage variation) of the transistor in each memory cell in the SRAM.

In addition, ReRAM (Resistive Random Access Memory; PUF) such as Patent Documents 1 to 3 and Non-Patent Documents 2 and 3 may be exemplified. In the example of Patent Document 3, the variation in the resistance value of the memory cell of ReRAM is used. Then, the resistance values in the memory group are acquired, a determination value serving as a reference for binarization is obtained from the resistance values, and PUF data is generated. Non-Patent Document 2 is a method of generating PUF data by writing two cells in the same state and comparing the magnitude relationship due to the resistance variation after writing. Further, in Patent Document 3 and Non-Patent Document 3, the randomness of forming of ReRAM is used as a PUF. In a memory cell of ReRAM, a transition to a rewritable variable state is performed by applying a voltage stress called forming, which is higher than a normal rewriting voltage, to an initial state having a high resistance value to cause dielectric breakdown. You can The application time of the voltage stress required in the forming process has a random characteristic for each memory cell. In this method, a voltage stress for a fixed time is applied to the memory group, and when the forming of about half of the memory cells is completed, the voltage stress application process is terminated. Then, in the memory cell group after completion, about half of the memory cells in the initial state and the variable state are recorded as random data unique to each device. The method is a method of using the random data as PUF data.

Furthermore, as an applied function of the PUF, a reconfigurable PUF as illustrated in Patent Document 3 and Non-Patent Document 4 is illustrated. In Patent Document 3 and Non-Patent Document 4, the rewriting process is executed for the resistance change type memory cell treated as a PUF data source. By executing the rewriting process, the device structure changes and the resistance variation relationship between the memory cells changes. Therefore, new PUF data different from that before the rewriting process can be generated. In this manner, the stress of common heat or voltage is applied to a plurality of devices from the outside to change the relationship of variation and realize the reconfiguration function.

With such PUF technology, by recording PUF data that is a random number unique to each IC, it is possible to treat it as data that is difficult to analyze and cannot be copied. This PUF data is used, for example, as a device key for encrypting the above-mentioned secret key. The private key encrypted with the device key (that is, PUF data) is stored in the nonvolatile memory in an encrypted state. That is, since the encrypted private key recorded in the non-volatile memory can be decrypted into the original private key data only by the device key, the security strength of the private key depends on the security strength of the PUF.

On the other hand, since the PUF utilizes slight variations in physical characteristics, when PUF data is reproduced to the same device, it is easily affected by environmental changes such as temperature and power supply, and the reproducibility is reduced, and the manufacturing process is reduced. There are some challenges, such as a decrease in uniqueness due to physical dependence in.

Patent Document 4 uses a technique called Fuzzy Extractor as a measure for improving the reproducibility and uniqueness. This is a technology in which post processing for PUF data such as an algorithm and a hash function capable of error correction while maintaining the security strength of PUF is installed.

The present disclosure provides a non-volatile memory device having a higher tamper resistance and a challenge/response method which are not in the related art.

Hereinafter, embodiments of the invention according to the present disclosure will be described in detail with reference to the drawings. Each of the embodiments described below shows one specific example of the present invention. Numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of constituent elements, steps, order of steps, and the like shown in the following embodiments are examples, and are not intended to limit the present invention. Further, among the constituent elements in the following embodiments, constituent elements that are not described in independent claims showing the highest concept of the present invention will be described as arbitrary constituent elements. In addition, each drawing is not necessarily an exact illustration. In each drawing, the substantially same components are denoted by the same reference numerals, and redundant description may be omitted or simplified.

(Outline of variable resistance nonvolatile memory device used in the present disclosure)
FIG. 1 is a block diagram showing an example of a schematic configuration of a variable resistance nonvolatile memory device 100 according to the embodiment. 2 is a cross-sectional view showing an example of a schematic configuration of a memory cell 91 included in the variable resistance nonvolatile memory device 100 shown in FIG. In the present specification, the resistance change type nonvolatile memory device is also simply referred to as a nonvolatile memory device.

In the example shown in FIG. 1, the non-volatile memory device 100 according to the present embodiment includes at least a memory cell array 90 and a control device 93. The control device 93 does not necessarily have to be a part of the non-volatile memory device 100, is a device provided outside the non-volatile memory device 100 and connected to the non-volatile memory device 100. The described operations may be performed.

The memory cell array 90 has a configuration in which a plurality of resistance change type memory cells 91 in which digital data is recorded according to the magnitude of the resistance value are arranged in an array. In the present embodiment, some of the plurality of memory cells 91 forming the memory cell array 90 are assigned as PUF data memory cells.

In the example illustrated in FIG. 2, the resistance change element 120 included in the memory cell 91 includes a base layer 122 (eg, Ta ₂ O ₅ ), a first electrode 124 (eg, Ir), and a resistance change layer 126 (eg, TaO). _x ) and the second electrode 128 (for example, TaN). A transistor 129 for selecting a specific memory cell is connected to each memory cell 91.

The memory cell 91 has a property that it can take a variable state in which a resistance value reversibly transits between a plurality of variable resistance value ranges by being applied with a plurality of different electric signals. The variable resistance value range includes at least a resistance value range in which the digital information is in a low resistance state as one state (first resistance state) and another state (second resistance state) as in the low resistance state. Also has a resistance value range in which a high resistance state is achieved. As described above, in the variable state, at least the resistance value can be reversibly transited between the low resistance state and the high resistance state.

Further, the memory cell 91 has a property that it can assume an initial state. The "initial state" is a state in which the resistance value is in the initial resistance value range that does not overlap with any of the variable resistance value ranges. The memory cell in the initial state does not enter the variable state unless forming is performed. “Forming” means applying a predetermined electrical stress to a memory cell to change the resistance value of the memory cell to a state in which the resistance value reversibly transits between a plurality of variable resistance value ranges. Say.

The electrical stress applied for forming (forming stress) may be, for example, an electrical pulse having a predetermined voltage and a time width, or may be a combination of a plurality of electrical pulses. .. The forming stress may be a cumulative stress. In that case, when the accumulated amount of stress exceeds a predetermined amount, the memory cell 91 transits from the initial state to the variable state.

In the present embodiment, it is assumed that the memory cell 91 has such a property that the resistance value does not reversibly transit between a plurality of variable resistance value ranges unless formed after forming. That is, it is assumed that the variable resistance element, which has been manufactured by the semiconductor process or the like and before the forming stress is applied, is in the initial state.

However, this property is an example and is not essential. The memory cell 91 does not have to be an element that can assume an initial state, and may be, for example, a so-called formingless element that has only a variable state.

The memory cell array 90 may be used as PUF, which is random individual identification information due to physical characteristics, in addition to recording an arbitrarily set data pattern depending on the difference in variable state.

The PUF of one example uses the variation in the resistance value of each memory cell in the low resistance state. Even in the low resistance state, there is a slight variation in the resistance value, and the PUF of the example uses the characteristic. In the memory cell array 90, a plurality of memory cells 91 are all set to the same resistance state as a variable state and treated as a memory group in which PUF data is recorded.

FIG. 3 is a diagram in which a relation between a normalized resistance value (horizontal axis) in a low resistance state obtained by actual measurement for a certain memory cell array and a deviation (σ) (vertical axis) of a standard normal distribution regarding the variation is plotted. is there. As shown in FIG. 3, the distribution of variations in the resistance value of the memory cells follows a normal distribution and is distributed in a substantially straight line. From this, it can be confirmed that the resistance variation is an extremely random phenomenon. In FIG. 3, the median value of the distribution of resistance variation (“Median” in the figure) is set as the determination value. For example, if the resistance value is larger than the determination value, “1” data (“Data “1” in the figure ""), and if smaller, "0" data ("Data "0"" in the figure) is assigned to output digital data.

FIG. 4 shows that, with respect to a certain 3-bit memory cell, as shown in the flowchart of FIG. 5, after writing with high resistance (or writing with low resistance), writing is performed again with low resistance (or high resistance writing). Deviation (σ) of the standardized normal resistance value (horizontal axis) and its normal distribution after each low resistance writing, when the returning process (hereinafter, this writing is called reconstruction writing) is executed 100 times. It is the figure which plotted the relationship with (vertical axis). The three distributions shown correspond to each 3-bit memory cell. As shown by this variation characteristic, the memory cell used in the present embodiment has not only the variation in the resistance value between the memory cells described in FIG. 3 but also the variation in the resistance value after the rewriting of each memory cell. I know that Furthermore, when comparing the write variation characteristics of the 3-bit memory cells, it can be confirmed that the shapes and absolute values of these distributions are greatly different, as can be seen from the fact that they are separated into three distributions. In consideration of this feature, for example, when the method of setting the median value as shown in FIG. 3 as the determination value and outputting the digital data is adopted, when the reconfiguration write is executed, 0 to 1 or before and after the reconfiguration write is executed. There are memory cells that change from 1 to 0 (distribution located in the center of FIG. 4) and memory cells that do not change from 0 or 1 before and after reconfiguration writing (distributions located on the left and right of FIG. 4). You can confirm that. From the above, by executing, for example, reconfiguration writing to the same plurality of memory cells, data of 0 and 1 of a plurality of bits are changed randomly before and after writing, and new digital data can be constructed. On the other hand, it can be seen that both permanent data such that 0 and 1 data do not change can be realized.

(Structure and basic operation of variable resistance nonvolatile memory device)
FIG. 6 is a block diagram showing a specific configuration example of the nonvolatile memory device 10 according to the embodiment. The non-volatile memory device 10 is one specific example of the non-volatile memory device 100 described above, and executes a challenge/response method of generating response data that is a secret key for challenge data given from the outside. .. However, the specific configuration of the nonvolatile memory device according to the embodiment is not limited to the configuration shown in FIG. The challenge data may have any format as long as it is information requesting response data.

As shown in FIG. 6, the nonvolatile memory device 10 according to the embodiment includes a memory body 22 on a semiconductor substrate. The nonvolatile memory device 10 further includes a data input/output circuit 6, a control circuit 15, and an address input circuit 16.

The memory body 22 includes a read circuit 12, a write circuit 14, a determination value setting circuit 13, a row decoder circuit 18, a column decoder circuit 17, and a memory cell array 20. Functionally, the control circuit 15, the read circuit 12, and the determination value setting circuit 13 mainly form a data generation circuit that generates response data using the memory cell array 20 when challenge data is acquired from the outside. To be done. In addition, the control circuit 15 and the write circuit 14 mainly configure a reconfiguration processing circuit that executes reconfiguration writing in which the voltage pulse is applied to the memory cell array 20 at least once.

The write circuit 14 applies a predetermined voltage in each operation to the selected memory cell 21 to write data. For example, the write circuit 14 executes a reconfiguration write to all memory cells in the PUF area 8 in addition to a write operation for setting an arbitrary resistance state in the information area 7 described later.

The read circuit 12 performs a read operation in parallel on each of the plurality of memory cells 21, and compares the obtained resistance value with a determination value output from a determination value setting circuit 13, which will be described later, based on a digital value. The data Dout is output. The read circuit 12 has an error correction circuit.

The judgment value setting circuit 13 calculates the median value of the resistance value variation distribution from the resistance values of the memory cells in the PUF region, which will be described later, and outputs it to the reading circuit 12 as a judgment value which is an example of the first judgment value (that is, the setting value). ) Do. Further, the judgment value setting circuit 13 outputs the first permanent judgment value and the second permanent judgment value to the reading circuit 12 as the judgment value in order to extract the permanent data in which the data does not change even after the reconstruction writing. That is, set). The first permanent determination value is an example of a third determination value that is larger than the first determination value, and the second permanent determination value is an example of a second determination value that is smaller than the first determination value. For example, the judgment value setting circuit 13 reads the digital data generated by using the median value as the judgment value (hereinafter, the digital data generated by using the judgment value is referred to as PUF data) in the reading circuit 12 when reading the digital data. When the median value is set based on the resistance value obtained from the circuit 12, on the other hand, when the read circuit 12 extracts the permanent data, the position information data of the bit (hereinafter In order to extract such position information data as permanent PUF information data), a first permanent judgment value or a second permanent judgment value is set.

It should be noted that the median of the acquired resistance values is calculated as a judgment value, it is judged whether or not the acquired resistance value is larger than the judgment value, and the first permanent judgment value and the second permanent judgment value are extracted in order to extract the permanent data. Judgment of the permanent judgment value, generation of PUF data, and extraction of permanent data do not have to be performed by the memory main body 22 including the judgment value setting circuit 13 and the read circuit 12, and the memory main body 22 May be performed outside of.

The row decoder circuit 18 selects one word line WL from a plurality of j word lines WL0 to WLj connected to the memory cell array 20.

The column decoder circuit 17 includes k bit lines, which is the number of parallel reads (the number of memory cells forming a memory group) among the n bit lines BL0 to BLn and the n source lines SL0 to SLn. BL and k corresponding source lines SL are selected, and the selected lines are connected to the write circuit 14 and the read circuit 12.

These (write circuit 14, read circuit 12, row decoder circuit 18, and column decoder circuit 17) operate according to the number of rows and/or columns in which reading and/or writing are performed in parallel.

The read circuit 12 outputs digital data Dout. The read circuit 12 is connected to the k memory cells selected by the column decoder circuit 17 and the row decoder circuit 18 via k bit lines, and the resistance values of the k memory cells and the judgment value setting circuit 13 are connected. Then, the generated digital data Dout is output to the data input/output circuit 6.

The memory main body 22 has an information area 7 and a PUF area 8 as storage areas. The information area 7 is an area to which the word lines WL0 to WLi are connected, while the PUF area 8 is an area to which WLi+1 to WLj are connected. The information area 7 is an example of a first area composed of memory cells holding a resistance value required to generate response data, while the PUF area 8 is a memory cell holding information other than the resistance value. It is an example of a second region configured by. Specifically, the information area 7 includes data cells and arbitrary data (user data) is recorded therein, while the PUF area 8 is recorded with PUF data in which the same resistance state is set.

The information area 7 and the PUF area 8 do not have to be divided by word lines as shown in FIG. 6, and may be divided by any area on the memory cell array 20. At this time, the more complicated the regularity of the physical area division, the higher the resistance to attacks such as hacking. The information area 7 and the PUF area 8 may be further subdivided so that access can be restricted according to the importance of security. For example, security data in the PUF area 8 in which PUF data is stored may be restricted so that the user cannot access it.

The memory cell array 20 intersects a plurality of word lines WL0 to WLj, a plurality of bit lines BL0 to BLn formed so as to intersect the word lines WL0 to WLj and extend in parallel with each other, and intersects the word lines WL0 to WLj. And source lines SL0 to SLn formed so as to extend parallel to each other and parallel to the bit lines BL0 to BLn. The memory cells 21 are arranged at the three-dimensional intersections of the word lines WL0 to WLj and the bit lines BL0 to BLn, respectively.

Each memory cell 21 includes a resistance change element 23 and a transistor 24. The word lines WL0 to WLj are connected to the gate terminals of the respective transistors 24, the bit lines BL0 to BLn are connected to the second electrodes of the resistance change elements 23 included in the respective memory cells 21, and the first of the resistance change elements 23 are connected. The electrodes are connected to the second main terminal of the transistor 24, and the source lines SL0 to SLn are connected to the first main terminal of the transistor 24, respectively.

The resistance change element 23 operates as a non-volatile memory element in the memory cell 21. The nonvolatile memory device 10 is a so-called 1T1R resistance change type nonvolatile memory device in which each memory cell 21 is composed of one transistor 24 and one resistance change element 23. The selection element of the memory cell is not limited to the above transistor. For example, a two-terminal element such as a diode may be used.

The control circuit 15 causes the column decoder circuit 17 to select either the bit line or the source line based on a control signal given from the outside, and connects the selected bit line or source line to the write circuit 14 at the time of writing. At the time of reading, the selected bit line or source line is connected to the reading circuit 12. Then, the write circuit 14 or the read circuit 12 is operated. The control circuit 15 may be configured by a memory in which a program is stored, a processor that executes the program, an input/output circuit, or the like, or may be configured by a dedicated logic circuit.

The variable resistance element 23 can have the same configuration as the variable resistance element 120 described above with reference to FIG. 2 in the embodiment, and thus detailed description thereof will be omitted.

Although the NMOS transistor is used as the selection transistor of the memory cell array 20 in the example shown in FIG. 6, the present invention is not limited to this, and a PMOS transistor may be used.

FIG. 7 is a diagram showing a configuration example of the read circuit 12 included in the nonvolatile memory device 10 shown in FIG. The memory cell array 20 and the column decoder circuit 17 are also shown in the figure. The read circuit 12 performs a read operation in parallel in units of a memory group including k (k is an integer satisfying 1≦k≦n) memory cells 21, and thus k sense amplifier circuits 30 (TSA0, TSA0, TSA1, TSA2,... TSAk). The k bit lines selected by the column decoder circuit 17 are connected to the k sense amplifier circuits 30, respectively. Each sense amplifier circuit 30 outputs the resistance value of the connected memory cell 21.

FIG. 8 is a circuit diagram showing a more detailed configuration example of one bit of the read circuit 12 shown in FIG. 7 (that is, corresponding to reading from one memory cell 21).

The read circuit 12 has a sense amplifier circuit 30. The sense amplifier circuit 30 includes a comparator 31, a resistance value counter 32, a precharge PMOS transistor 33, a load PMOS transistor 34, and a clamp circuit composed of a clamp NMOS transistor 36.

The resistance counter 32 is connected to the output destination of the comparator 31. The resistance value counter 32 starts counting by the CLK signal after the count value in the resistance value counter 32 is initialized when the reset control signal RST becomes low level. The CLK signal is a signal output from the control circuit 15 and serves as a reference when converting the discharge time or the charge time that changes depending on the resistance value of the resistance change element 23 into a count value. The CLK signal is, for example, a rectangular wave that maintains a constant frequency. Each time this CLK signal rises, the count value of the resistance value counter 32 is incremented by one. When the node SEN falls below the reference voltage VREF, the output signal from the comparator 31 is inverted, and the count value at that time is held as COUNT_OUT. It The count value COUNT_OUT is input to the input terminal a of the comparator 35, while the determination value received from the determination value setting circuit 13 is input to the input terminal b of the comparator 35, and the value of the input terminal a is input to the comparator 35. The value of the terminal b is compared, and the comparison result is transmitted to the data input/output circuit 6 as digital data Dout.

In the precharge PMOS transistor 33, the precharge control signal PRE is input to the gate terminal, the power supply voltage VDD is input to the source terminal, and the node SEN is connected to the drain terminal.

The capacitor 36a is installed to adjust the discharge or charge time, and has one end connected to the node SEN and the other end connected to GND.

In the load PMOS transistor 34, the load control signal LOAD is input to the gate terminal, the power supply voltage VDD is input to the source terminal, and the node SEN is connected to the drain terminal.

A clamp control signal CLMP is input to the gate terminal of the clamp NMOS transistor 36, the node SEN is connected to either the source terminal or the drain terminal, and the memory cell is connected to the other end.

FIG. 9 is a timing chart when reading the selected memory cell in the nonvolatile memory device 10 shown in FIG.

During the precharge period of T1, the precharge control signal PRE becomes low level and the precharge PMOS transistor 33 is turned on, while the load control signal LOAD becomes high level and the load PMOS transistor 34 is turned off. The potential of the selected word line WLs is low level and the transistor 24 is in the off state.

By applying the voltage of VCLMP to the gate terminal of the clamp NMOS transistor 36 of the clamp circuit, the potential of the selected bit line BLs is precharged to the potential obtained by subtracting VT (threshold of the clamp NMOS transistor 36) from VCLMP. The selected source line SLs is fixed to GND. The node SEN is precharged up to the power supply voltage VDD. Further, since the reset control signal RST of the resistance value counter 32 connected to the output of the comparator 31 is at high level, a fixed value of 0 is output as the count value COUNT_OUT from the output terminal of the resistance value counter 32. It

In the sense period of T2, the precharge control signal PRE is set to the high level to turn off the precharge PMOS transistor 33, and the load control signal LOAD is set to the low level to turn on the load PMOS transistor 34. The NMOS transistor 24 is turned on by setting the potential of the selected word line WLs to the high level.

Then, a voltage is applied from the selected bit line BLs to the selected source line SLs via the selected memory cell 21, and discharge is started. Simultaneously with the start of discharge, the reset control signal RST of the resistance value counter 32 becomes low level, and the resistance value counter 32 starts counting. Then, for each count, the comparator 31 compares the potential of the node SEN with the voltage of the reference voltage VREF, and the count value is continuously added until the node SEN falls below the reference voltage VREF. The higher the resistance value of the resistance change element 23 at the time of reading, the longer the discharge time and the larger the count value.

Also, the discharge time can be adjusted by adjusting the capacity of the capacitor 36a. If the capacitance of the capacitor 36a is large, the discharge time of the node SEN is also long, so the count value is large, and if the capacitance is small, the discharge time of the node SEN is short and the count value is small. Adjusting the capacitance of the capacitor 36a is effective, for example, when it is desired to improve the detection accuracy of a low resistance level where the discharge time is short. Since the counting interval is determined by the CLK signal, its operating frequency becomes the resolution of the counting value. However, when reading out a low resistance value, the discharge time may be close to the resolution of the count value, so that it may not be possible to distinguish the magnitude of the resistance value. Therefore, by adding a capacitive load to the node SEN and lengthening the discharge time, it is possible to intentionally secure the discharge characteristic at a level that can be detected with the resolution.

In the latch period of T3, the count value of the resistance value counter 32 when the node SEN becomes lower than the reference voltage VREF after the discharge is started is latched. The latched count value is output as COUNT_OUT and is treated as the count value of the resistance change element 23.

In the reset period of T4, when the data output of the resistance value counter 32 is completed, the potential of the selected word line WLs is set to the low level, the transistor 24 of the selected memory cell 21 is turned off, and the read operation is completed.

The count value COUNT_OUT stored in the resistance value counter 32 is input to the determination value setting circuit 13, and the determination value setting circuit 13 calculates a determination value (central value) based on the input count value COUNT_OUT.

Since the read circuit 12 shown in FIG. 7 has 16 sense amplifier circuits 30 in the nonvolatile memory device 10 according to the present embodiment, a maximum of 16 sense amplifier circuits 30 can be operated in parallel. You can

Next, an example of the operation of the non-volatile memory device 10 according to the present embodiment will be described. The non-volatile memory device 10 in this embodiment has five modes: a PUF registration mode, a PUF reproduction mode, a PUF reconstruction mode, a permanent PUF registration mode, and a permanent PUF data reproduction mode. These operations are selected by a control signal input from the outside, and the control circuit 15 executes the operation in each mode. The challenge data can be externally input to the control circuit 15 as a control signal, and the response data can be externally output from the data input/output circuit 6 as a data signal. In the following, the operation during execution of each mode will be described in detail.

(PUF registration mode)
In the PUF registration mode, the data generation circuit included in the nonvolatile memory device 10 is read from the first determination value set by the determination value setting circuit 13 and the memory cell 21 when the first type of challenge data is acquired. The first response data, which is PUF data, is generated by comparison with the resistance value and stored in the PUF area 8. Then, the data generation circuit, after generating the first response data, reconfiguration writing is executed by the reconfiguration processing circuit, and after the reconfiguration writing is executed, the first type of challenge data is acquired again. In this case, the third response data different from the first response data is generated and stored in the PUF area 8. That is, in this PUF registration mode, the non-volatile memory device 10 generates new PUF data that is updated by reconfiguration writing each time the first type of challenge data is acquired.

Hereinafter, the PUF registration mode will be described in detail with reference to FIGS. 10 and 11.

FIG. 10 is a flowchart showing an operation example when PUF data is registered by the non-volatile memory device 10 according to the present embodiment. FIG. 11 is a data flow diagram showing a method of generating helper data generated when PUF data is registered by the non-volatile memory device 10 according to the present embodiment.

In FIG. 10, when the first type of challenge data is input to the non-volatile memory device 10, in step S1, the resistance value of each memory cell 21 in the PUF region 8 set to the low resistance state is the sense amplifier circuit. In step S2, the judgment value setting circuit 13 calculates the median value of the variation distribution based on the read resistance value. In step S3, the median value calculated in step S2 is output to the read circuit 12 as a determination value, and in step S4, the read circuit 12 compares the determination value with the resistance value to obtain the first response data. Alternatively, PUF data is generated as the third response data. In step S5, the helper data that is error correction information of the generated PUF data is generated in the read circuit 12, and in step S6, the generated helper data is passed through the data input/output circuit 6 and the write circuit 14 and stored in the information area 7. Will be written to any specified address, and registration will be completed.

Next, a method of generating helper data by the read circuit 12 will be described with reference to FIG. In the present embodiment, the BCH(15+1,7) code is used as the correction code used when generating the helper data. BCH(15+1,7) uses 7 bits of information bits and 9 bits of parity bits as a total of 16 bits as code data, and is capable of error correction of 2 bits and error detection of 3 bits among 16 bits. In the generation of helper data, the 16-bit PUF data generated in step S4 of FIG. 10 is divided into upper 7 bits (P1) and lower 9 bits (P2). Next, 7-bit P1 is set as an information bit of the BCH code, and 9-bit parity data (E) corresponding to P1 is generated. 9-bit helper data (H) is obtained by XORing the generated 9-bit parity bit (E) and P2 of the generated PUF data. The generated helper data (H) is written and held in an arbitrary designated address in the information area 7 in the same manner as the normal memory data.

(PUF playback mode)
Next, the flow of PUF data reproduction will be described with reference to FIGS. 12 and 13.

FIG. 12 is a flowchart showing an operation at the time of PUF data reproduction by the non-volatile memory device 10 according to the present embodiment. FIG. 13 is a data flow showing a process by the non-volatile memory device 10 according to the present embodiment from raw PUF data including helper data used during PUF data reproduction and an error to reproduction of correct PUF data during registration. It is a figure.

In FIG. 12, in step S7, the resistance value of each memory cell in the PUF area 8 is read by the sense amplifier circuit 30. In step S8, the read resistance value is used to determine the median value by the determination value setting circuit 13, and in step S9, the detected median value is output to the read circuit 12 as the determination value. In step S10, the read circuit 12 compares the resistance value read in step S7 with the determination value set in step S9 to generate raw PUF data. Subsequently, the read circuit 12 reads the helper data stored at the time of PUF data registration in step S11, and the error correction circuit included in the read circuit 12 reads the raw PUF data obtained in step S9 and step S10 in step S12. Error correction is executed using the helper data read in step S13, and as a result, correct PUF data at the time of registration is acquired in step S13.

Next, an error correction method using helper data by the error correction circuit of the read circuit 12 in step S12 will be described with reference to FIG. The raw PUF data reproduced in step S10 may have an error due to the deterioration of the device over time and the influence of environmental changes during operation. In the following description, it is assumed that errors of e1 and e2 occur in P1 and P2 of 16-bit raw PUF data acquired during reproduction (however, e1+e2 is 2 bits or less). The helper data (H) read in step S11 and the lower 9 bits (P2+e2) of the raw PUF data are XOR-processed to reproduce the parity bit for the upper 7 bits generated at the time of PUF data registration. However, since the raw PUF data P2 contains an error of e2, it is actually reproduced as a parity bit (E+e2) containing an error of e2. Next, error correction is executed using the high-order 7-bit raw PUF data (P1+e1) and the reproduced parity data (E+e2). If e1+e2 is an error of 2 bits or less, the number of error bits is such that error correction is possible, so the original PUF data (P1) and parity data (E) are corrected, and correct P1 and E are reproduced. .. Finally, by XORing the correctly reproduced parity data (E) and helper data (H), the original correct P2 data is obtained, and correct 16-bit PUF data at the time of PUF data registration is acquired. You can

Note that the processing described with reference to FIGS. 12 and 13 is performed by the read circuit 12 and the like as described above, but is not limited to this, and may be performed by another component included in the nonvolatile memory device 10. , May be performed by a component external to the non-volatile memory device 10.

In general error correction, parity data (error correction data) corresponding to information data is added to perform error correction, and both the data and the parity data are stored in the nonvolatile memory. For example, when the parity data is added to the PUF data and stored in the non-volatile memory, the parity data is associated with the PUF data on a one-to-one basis, so the PUF data is inferred from the parity data information. You have a risk. However, the PUF data error correction method described in the present embodiment divides the PUF data into two, generates parity data corresponding to one PUF data, and then encrypts the other PUF data by XOR. Since the data generated by is stored as helper data, it is difficult to predict the original PUF data from the helper data. That is, the error correction method described above is more secure than the conventional error correction method.

(PUF reconstruction mode)
FIG. 14 is a flowchart showing an operation example of the PUF reconstruction mode by the non-volatile memory device 10 according to the present embodiment. In step S14, the control circuit 15 (that is, the reconfiguration processing circuit included in the non-volatile memory device 10) executes the reconfiguration writing that continuously processes the high resistance writing and the low resistance writing described in FIG. Then, according to the judgment in step S15, the reconfiguration writing is executed until the designated number of times is reached. The designated number of times (that is, the number of reconfiguration writes) used in the determination in step S15 is an effective parameter for improving the uniqueness of the PUF before and after the reconfiguration writing. FIG. 15 is a graph showing the Hamming distance between PUF data at each number of times generated when the reconstruction writing of FIG. 14 is executed 100 times, the horizontal axis being the Hamming distance, and the vertical axis being the normalized frequency. is there. 15A to 15C are graphs when the number of times of reconfiguration writing is changed to 1, 3, and 5, respectively. This graph based on the Hamming distance is used as an evaluation index for the uniqueness of PUF data, and the ideal value is that the width of the distribution is narrow and the center is 0.5 (that is, the values of half the bits are different). As shown in (a) to (c) of FIG. 15, comparing the distributions when the number of times of reconfiguration writing is changed to 1, 3, and 5 times, the number of times of reconfiguration writing is increased. It can be confirmed that the center of the distribution approaches 0.21, 0.24, 0.27 and 0.5, and the uniqueness is improved. That is, in the PUF reconfiguration mode, the number of reconfiguration writes is an important parameter for improving uniqueness. However, on the other hand, although the increase in the number of reconfigurations improves the uniqueness, a large amount of voltage stress is applied to the memory cells, which may reduce the reliability. Regarding the selection of the number of reconstructions, it is necessary to select the optimum number of times according to the uniqueness and reliability specifications required for the intended use.

(Permanent PUF registration mode)
In the permanent PUF registration mode, the data generation circuit included in the non-volatile memory device 10 reads the first determination value set by the determination value setting circuit 13 and the memory cell 21 when the second type challenge data is acquired. The second response data, which is PUF data, is generated by comparison with the determined resistance value and stored in the PUF area 8. The data generation circuit, after generating the second response data, executes the reconfiguration writing by the reconfiguration processing circuit, and again acquires the second type of challenge data after the reconfiguration writing is executed. In this case, the same fourth response data as the second response data is generated and stored in the PUF area 8. That is, in the permanent PUF registration mode, the non-volatile memory device 10 generates new PUF data that is not updated by reconfiguration writing every time the second type challenge data is acquired.

The operation in the permanent PUF data registration mode will be described below with reference to FIGS. 16, 17, and 18. FIG. 16 is a flowchart showing an operation example of the permanent PUF data registration mode by the nonvolatile memory device 10 according to the present embodiment. FIG. 17 is a diagram in which a description regarding the permanent PUF data registration mode is added to FIG. FIG. 18 is a diagram showing a specific example of data used for generating permanent PUF data by the nonvolatile memory device 10 according to the present embodiment. More specifically, FIG. 18A shows an example of the median value, the first permanent judgment value, and the second permanent judgment value, and FIG. 18B shows an example of the value of the resistance value register. 18C shows an example of PUF data and permanent information data.

In FIG. 16, in step S17, the resistance value of each memory cell in the PUF area 8 is read by the sense amplifier circuit 30. In step S18, the determination value setting circuit 13 determines the first permanent determination value that is set with a resistance value higher than the determination value used to generate the PUF data (hereinafter, also referred to as PUF determination value) and the PUF determination value. The second permanent judgment value set with a low resistance value is output (that is, set) to the reading circuit 12. Subsequently, the read circuit 12 compares the resistance value of each memory cell with the set first permanent judgment value and second permanent judgment value in step S19, and in steps S20 and S21, as shown in FIG. , A memory cell having a resistance value larger than the first permanent judgment value and smaller than the second permanent judgment value is assigned as “1” data, and the resistance value is smaller than the first permanent judgment value and larger than the second permanent judgment value. The memory cell is allocated as "0" data, and the data thus allocated is acquired as permanent information data (that is, mask data). Finally, in step S22, the read circuit 12 stores the acquired permanent information data in the designated information area 7 by the same method as the normal memory, and ends the processing. Since this permanent information data does not indicate permanent PUF data but data indicating the position (address) of the bit that is the target of the permanent PUF data, even if this data is stolen, the permanent PUF data is leaked. It can be said that there is no risk to

Hereinafter, an example of processing with a specific value will be described with reference to FIG. In FIG. 18, the acquired bits are 16 bits for simplification of description. For example, as shown in (a) of FIG. 18, the median value (that is, the PUF determination value) detected in advance by the determination value setting circuit 13 is 124, the set first permanent determination value is 210, and the first permanent determination value is 210. 2 Set the permanent judgment value to 40. When the resistance value of each memory cell measured by the sense amplifier circuit is read, the resistance value of each memory cell is stored in the resistance value register mounted in the read circuit 12 as shown in (b) of FIG. Is stored. Next, as shown in FIG. 18C, the read circuit 12 compares the obtained resistance value with the median value to generate PUF data (100011100010110 in the table), and further, By comparing the acquired resistance value with the first permanent judgment value and the second permanent judgment value, the permanent information data (1100010000010011 in the table) is generated. The permanent information data is stored and managed at a designated address in the information area 7.

(Permanent PUF playback mode)
Next, the permanent PUF data reproduction mode will be described with reference to FIGS. FIG. 19 is a flowchart showing an operation example of the permanent PUF data reproduction mode by the non-volatile memory device 10 according to the present embodiment. FIG. 20 is a diagram showing an example of generation of permanent PUF data by the non-volatile memory device 10 according to the present embodiment.

In FIG. 19, when the second type of challenge data is input to the nonvolatile memory device 10, the resistance value of each memory cell in the PUF area 8 is read by the sense amplifier circuit 30 in step S23, and in step 24. After the median value of the obtained resistance value is detected by the judgment value setting circuit 13, the detected median value is output (that is, set) as the judgment value to the reading circuit 12 in step S25. In step S26, the read circuit 12 compares the judgment value set in step S25 and the resistance value acquired in step S23 to obtain the raw PUF data. Subsequently, the read circuit 12 reads the helper data stored in the information area 7 of the nonvolatile memory in step S27, and the error correction circuit included in the read circuit 12 uses the helper data read in step S28. The error correction of the raw PUF data is executed, and the correct PUF data at the time of PUF data registration is acquired in step S29.

Next, in step S30, the reading circuit 12 reads the permanent information data generated in the permanent PUF data registration mode and stored in the information area 7, and in step S31, as shown in FIG. Only the bits assigned as data are extracted, and the PUF data that is the target bit is sequentially fetched from the upper bits. At this time, the permanent information data corresponds to 1 even if the reconfiguration writing in the PUF reconfiguration mode is executed once, twice,... N times in the PUF area 8 before the permanent PUF playback mode is executed. For the bits to be set, PUF data does not change, and a fixed value is always extracted as permanent PUF data. Since the target bits of this permanent PUF data are randomly present in the PUF area 8, if a plurality of memory cells read in parallel by the sense amplifier circuit 30 are used as a read memory group, a plurality of permanent PUF data are stored in the read memory group. It may or may not exist. That is, in step S32, the read circuit 12 determines whether or not the extracted cumulative permanent PUF data has reached 128 bits, and if it has not reached 128 bits, the read circuit 12 stores in the PUF area 8 as in step S33. The extraction of the permanent PUF data in the next read memory group is repeated. When the permanent PUF data becomes 128 bits, the operation ends, and the permanent PUF data is acquired as the second response data or the fourth response data.

The permanent PUF data may be extracted as raw PUF data without using error correction by helper data. The cause of an error in PUF data is that the resistance value of a memory cell near the median value fluctuates and exceeds the median value. However, as in the present embodiment, the permanent PUF data that does not use the vicinity of the median value adopts only the resistance value at a position away from the median value, in other words, only the data that is less likely to cause an error is used. It can be said that it is adopted.

Further, in the present embodiment, error correction processing is not performed on permanent PUF data, but error correction may be performed by generating helper data for permanent PUF data. If high reliability is required especially in a harsh environment such as in a vehicle, storing helper data for both PUF data and permanent PUF data in the information area 7 and performing error correction will improve reliability. It is possible to increase.

Further, the helper data of PUF data may not be stored in the information area 7, and only the helper data of permanent PUF data may be stored in the information area 7. When only permanent PUF data is used as valid PUF data without using PUF data, by registering only the helper data of the permanent PUF data, the helper data for the PUF data is not stored and the bits required for playback The number can be reduced.

As described above, the nonvolatile memory device 10 according to the present embodiment uses the memory cell array 20 including the plurality of resistance change type memory cells 21 and the memory cell array 20 when the challenge data is acquired. A data generation circuit (mainly a functional circuit realized by the control circuit 15, the read circuit 12, and the judgment value setting circuit 13) that generates response data, and a memory pulse that applies a voltage pulse at least once to the memory cell array 20. And a reconfiguration processing circuit (mainly a functional circuit realized by the control circuit 15 and the writing circuit 14) that executes the configuration writing, and the data generation circuit is non-volatile when the first type of challenge data is acquired. If unique first response data that is different for each memory device 10 is generated (PUF registration mode) and challenge data of the second type is acquired, unique second response data that is different for each non-volatile memory device 10 will be described. Is generated (permanent PUF registration mode) and the first response data is generated, reconfiguration writing is executed by the reconfiguration processing circuit, and the first type of challenge data is executed after the reconfiguration writing is executed. When reacquired, the third response data different from the first response data is generated (PUF registration mode), and after the second response data is generated, reconfiguration writing is executed by the reconfiguration processing circuit, Further, when the second type of challenge data is acquired again after the reconfigurable writing is executed, the same fourth response data as the second response data is generated (permanent PUF registration mode).

Accordingly, the non-volatile memory device 10 has a PUF registration mode in which new PUF data is generated by reconfiguration writing and a permanent PUF registration mode in which PUF data that does not change by reconfiguration writing is generated. Therefore, a non-volatile memory device having higher tamper resistance than a conventional non-volatile memory device in which new PUF data is always generated by reconfiguring writing is realized.

In addition, the memory cell array 20 includes a first area (information area 7) formed of the memory cells 21 holding a resistance value required to generate response data among the plurality of memory cells 21, and a plurality of memory cells. 21 of the memory cells 21, a second area (PUF area 8) formed of the memory cells 21 holding information other than the resistance value. As a result, since one non-volatile memory device 10 is provided with the second area for holding information other than the resistance value used for generating PUF data, the non-volatile memory device 10 is used only as a PUF data generating device. Instead, it can also be used as a general memory for storing various information.

The data generation circuit includes a read circuit that acquires resistance values from the plurality of memory cells 21 that form the memory cell array 20, and a judgment value setting circuit 13 that determines the first judgment value from the acquired resistance values. When the one type of challenge data is acquired, the first response data and the third response data are generated by comparing the first determination value and the resistance value. As a result, the first determination value used to generate PUF data can be dynamically determined by the determination value setting circuit 13.

The first determination value is the median value of the resistance values of a plurality of predetermined memory cells 21 among the plurality of memory cells 21. As a result, PUF data is generated by comparing the median value with the resistance value of each memory cell, so that the probability that "1" is generated and the probability that "0" are generated are substantially equal, and there is little bias. PUF data is generated.

Further, the data generation circuit uses the second judgment value smaller than the first judgment value and the third judgment value larger than the first judgment value, and is larger than the second judgment value and larger than the third judgment value. The first data is assigned to the memory cell 21 having a resistance value smaller than that, and the second data is assigned to the memory cell 21 having a resistance value smaller than the second determination value or larger than the third determination value. When the mask data (that is, the permanent information data) is generated and the second type of challenge data is acquired, the second response data is obtained by comparing the mask data with the first response data or the third response data. Alternatively, the fourth response data is generated. As a result, in the permanent PUF registration mode, since the mask data defined by the resistance value far apart from the first determination value is used, stable PUF data that is hard to change by reconstruction writing is generated.

In addition, the memory cell array 20 includes a first area (information area 7) formed of the memory cells 21 holding a resistance value required to generate response data among the plurality of memory cells 21, and a plurality of memory cells. The second area (PUF area 8) in which the mask data is stored. As a result, the mask data is stored in the second area of the non-volatile memory device 10, so it is not necessary to prepare a special storage device other than the non-volatile memory device 10 for storing the mask data.

In addition, the plurality of memory cells 21 included in the memory cell array 20 transition from the first resistance state to the second resistance state by performing the first write, and perform the second write different from the first write, The data generation circuit has a property of transitioning from the second resistance state to the first resistance state, and the data generation circuit uses the plurality of memory cells 21 set to the first resistance state among the plurality of memory cells 21 of the memory cell array 20. To generate response data. As a result, PUF data is generated using the resistance values of the memory cells in the same resistance state, which makes it more difficult to predict the generated PUF data and ensures high safety.

Further, the reconfiguration processing circuit, as reconfiguration writing, transitions the memory cell 21 in the first resistance state to the second resistance state by the first writing, and then changes it to the first resistance state by the second writing. Make a transition. As a result, even after the reconfiguration write is performed, the resistance state returns to the same resistance state as before the reconfiguration write is performed, so that it becomes more difficult to predict the PUF data generated before and after the reconfiguration write, which is high. Safety is secured.

In addition, the data generation circuit includes an error correction circuit and performs error correction on the response data. Thus, even if the PUF data stored in the non-volatile memory device 10 has a bit error due to long-term storage or the like, the original PUF data can be reproduced by error correction.

In addition, the memory cell array 20 includes a first area (information area 7) formed of the memory cells 21 holding a resistance value required to generate response data among the plurality of memory cells 21, and a plurality of memory cells. The second area (PUF area 8) of the memory cells 21 in which helper data required for error correction is stored. As a result, the helper data used for error correction is stored in the second area of the non-volatile memory device 10, so it is not necessary to prepare a special storage device other than the non-volatile memory device 10 for error correction.

In addition, the challenge-response method according to the present embodiment uses the non-volatile memory device 10 including the memory cell array 20 including a plurality of resistance change type memory cells 21 to generate response data corresponding to the challenge data. A response method, which includes a data generating step of generating response data using the memory cell array 20 when the challenge data is acquired, and a reconfiguration write for applying a voltage pulse to the memory cell array 20 at least once. In the data generation step, when the first type of challenge data is acquired, a unique first response data that is different for each non-volatile memory device 10 is generated (PUF registration mode). ), when the second type of challenge data is acquired, unique second response data different for each nonvolatile memory device 10 is generated (permanent PUF registration mode), and after generating the first response data, When the reconfiguration write is executed by the reconfiguration processing step, and when the first type challenge data is acquired after the reconfiguration write is executed, the third response data different from the first response data is generated. (PUF registration mode), after the second response data is generated, the reconfiguration writing is executed by the reconfiguration processing step, and the second type of challenge data is acquired after the reconfiguration writing is executed. Then, the same fourth response data as the second response data is generated (permanent PUF registration mode).

As a result, the nonvolatile memory device 10 realizes a PUF registration mode in which new PUF data is generated by reconfiguration writing and a permanent PUF registration mode in which PUF data that does not change by reconfiguration writing is generated. Therefore, as compared with the conventional nonvolatile memory device in which new PUF data is always generated by reconfiguring writing, a challenge/response method having higher tamper resistance is realized.

(Other embodiments)
Although the non-volatile memory device 10 and the challenge/response method according to the embodiment have been described above, the present disclosure is not limited to the above embodiment. Without departing from the gist of the present disclosure, various modifications made by those skilled in the art to the present embodiment, and other forms constructed by combining some of the components in the embodiment are also included in the scope of the present disclosure. Contained within.

For example, in the above embodiment, the generated helper data does not necessarily have to be stored in the information area 7, but may be stored in the server or an external recording medium.

Further, the control signals for controlling the PUF registration mode, PUF reproduction mode, PUF reconstruction mode, permanent PUF registration mode, and permanent PUF data reproduction mode described in the above embodiment are executed by a computer (computer system). Good. Then, it can be realized as a program to be executed by a computer. Further, the present disclosure can be realized as a non-transitory computer-readable recording medium such as a CD-ROM that records the program.

For example, when the present disclosure is realized by a program (software), each step is executed by executing the program by using hardware resources such as a CPU, a memory and an input/output circuit of a computer. .. That is, each step is executed by the CPU acquiring data from the memory or the input/output circuit or the like and performing the operation or outputting the operation result to the memory or the input/output circuit or the like.

In addition, each component included in the non-volatile memory device 10 in the above-described embodiment may be realized as a dedicated or general-purpose circuit.

Further, each component included in the non-volatile memory device 10 in the above-described embodiment may be realized as an LSI (Large Scale Integration) which is an integrated circuit (IC: Integrated Circuit).

Further, the integrated circuit is not limited to the LSI and may be realized by a dedicated circuit or a general-purpose processor. A programmable FPGA (Field Programmable Gate Array) or a reconfigurable processor in which connection and setting of circuit cells inside the LSI are reconfigurable may be used.

Furthermore, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally possible to carry out integrated circuit integration of the components included in the non-volatile memory device 10 using that technology. May be broken.

From the above description, many improvements and other embodiments of the present disclosure will be apparent to those skilled in the art. Therefore, the above description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of embodying the present disclosure. Details of its structure and/or function may be changed substantially without departing from the spirit of this disclosure.

The present disclosure is used as a non-volatile memory device having tamper resistance, and as a challenge/response method using the non-volatile memory device, for example, for electronic commerce services performed via the Internet, such as online banking and online shopping. It can be used as an encryption key generation device.

6 Data Input/Output Circuit 7 Information Area 8 PUF Area 10, 100 Nonvolatile Memory Device 12 Read Circuit 13 Judgment Value Setting Circuit 14 Write Circuit 15 Control Circuit 16 Address Input Circuit 17 Column Decoder Circuit 18 Row Decoder Circuit 20 Memory Cell Array 21 Memory Cell 22 Memory Main Unit 23 Resistance Change Element 24 Transistor 30 Sense Amplifier Circuit 31 Comparator 32 Resistance Value Counter 33 Precharge PMOS Transistor 34 Load PMOS Transistor 35 Comparator 36 Clamp NMOS Transistor 36a Capacitor 90 Memory Cell Array 91 Memory Cell 93 Control Device 120 Resistance Change Element 122 Base layer 124 First electrode 126 Resistance change layer 128 Second electrode 129 Transistor

Claims (11)

A non-volatile memory device,
A memory cell array composed of a plurality of resistance change type memory cells,
A data generation circuit that generates response data by using the memory cell array when the challenge data is acquired;
A reconfiguration processing circuit that executes reconfiguration writing by applying a voltage pulse at least once to the memory cell array,
The data generation circuit,
When the first type of challenge data is acquired, unique first response data different for each nonvolatile memory device is generated,
When the second type of challenge data is acquired, a unique second response data that is different for each nonvolatile memory device is generated,
When the reconfiguration writing is performed by the reconfiguration processing circuit after the first response data is generated, and the challenge data of the first type is acquired again after the reconfiguration writing is performed. , Generating a third response data different from the first response data,
When the reconfiguration writing is executed by the reconfiguration processing circuit after the second response data is generated, and the second type challenge data is acquired again after the reconfiguration writing is executed. , Generating the same fourth response data as the second response data,
Non-volatile memory device. The memory cell array includes a first region formed of memory cells that hold a resistance value required to generate the response data among the plurality of memory cells, and the resistance value of the plurality of memory cells. The non-volatile memory device according to claim 1, further comprising: a second region including a memory cell that holds information other than the above. The data generation circuit includes a read circuit that acquires a resistance value from a plurality of memory cells that form the memory cell array, and a judgment value setting circuit that determines a first judgment value from the acquired resistance value. When the challenge data of the type is acquired, the first response data and the third response data are generated by comparing the first determination value and the resistance value.
The non-volatile memory device according to claim 1. The first determination value is a median value of resistance values of a plurality of predetermined memory cells among the plurality of memory cells,
The non-volatile memory device according to claim 3. The data generation circuit uses a second judgment value smaller than the first judgment value and a third judgment value larger than the first judgment value, and is larger than the second judgment value and the third judgment value. First data assigned to a memory cell having a resistance value smaller than the determination value, and second data assigned to a memory cell having a resistance value smaller than the second determination value or larger than the third determination value. When the configured mask data is generated and the second type of challenge data is obtained, the second response data or the third response data is compared by comparing the mask data with the first response data or the third response data. Generating the fourth response data,
The non-volatile memory device according to claim 3 or 4. The memory cell array includes a first region of the plurality of memory cells that holds a resistance value necessary to generate the response data, and the mask data of the plurality of memory cells. A second area in which is stored,
The non-volatile memory device according to claim 5. The plurality of memory cells forming the memory cell array transition from the first resistance state to the second resistance state by performing the first write, and perform the second write different from the first write to perform the second write. Has the property of transitioning from the resistance state to the first resistance state,
The data generation circuit generates the response data using a plurality of memory cells set to the first resistance state among the plurality of memory cells of the memory cell array,
The non-volatile memory device according to claim 1. As the reconfiguration write, the reconfiguration processing circuit causes the memory cell in the first resistance state to transition to the second resistance state by the first write, and then performs the second write by the second write. Transition to 1 resistance state,
The non-volatile memory device according to claim 7. The non-volatile memory device according to claim 1, wherein the data generation circuit includes an error correction circuit, and performs error correction on the response data. The memory cell array includes a first region formed of memory cells holding a resistance value required to generate the response data among the plurality of memory cells, and the error correction of the plurality of memory cells. A second area composed of memory cells in which helper data necessary for performing
The non-volatile memory device according to claim 9. A challenge-response method for generating response data corresponding to challenge data by a nonvolatile memory device including a memory cell array composed of a plurality of resistance change type memory cells,
A data generation step of generating response data using the memory cell array when the challenge data is acquired,
A reconfiguration processing step of performing reconfiguration writing by applying a voltage pulse at least once to the memory cell array,
In the data generation step,
When the first type of challenge data is acquired, unique first response data different for each nonvolatile memory device is generated,
When the second type of challenge data is acquired, a unique second response data that is different for each nonvolatile memory device is generated,
When the reconfiguration writing is executed by the reconfiguration processing step after generating the first response data, and when the first type of challenge data is acquired after the reconfiguration writing is executed, Generate third response data different from the first response data,
When the reconfiguration writing is executed by the reconfiguration processing step after the second response data is generated, and when the second type challenge data is acquired after the reconfiguration writing is executed, Generate the same fourth response data as the second response data,
Challenge response method.