JP6793044B2 - Non-volatile memory device - Google Patents

Description

The present disclosure relates to a non-volatile memory device, and more particularly to a non-volatile memory device having a plurality of resistance-changing non-volatile memory cells.

The market for e-commerce services provided via the Internet, such as online banking and online shopping, is expanding rapidly. Electronic money is used as a payment method at this time, and the use of IC (“Integrated Circuit”, the same applies hereinafter) cards and smartphone terminals used as the medium is also expanding. For security at the time of payment, these services always require a higher level of security technology for mutual authentication in communication and encryption of communication data.

With regard to software technology, encryption technology for program processing centered on advanced encryption algorithms has been accumulated, and sufficient security has been achieved. However, due to technological advances, there is a rapidly growing concern that information inside the circuit can be read directly from the outside.

International Publication No. 2012/014291 Special Table 2013-545340

"A 0.19pJ / b PVT-Variation-Tolerant Hybrid Physically Uncle Toleration Circuit Circuit for 100% Table Secure Key Generation in 22nm CMOS" San. Mathew, et al. ISSCC2014 "Development and evaluation of anti-tamper-resistant VLSI system" Takeshi Fujino, "Basic technology of dependable VLSI system" CREST 2009 adopted theme 2012 performance report material “Comprehensive Assessment of RRAM®-based PUF for Hardware Security Applications” An Chen, IEDM2015

The present disclosure provides a non-volatile memory device having a function as a PUF capable of realizing low power consumption and area saving.

The non-volatile memory device according to one aspect of the present disclosure includes a memory cell array composed of a plurality of resistance-changing memory cells capable of holding data by utilizing a change in resistance value, and a plurality of memories from the memory cell array. By a read operation that acquires time information based on a discharge phenomenon or a charge phenomenon that depends on the resistance value of each of the plurality of memory cells in a unit of a memory group composed of cells, and a read operation by the read circuit. The memory cell array includes user data in which arbitrary data is stored, including a data generation circuit that generates individual identification information based on the order of the time information of the plurality of obtained memory cells in ascending or descending order. The read circuit and the data generation circuit have a region and a digital ID data region in which one of the two resistance states that can be reversibly transitioned is written, and the read circuit and the data generation circuit refer to the digital ID data region. The reading operation and the generation of the individual identification information are performed, respectively .

The present disclosure provides a non-volatile memory device having a function as a PUF capable of realizing low power consumption and area saving.

A block diagram showing an example of a schematic configuration of a resistance-changing non-volatile memory device according to an embodiment. Sectional drawing which shows an example of the schematic structure of the memory cell included in the resistance change type non-volatile memory apparatus which concerns on embodiment. A plot of the relationship between the normalized resistance value information in the set state of the digital ID and the deviation of the standard normal distribution for its variation. The figure which shows the relationship of the resistance value of the same address between each chip when writing is executed to the same address of two different chips X and Y. The figure explaining the mechanism of resistance change in a resistance change element A block diagram showing a specific configuration example of the non-volatile memory device of the embodiment. The figure which shows the configuration example of the read circuit and the data generation circuit provided in the non-volatile memory device. Circuit diagram showing a configuration example of a sense amplifier circuit included in a non-volatile memory device Timing chart when the sense amplifier circuit reads out the selected memory cell by the discharge method Timing chart showing rising edges of each Tout from k sense amplifier circuits Flow chart showing an operation example of the non-volatile memory device of the embodiment The figure which shows the relationship between the conversion signal input to a data conversion circuit and each mode executed by a data conversion circuit. Timing chart for explaining the data conversion of the data conversion circuit in the Tout output mode Timing chart for explaining the data conversion of the data conversion circuit in the SA address mode Explanatory drawing about the relationship between the processing signal input to the data processing circuit and the data processing method executed by the data processing circuit. The figure explaining the data processing of the data processing circuit in the even / odd system The figure explaining the data processing of the data processing circuit in the majority decision system Diagram showing an operation example of challenge-response authentication before shipping the terminal to the market Diagram showing an operation example of challenge-response authentication after the terminal is shipped to the market The figure which shows the application example to the unique ID data technology of a non-volatile memory device The figure which shows the example of data transmission and reception in the application example to the unique ID data technology The figure which shows the reading operation from a plurality of memory cells in the non-volatile memory apparatus which concerns on the 1st modification of embodiment A timing chart showing the order of reading time information and data conversion in the non-volatile memory device according to the first modification of the embodiment. A flowchart showing an operation example of the non-volatile memory device according to the first modification of the embodiment. A block diagram showing a detailed configuration of a control circuit included in the non-volatile memory device according to the second modification of the embodiment. A block diagram showing a detailed configuration of the SA0 control circuit to the SAk control circuit in FIG. 25A. A timing chart showing an operation example of a read circuit in the non-volatile memory device according to the second modification of the embodiment.

(Findings underlying this disclosure)
Generally, in an IC with enhanced security, confidential information is encrypted and used by using an internal encryption circuit to prevent information leakage. In this case, it is essential that the information of the encryption key (also referred to as "private key") held inside is not leaked to the outside.

Typical cryptographic circuit methods include 3DES (Triple Data Encryption Standard) and AES (Advanced Encryption Standard).
Standard) is widely used. For these encryption methods, even if the plaintext (pre-encryption data) -ciphertext pair that is the input / output is obtained and analyzed using the fastest computer, the encryption key is within a realistic time. An advanced encryption algorithm that cannot identify is adopted, and its security has been confirmed. However, even if hacking of encrypted data is said to be secure, there is concern about the vulnerability that the encryption key is directly hacked.

In the IC of the classical method, the encryption key is stored in the internal fuse ROM or non-volatile memory. The former configuration has a problem that the state of the fuse element is observed by X-ray projection or the like, the continuity / non-conduction of the fuse element is analyzed, and the stored key information is hacked. Further, although the latter configuration is not analyzed by X-ray projection, there is a problem that key information is hacked by directly applying probes to both ends of the memory element of the non-volatile memory and electrically reading the state of the element. Therefore, ICs with enhanced security are manufactured using the most advanced microprocess so that the probe cannot be directly applied to the internal circuit. That is, the threat of analysis by probing was avoided by manufacturing the IC by a fine process having a wiring rule smaller than the tip diameter of the probe of the latest technology.

However, side-channel attacks have begun to be taken against such countermeasures, and have become a threat. As described in Patent Document 1, a side-channel attack uses side-channel information such as power consumption of a semiconductor device during execution of each signal processing circuit and radiated electromagnetic waves depending on the power consumption to obtain an encryption key. It is a method to identify. The reason why this method is a threat is that an attacker (hacker) can hack key information during actual operation without physically damaging the IC.

The differential power attack (DPA: Differential Power Analysis), which is classified as such a side channel attack, was introduced in 1999 by P.I. Announced by Kocher. This DPA method utilizes the fact that there is a correlation between the signal value or signal transition frequency during IC operation and the power consumption. Specifically, the DPA method integrates such correlations many times and performs machine learning control while removing noise to derive a fixed pattern and specify key information. In the example of Patent Document 1, an example specified from the operation of the encryption processing circuit is shown. The key information stored in the non-volatile memory is read out at a timing triggered by executing the encryption process. In view of the principle of DPA, if the data read at the same timing as that timing is specified and acquired, there is a possibility that the data content will be analyzed by DPA. In addition, if the internal specifications of the IC are leaked, the hacker understands the control method of the IC, and as described above, all the data stored in the non-volatile memory is hard-copied including the encryption key information, and a copy of the IC is created. Will be done.

In recent years, in order to solve these problems, PUF (Physical Replication Uncle Function) technology has been proposed (Patent Document 2, Non-Patent Documents 1, 2, and 3).

PUF technology is an important technology that enhances security in performing encryption and mutual authentication securely.

The PUF technology is a technology for generating unique individual identification information that differs for each IC by utilizing manufacturing variations. Hereinafter, in the present specification, the individual identification information generated by the PUF technique is also referred to as "digital ID data". It can be said that the digital ID data is random number data unique to each device associated with variations in the physical characteristics of the IC. Since it is impossible to artificially control the physical properties of each IC, it is possible to generate data that cannot be physically duplicated.

Even if it is possible to control the variation in physical characteristics to some extent, it is easy to create unique digital ID data unique to each IC by PUF technology when using the random process variation generated during manufacturing. Is. However, it is practically extremely difficult to intentionally create a specific individual identification information determined in advance. Manufacturing variations occur in various physical properties in the semiconductor process. Examples of manufacturing variations include doping amount, oxide thickness, channel length, width and thickness of metal wiring layer, parasitic resistance and parasitic capacitance in a semiconductor process.

As a specific precedent example, SRAM-PUF such as Patent Document 2 and Non-Patent Document 1 can be exemplified. In these examples, in each memory cell in SRAM, it depends on whether the digital data of the initial value at the time of power-on tends to be in the 1 state or 0 state mainly due to the Vt variation (variation in the operating voltage) of the transistor. The phenomenon is used. This is unique and different for each SRAM cell mounted on each IC. That is, the initial value data when the power is turned on to the SRAM is used as the digital ID data.

In addition, Patent Document 1 and Non-Patent Document 2 introduce PUF techniques called arbiter PUF and glitch PUF. In the arbiter PUF and the glitch PUF, the output of the combinational circuit changes randomly with respect to the input by using the gate delay and the wiring delay. The gate delay and wiring delay that change due to manufacturing variations are unique delay amounts in each IC. Therefore, although it differs for each IC, each IC outputs substantially the same result for the input, so that digital ID data can be generated.

More recently, PUF technology using resistance value variation of ReRAM, which is a non-volatile memory, as in Non-Patent Document 3, has also been introduced. The ReRAM PUF is a method of generating unique data by writing two adjacent cells in the same state and comparing the magnitude relationship due to the variation in resistance value after writing.

In this way, the PUF technology generates digital ID data, which is a random number unique to each IC, as data that cannot be duplicated. This digital ID data is used as a device key for encrypting the above-mentioned private key. The private key encrypted by the device key (that is, digital ID data) is stored in the non-volatile memory in the encrypted state. That is, the encrypted private key recorded in the non-volatile memory can be decrypted into the original private key data only with the device key. Therefore, even if all the data in the non-volatile memory is hard-copied by hacking, the device key unique to each IC (that is, digital ID data) cannot be duplicated, so the encrypted private key cannot be restored and used. ..

As described above, PUF technology is an important technology for enhancing security in performing encryption and mutual authentication securely.

However, PUF technology is required to have low power consumption and area saving in order to incorporate it into various small IoT products such as IC cards, electronic devices, in-vehicle ECUs and sensors as well as security.

The present disclosure provides a non-volatile memory device having a function as a PUF capable of realizing low power consumption and area saving.

Before explaining the embodiment, the findings found in the experiments by the inventors of the present application will be described in connection with the principle of ReRAM. The following description is an example of data for understanding the present disclosure, and does not limit the present disclosure.

The non-volatile memory device has, for example, a function of generating individual identification information. In the non-volatile memory device, data is encrypted / decrypted based on the generated individual identification information, and mutual authentication can also be performed. More specifically, the non-volatile memory device according to the present disclosure reads the contents of the resistance change memory element, and at least partially derives a digital identifier from the contents, and is a unique random number unique to each chip for individual identification information. It has a function to generate data. This makes it possible to prevent electrical and physical replication.

The non-volatile memory device can be mounted on a card equipped with an IC chip used in, for example, mobile electronic money. The IC chip also includes a logic circuit, a volatile memory device, and a microprocessor. By using these, various information security functions such as encryption function, digital signature, and digital authentication function are realized. Data encryption with a private key is used when these functions are performed. As mentioned above, it is desirable to safely store the private key in the IC card so that it cannot be duplicated.

The above-mentioned PUF technology is used to realize the above-mentioned storage of the private key. The random digital ID data, which is the individual identification information obtained by the PUF technology, is used as the device encryption key, and the private key is encrypted and stored in the non-volatile memory. Since the digital ID data is a random number different for each IC, the data encrypted using the digital ID data is also a unique data string for each IC. Even if the encrypted private key is copied to another IC by hacking or the like, the digital ID data that cannot be duplicated is not copied, so that the original private key is not misused.

However, ultra-small devices such as IC cards are required to be highly miniaturized in circuits for generating digital ID data that embody PUF technology. Further, in a general IC card without a battery, it is necessary to execute various functions in a short time with the electric power obtained by wireless power supply during communication. That is, even in the generation of digital ID data, ultra-low power consumption and high generation speed are required at the same time. Therefore, the inventors of the present application have examined some prior arts as a generator of digital ID data that can meet such a demand.

Non-Patent Document 2 benchmarks various PUF techniques, which are precedent examples. Focusing on the error rate of digital ID data in particular, it is said that SRAM-PUF and glitch PUF deteriorate to a data error rate of 15% at worst in consideration of environmental changes. Considering the manufacturing yield, an error correction circuit that allows data errors of 20% or more is required, and the circuit scale becomes a hindrance to the IC. In addition, in the latest research in the case of SRAM-PUF, cells with extremely low errors have been reported as in Non-Patent Document 1, but since a dedicated memory cell with measures taken to reduce errors is used, The cell size is extremely large at 4.66 μm ² despite using the 22 nm process. Further, when a special SRAM cell for PUF is provided, the element can be easily identified, which causes a problem of tamper resistance.

The inventors of the present application have arranged the features of the PUF technology as follows. The features of PUF technology are considered to be summarized in the following two points.

Feature (1): Unique digital ID data (individual identification information) is obtained from a physical phenomenon that cannot be duplicated.
Feature (2): The physical phenomenon can be obtained only by dynamic circuit control, and the required physical phenomenon cannot be obtained by static analysis such as direct reading by a probe.

Furthermore, the inventors of the present application have summarized the main performances required for digital ID data obtained by the PUF technology as follows.

Performance (1): The digital ID data obtained by the PUF technology has high random number and becomes unique unique data for each IC.
Performance (2): Even if PUF technology is adopted, the overhead of the circuit to be added for that purpose is small, it is realized at low cost, and the power consumption when generating digital ID data is small.
Performance (3): By increasing the number of parallel processes of the generation circuit that generates each data bit, it is resistant to side channel attacks.
Performance (4): The error rate of data is small, and the circuit scale of the error correction circuit can be reduced.
Performance (5): There are few restrictions on the timing of generating digital ID data, and the generation speed is high.

With respect to the above-mentioned features and performance, the SRAM-PUF known as a conventional example has a large limitation in the performance (5). In principle, SRAM-PUF can only be obtained when the power is turned on. Since the SRAM inside the IC is used as a data cache, when ID data is generated by PUF, the data in the SRAM must be temporarily saved or discarded, which causes a big restriction on the system operation. Further, as a countermeasure against this, in order to generate at an arbitrary timing, it is necessary to separately provide a cell dedicated to PUF as in Non-Patent Document 1, and the overhead of the circuit increases. Therefore, the above performance (2) and ( It significantly reduces the requirement of 4).

The inventors of the present application have diligently studied a novel digital ID data generation method that may solve the above problems. As a result, the inventors of the present application have found a phenomenon in which the written resistance value of the resistance changing element varies in a normal distribution, and have come up with the idea of generating stable digital ID data from the variation in the resistance value.

The resistance change type memory element changes at least a first resistance state and a second resistance state having a resistance value smaller than that of the first resistance state by applying an electric pulse having a predetermined voltage, polarity and width. .. Normally, digital data (for example, "0" and "1") is assigned to the first resistance state and the second resistance state, and stored as information.

Here, the inventors of the present application pay attention to a group of cells belonging to any one of the above-mentioned first resistance state, the second resistance state, and the initial state described later, and each cell included in the cell group is selected. It was classified into two according to its resistance value. That is, each cell included in the cell group was binarized (digitalized). The resistance value of each cell varies, and by converting each cell into digital data using the variation, an unprecedented digital ID data generation method that can be applied to more secure and stable encryption technology, etc. It became possible to provide. This is one of the findings obtained by the inventors of the present application.

In addition, many circuit elements that generate digital ID data can be shared with circuits mounted as ordinary non-volatile memory devices. Therefore, the circuit scale that increases due to the generation of digital ID data can be greatly suppressed, and the size can be highly reduced.

Further, since the data read of the non-volatile memory device reads a plurality of data by parallel processing due to the structure of the memory cell array, the generation speed of digital ID data can be dramatically increased. At the same time, even in a side channel attack, the resistance to the attack can be improved because the radiated electromagnetic wave is given by the total number of parallel processes by parallel processing.

Based on the findings of the inventors of the present application, the outline of one aspect of the present disclosure is as follows.

The non-volatile memory device according to one embodiment of the present disclosure includes a memory cell array composed of a plurality of resistance-changing memory cells capable of holding data by utilizing a change in resistance value, and a plurality of memories from the memory cell array. By a read circuit that acquires time information based on a discharge phenomenon or a charge phenomenon that depends on the resistance value of each of the plurality of memory cells in a unit of a memory group composed of cells, and a read operation by the read circuit. A data generation circuit that generates individual identification information based on the order of the time information of the plurality of obtained memory cells in ascending or descending order is provided. The order in the ascending or descending order of the time information is the order in the ascending or descending order of the values indicated by the time information (the value of the number in a plurality of memory cells).

As a result, the individual identification information is generated by the data generation circuit based on the order of the time information depending on the resistance values of the plurality of resistance-changing memory cells read by the reading circuit. Therefore, individual identification information as PUF data based on low resistance variation in memory cells in the same resistance state is generated. Further, the circuit for generating individual identification information can be shared with the circuit mounted as a normal non-volatile memory device, which has a function as a PUF capable of realizing low power consumption and area saving. A non-volatile memory device is realized.

Here, the read circuit may simultaneously read the time information to at least two or more memory cells among the plurality of memory cells.

As a result, time information is read from a plurality of memory cells at the same time in units of memory groups, so that individual identification information is generated at high speed with high resistance to side channel attacks.

Further, the data generation circuit sets at least one of the plurality of memory cells in the memory group as a reference memory cell, and is a data generation memory cell excluding the reference memory cell among the plurality of memory cells. When the rank of the time information of the above is smaller than the rank of the time information of the reference memory cell, the first data is assigned to the data generation memory cell, and the rank of the time information of the data generation memory cell is changed. When the time information of the reference memory cell is larger than the rank, it has a data conversion circuit that performs data conversion for allocating the second data to the data generation memory cell, and the data after data conversion by the data conversion circuit. The individual identification information is generated based on the above.

As a result, at least one of the plurality of memory cells constituting the memory group is used as a reference memory cell for comparing the order of time information, so that the individual identification generated is compared with the case where the reference memory cell is fixedly set. The randomness of information is enhanced.

Further, the data generation circuit sets at least one of the plurality of memory cells in the memory group as a reference memory cell, and is a data generation memory cell excluding the reference memory cell among the plurality of memory cells. When the time information of the reference memory cell is compared with the time information of the reference memory cell, if the time information of the data generation memory cell is smaller than the time information of the reference memory cell, the first is the data generation memory cell. It has a data conversion circuit that allocates one data and allocates second data to the data generation memory cell when the time information of the data generation memory cell is larger than the time information of the reference memory cell. Then, the individual identification information may be generated based on the data after the data conversion by the data conversion circuit.

Specifically, the reference memory cell may be assigned to the memory cell corresponding to the upper M (M is 2 or more) th time information from the time information of the plurality of memory cells in the memory group. .. Further, the reference memory cell may be assigned to the memory cell corresponding to the upper N (N is a natural number) address among the addresses of the plurality of memory cells in the memory group.

As a result, at least one of the plurality of memory cells constituting the memory group is used as a reference memory cell for comparison of time information. Therefore, as compared with the case where the reference memory cell is fixedly set, the generated individual identification information Randomness is enhanced.

Further, the data conversion circuit may allocate the first data to the reference memory cell.

As a result, the individual identification information is generated after allocating the data to the reference memory cell as well. Therefore, the memory cell used for generating the individual identification information is compared with the case where the data is not assigned to the reference memory cell. The number of individuals is increased, and the randomness of the generated individual identification information is enhanced.

Further, one of the first data and the second data is an even number and the other is an odd number, and the data generation circuit is the first data and the second data allocated to the plurality of memory cells by the data conversion circuit. It has a data processing circuit that calculates the total of data, outputs the first data if the total number is odd, and outputs the second data if the total number is even, and data processing by the data processing circuit. The individual identification information may be generated based on the later data.

As a result, the individual identification information is generated after the data processing by the even / odd method is added to the digital data after the data conversion by the data conversion circuit in the data processing circuit, so that the data processing is added. Compared to the case without it, the randomness of the generated individual identification information is enhanced.

Further, the data generation circuit calculates the number of first data and the number of second data allocated to the plurality of memory cells by the data conversion circuit, and the number of the first data is the number of the second data. The data processing circuit has a data processing circuit that outputs the first data if the number is larger than the number, and outputs the second data if the number of the first data is smaller than the number of the second data. The individual identification information may be generated based on the data after the data processing by the circuit.

As a result, the individual identification information is generated after the data processing by the majority decision method is added to the digital data after the data conversion by the data conversion circuit in the data processing circuit. Therefore, when the data processing is not added. Compared with, the randomness of the generated individual identification information is enhanced.

Further, the data conversion circuit selects the data conversion method according to the conversion signal, the data processing circuit selects the data processing method according to the processing signal, and the data generation circuit is the individual. At the time of reproducing the identification information, the individual identification information may be generated by using the data conversion circuit and the data processing circuit based on the conversion signal and the challenge signal including the processing signal.

As a result, individual identification information, which is PUF data, is generated as a response based on the challenge signal including the conversion signal and the processing signal given from the outside, so that a non-volatile memory device that can be applied to highly secure challenge-response authentication can be used. It will be realized.

Further, the data conversion circuit selects the data conversion method according to the conversion signal, the data processing circuit selects the data processing method according to the processing signal, and the data generation circuit is the individual. At the time of reproducing the identification information, the individual identification information may be generated by inputting the predetermined fixed conversion signal and the processing signal to the data conversion circuit and the data processing circuit, respectively.

As a result, individual identification information, which is PUF data, is generated from a predetermined fixed conversion signal and processing signal, so that a non-volatile memory device that can be applied to a highly secure unique ID data system is realized.

Hereinafter, the details of the present disclosure based on these findings will be described with reference to the accompanying drawings.

Each of the embodiments described below is a specific example. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components, steps, the order of steps, and the like shown in the following embodiments are merely examples, and do not limit the present disclosure. Among the components in the following embodiments, the components not described in the independent claims indicating the highest level concept of the present disclosure are described as arbitrary components. Further, in the drawings, those having the same reference numerals may omit the description. Further, in order to make the drawings easier to understand, each component is schematically shown, and the shape, dimensional ratio, and the like may not be accurately displayed. Further, in the manufacturing method, the order of each step and the like can be changed as needed, and other known steps can be added.

(Embodiment)
(Overview of the resistance-changing non-volatile memory device used in the present disclosure)
FIG. 1 is a block diagram showing an example of a schematic configuration of the resistance change type non-volatile memory device 100 according to the embodiment. Further, FIG. 2 is a cross-sectional view showing an example of a schematic configuration of a memory cell 91 included in the resistance change type non-volatile memory device 100 according to the embodiment. In this specification, the resistance change type non-volatile memory device is also simply referred to as a non-volatile memory device.

In the example shown in FIG. 1, the resistance-changing non-volatile memory device 100 of the present embodiment includes at least a memory cell array 90 and a control device 93. The control device 93 does not necessarily have to be a part of the resistance change type non-volatile memory device 100, and the operation described below can be performed by using the control device connected to the outside of the resistance change type non-volatile memory device 100. You may be broken.

The memory cell array 90 is composed of a plurality of resistance-changing memory cells 91 capable of holding data by utilizing a change in resistance value, and in the present embodiment, the plurality of memory cells 91 are arranged in an array. Has.

The control device 93 acquires a plurality of resistance value information (specifically, time information corresponding to the resistance value) from a group of memory cells 91 having the same resistance value, and detects variation in the time information. Based on the detected time information, reference memory cells are set from the memory cell 91 group, and 0 or 1 is obtained by comparing each memory cell of the memory cell group in the same resistance state with the set reference memory cell. It is determined which value of the digital data is to be assigned, and the digital ID data is generated. The same resistance state means one resistance value range used for assigning one state of digital information. The control device 93 is a circuit including a read circuit described later and a data generation circuit. The read circuit is a read operation for acquiring time information from the memory cell array 90 in units of a memory group composed of a plurality of memory cells 91 based on a discharge phenomenon or a charge phenomenon depending on the resistance value of each of the plurality of memory cells 91. It is a circuit that performs at the same time. The data generation circuit is a circuit that generates individual identification information by comparing the time information of a plurality of memory cells 91 obtained by the read operation by the read circuit with each other.

Generally, in a non-volatile memory device, when a binary information, which is the minimum unit of a digital quantity, is assigned to a physical quantity of a memory cell, the physical quantity belongs to a range equal to or more than a predetermined threshold value or is less than a predetermined threshold value. Which of the binary information is assigned is changed depending on whether it belongs to a certain range of. A recent non-volatile memory device is provided with an error correction circuit. According to the error correction processing of the error correction circuit, even if the physical quantity of some memory cells does not fall within the range assumed in advance for allocating the binary information, the binary information obtained from the physical quantity is correct. It will be restored. This means that some of the memory cells forming the digital ID data do not have to be in the same resistance value range. As defined in the present specification, the various functions in the present disclosure can be achieved if at least half of the memory cells forming the digital ID data are in the same resistance state.

When generating digital ID data used as individual identification information of the resistance-changing non-volatile memory device 100, each resistance value is the first resistance state and the second resistance state described above, or the initial state described later. Multiple non-volatile memory cells belonging to the same resistance value range of any of the above are used. No user data is written to the plurality of non-volatile memory cells. That is, the resistance value is not rewritten. The resistance value of each non-volatile memory cell is fixed within a predetermined resistance value range. Each resistance value varies within the same resistance value range, and the variation becomes unique information of the resistance change type non-volatile memory device 100.

The "resistance value information" is information having a correlation with the resistance value, and may be the resistance value itself or a value that increases or decreases according to the resistance value. Values that increase or decrease according to the resistance value include, for example, the discharge time in which the electric charge accumulated in the capacitor connected in parallel with the memory cell is discharged through the selected memory cell, as described later. On the contrary, the charging time may be such that a predetermined constant current is passed through the discharged capacitor and the capacitor is charged to a predetermined level. The discharge time or charge time is an example of time information based on a discharge phenomenon or a charge phenomenon that depends on the resistance value of the memory cell, and specifically, even if it is a count value counted in a predetermined clock cycle or the like. Good. The capacitor is not limited to an element, and may be a parasitic capacitance such as wiring.

The resistance value information may be a value measured by a sense amplifier having a predetermined resolution. Alternatively, the resistance value information may be a value obtained by determining which of the plurality of resistance value ranges the value measured by the sense amplifier corresponds to, which is divided by the threshold value. In that case, each of the plurality of resistance value ranges may be a part of the resistance value ranges further divided.

In the example shown in FIG. 2, the resistance changing element 120 included in the memory cell 91 includes the base layer 122 (for example, Ta ₂ O ₅ ), the first electrode 124 (for example, Ir), and the resistance changing layer 126 (for example, TaO). _x ) and a second electrode 128 (for example, TaN) are provided. A transistor 129 for selecting a specific memory cell is connected to each memory cell 91.

The memory cell 91 has a property of being able to take a variable state in which a resistance value reversibly transitions between a plurality of variable resistance value ranges by applying a plurality of different electric signals.

The "initial state" means a state in which the resistance value is in the initial resistance value range that does not overlap with the variable resistance value range. The memory cell in the initial state does not become the variable state unless forming is performed. "Forming" refers to applying a predetermined electrical stress to a memory cell to change the memory cell so that the resistance value of the memory cell reversibly transitions between a plurality of variable resistance value ranges. Say.

The electrical stress applied for forming (forming stress) may be, for example, an electrical pulse having a predetermined voltage and time width, or may be a combination of a plurality of electrical pulses. .. The forming stress may be cumulative stress. In that case, when the cumulative amount of stress exceeds a predetermined amount, the memory cell 91 (FIG. 2) transitions from the initial state to the variable state.

In the present embodiment, it is assumed that the memory cell 91 has a property that the resistance value does not become a variable state in which the resistance value reversibly transitions between a plurality of variable resistance value ranges unless forming is performed after manufacturing. .. That is, the resistance changing element after being manufactured by a semiconductor process or the like and before the forming stress is applied will be described as being in the initial state.

However, this property is an example and is not essential. The memory cell 91 does not have to be an element capable of taking an initial state, and may be, for example, a so-called formingless element having only a variable state.

With reference to FIG. 3, the characteristics of the resistance value variation of the memory cell in the set state of the digital ID (the state in which “0” or “1” is written) will be described. FIG. 3 is a diagram in which the relationship between the standardized resistance value information of the memory cell in the set state of the digital ID and the deviation of the standard normal distribution with respect to the variation of the standardized resistance value information is plotted (triangular marks are plotted). .. As shown in this figure, the normal distribution of memory cells is distributed almost linearly with respect to the resistance value information. From this, it is shown that the variation in the resistance distribution is an extremely random phenomenon.

With reference to FIG. 4, the reason why the digital ID data cannot be duplicated (that is, the duplication is extremely difficult) with the non-volatile memory device of the present disclosure will be described. In FIG. 4, writing is executed for the same address of two different chips X and Y under the two conditions of write condition A (plot of x mark) and condition B (plot of circle mark), respectively, and the horizontal axis is The relationship between the resistance values of the same address between the chips is shown when the resistance value of the chip X and the vertical axis are the resistance values of the chip Y. As is clear from FIG. 4, the relationship between the resistance value and the same condition under the same conditions is not visible at all. This is the same even if the condition A and the condition B in which the writing voltage and the pulse width are changed are compared. That is, when further binary data is generated from a memory group having the same resistance state, it is impossible (that is, extremely difficult) to write arbitrary data separately for an arbitrary address.

Next, the reason why it is extremely difficult to duplicate the digital ID data will be described while associating with the mechanism of resistance change in the resistance change element used in the present embodiment. As shown in FIG. 5, the resistance changing element is formed by applying a high voltage to cause dielectric breakdown from the initial insulating state, and a conductive path called a filament is formed in the resistance changing layer. This filament is formed by a series of oxygen deficiencies caused by oxygen deficiency in the resistance change layer due to forming. The location and number of oxygen deficiencies that occur are random for each element. Further, the resistance in which a relatively large amount of oxygen deficiency is generated is low, and the resistance of an element having a relatively small number of deficiencies is high, resulting in variation. Such variations are uncontrollable (that is, extremely difficult to control), and when oxygen deficiency is often formed and filament paths are likely to be formed, the resistance value of the resistance changing element becomes lower. On the other hand, when the density of oxygen deficiency is even partially low, the filament path is difficult to form, so that the resistance value of the resistance changing element becomes higher. The resistance value of each element varies, and such variation cannot be artificially controlled (that is, it is extremely difficult to control).

(Configuration and circuit basic operation of resistance-changing non-volatile memory device)
FIG. 6 is a block diagram showing a specific configuration example of the non-volatile memory device 10 of the embodiment. Note that FIG. 6 is merely an example, and the specific configuration of the non-volatile memory device of the embodiment is not limited to the configuration shown in FIG.

As shown in FIG. 6, the non-volatile memory device 10 of the embodiment includes a memory main body 22 on a semiconductor substrate. The non-volatile memory device 10 further includes a data input / output circuit 6, a control circuit 15, and an address input circuit 16.

The memory main body 22 includes a read circuit 11, a write circuit 14, a column decoder circuit 17, a row decoder circuit 18, a data generation circuit 25, and a memory cell array 20.

The writing circuit 14 applies a predetermined voltage in each operation to the selected memory cell 21 to write data.

The read circuit 11 acquires time information from the memory cell array 20 based on a discharge phenomenon or a charge phenomenon depending on the resistance value of each of the plurality of memory cells 21 in a unit of a memory group composed of a plurality of memory cells 21. It is a circuit that performs operations simultaneously (in parallel). In this embodiment, a change in the current flowing through a bit line is detected by a read-out method (discharge phenomenon) described later, and resistance value information of a selected memory cell is obtained. Output as time information.

The data generation circuit 25 is a circuit that generates individual identification information by comparing the time information of a plurality of memory cells 21 obtained by the read operation by the read circuit 11 with each other. In the present embodiment, the data generation circuit 25 is a binary digital ID. A reference memory cell as a reference for generating data is set, and binary digital ID data (output Dout) is generated based on the time information of each memory cell.

The low decoder circuit 18 selects one word line WL from a plurality of n word line WLs connected to the memory cell array 20.

The column decoder circuit 17 includes k bit lines BL, which is the number of parallel reads (the number of memory cells constituting the memory group) from the plurality of n bit lines BL and the plurality of n source lines SL, and k lines of the bit lines BL. The corresponding k source lines SL are selected and connected to the write circuit 14 and the read circuit 11.

These (write circuit 14, read circuit 11, data generation circuit 25, row decoder circuit 18 and column decoder circuit 17) operate according to the number of rows and / or columns in which reads and / or writes are performed in parallel.

The read circuit 11 of the non-volatile memory device 10 has an output Tout as time information. In the read circuit 11, k memory cells (that is, memory groups) selected by the column decoder circuit 17 and the row decoder circuit 18 are connected via k bit lines, and time information of k memory cells is obtained. Toout is transmitted to the data generation circuit 25.

Further, the data generation circuit 25 converts the input Tout into binary digital ID data Dout based on the conversion signal and the processing signal given from the outside. That is, the data generation circuit 25 uses the time information (Tout) obtained from the read circuit 11 to convert it into binary digital ID data, and transmits it to the data input / output circuit 6 as an output Dout.

As shown in FIG. 6, the memory main body 22 has a user data area 7 and a digital ID data area 8 as storage areas. Arbitrary user data (user data) is stored in the user data area 7. The writing and reading of the user data is performed by selecting the address of the user data area 7. In the digital ID data area 8, the same resistance state is written in the memory cell group in order to derive individual identification information that is difficult to duplicate and is used as digital ID data. As a result, digital ID data (individual identification information) is output from the data generation circuit 25 as the output Dout.

The user data area 7 and the digital ID data area 8 do not need to be divided into word line units as shown in FIG. 6, and may be divided into arbitrary areas on the memory cell array 20. The more complicated the regularity of the physical area division, the more resistant it is to attacks such as hacking.

The memory cell array 20 is divided into a user data area 7 for WL0, WL1, WL2, ... WLm-1 and a digital ID data area 8 for WLm, ... WLn in word line units, and (1) parallel to each other. Multiple word lines WL0, WL1, WL2, ... WLm-k-1, WLm-k, ... WLm formed so as to extend to (2) intersecting and parallel to the plurality of word lines. A plurality of bit lines BL0, BL1, ... BLn formed so as to extend to, and (3) formed so as to intersect with a plurality of word lines and extend parallel to each other and parallel to the bit lines. The source lines SL0, SL1, SL2, ... SLn are provided. Memory cells 21 are arranged at the three-dimensional intersections of the plurality of word lines and the plurality of bit lines.

Each memory cell 21 includes a resistance changing element 23 and a transistor 24, as shown in FIG. The word lines WL0, WL1, WL2, ... WLm-k-1, WLm-k, ... WLm are connected to the gate terminals of the respective transistors 24, and the bit lines BL0, BL1, ... BLn are respectively. The first electrode of the resistance changing element 23 is connected to the second electrode of the resistance changing element 23 included in the memory cell 21, and the first electrode of the resistance changing element is connected to the second main terminal of the transistor 24, respectively, and the source lines SL0, SL1, SL2, ... SLn Are connected to the first main terminal of the transistor 24, respectively.

The resistance changing element 23 operates as a non-volatile memory element in the memory cell 21. The non-volatile memory device 10 is a so-called 1T1R type resistance change type non-volatile memory device in which each memory cell 21 is composed of one transistor 24 and one resistance change element 23. The selection element of the memory cell is not limited to the above-mentioned transistor. For example, a two-terminal element such as a diode may be used.

Based on the control signal, the control circuit 15 selects either a bit line or a source line for the column decoder circuit 17 and connects it to the write circuit 14 at the time of writing and to the read circuit 11 at the time of reading. Then, the writing circuit 14 or the reading circuit 11 is operated.

Since the resistance changing element 23 can have the same configuration as the resistance changing element 120 described above in the embodiment, detailed description thereof will be omitted.

In the example shown in FIG. 6, an NMOS transistor is used as the selection transistor of the memory cell array 20, but the method is not limited to this, and a NMOS transistor may be used.

FIG. 7 is a diagram showing a configuration example of a read circuit 11 and a data generation circuit 25 included in the non-volatile memory device 10 according to the embodiment. The read circuit 11 has k sense amplifier circuits 30 (SA0, SA1, SA2, ... SAk) by a discharge method in order to simultaneously acquire time information in units of a memory group consisting of k memory cells. doing. The k bit lines selected from the column decoder circuit 17 are connected to the sense amplifier circuit 30 by the k discharge method. Each sense amplifier circuit 30 outputs each time information and transmits it to the data generation circuit 25. As a result, among the plurality of memory cells 21 constituting the memory cell array 20, each of the plurality of memory cells 21 with respect to the memory group consisting of the plurality of memory cells 21 selected by the selected word line WL and the column decoder circuit 17. A read operation for acquiring time information is performed at the same time based on the discharge phenomenon that depends on the resistance value of.

The data generation circuit 25 is a circuit that generates digital ID data (individual identification information) by comparing the time information of a plurality of memory cells 21 obtained by the read operation by the read circuit 11 with each other, and is the data conversion circuit 28 and the data. It is composed of a processing circuit 29. A conversion signal is input to the data conversion circuit 28, and a processing signal is input to the data processing circuit 29.

The data conversion circuit 28 sets at least one of the plurality of memory cells 21 in the memory group as the reference memory cell, and sets the time information of the data generation memory cell excluding the reference memory cell among the plurality of memory cells 21. When comparing with the time information of the reference memory cell, if the time information of the data generation memory cell is smaller than the time information of the reference memory cell, the first data is assigned to the data generation memory cell and the data is generated. If the time information of the memory cell is larger than the time information of the reference memory cell, data conversion for allocating the second data to the data generation memory cell is performed. In the present embodiment, in the data conversion circuit 28, a reference memory cell is set based on the conversion signal, and each time information obtained from Tout from the read circuit 11 is binarized as 0 or 1 data. That is, in the data conversion circuit 28, the data conversion method is selected according to the conversion signal.

The data processing circuit 29 is a circuit that adds a process for converting the data binarized by the data conversion circuit 28 into another data based on the processed signal. That is, in the data processing circuit 29, the data processing method is selected according to the processing signal.

A conversion signal input to the data conversion circuit 28 and a method of setting a reference memory cell in the data conversion circuit 28 based on the conversion signal, and a processing signal input to the data processing circuit 29 and data processing based on the processing signal. The data processing method in the circuit 29 will be described in detail later.

FIG. 8 is a circuit diagram showing a configuration example of a sense amplifier circuit 30 included in the non-volatile memory device 10 according to the embodiment. Note that the memory cell 21 connected to the sense amplifier circuit 30 is also shown in this figure. The sense amplifier circuit 30 is one of the k sense amplifier circuits 30 that constitute the read circuit 11, and includes a comparator 31, a precharging MOSFET transistor 33, a loading MOSFET transistor 34, and a clamping NMOS transistor 36. And have.

In the comparator 31, the voltage of the node SEN is input to one input terminal, VREF as a reference voltage is input to the other end, and the output is connected to the data generation circuit 25 as time information Tout.

In the precharge epitaxial transistor 33, the precharge control signal PRE is input to the gate terminal, the power supply voltage VDD is input to the source terminal, and the node SEN is connected to the drain terminal.

In the load epitaxial transistor 34, a load control signal LOAD is input to the gate terminal, a power supply voltage VDD is input to the source terminal, and a node SEN is connected to the drain terminal.

In the clamping NMOS transistor 36, the clamp control signal CLMP is input to the gate, the node SEN is connected to either the source terminal or the drain terminal, and the other end is the memory cell 21 selected via the column decoder circuit 17. Is connected. Note that the column decoder circuit 17 is not shown in FIG.

A capacitor 136 is connected to the node SEN as a load capacitance.

Here, the operation of the sense amplifier circuit 30 to output the count value (an example of the resistance count value) which is the time information is concretely described by using the configuration diagram (FIG. 8) and the timing chart of FIG. 9 of the sense amplifier circuit 30. Explain to.

FIG. 9 is a timing chart when the sense amplifier circuit 30 reads out the memory cells selected in the embodiment by the discharge method.

During the precharge period of T1, the precharge control signal PRE is at a low level and the precharge epitaxial transistor 33 is on, while the load control signal LOAD is at a high level and the load epitaxial transistor 34 is off. The potential of the selected word line WLs is low and the transistor 24 is in the off state.

When the voltage of VCLMP is applied to the gate terminal of the clamping NMOS transistor 36, the potential of the selected bit line BLs is precharged to the potential obtained by subtracting VT (threshold value of the clamping NMOS transistor 36) from VCLMP. The selected source lines SLs are fixed to GND. The node SEN is precharged up to the power supply voltage VDD.

In the sense period of T2, the precharge control signal PRE is set to a high level to turn off the precharge epitaxial transistor 33, and the load control signal LOAD is set to a low level, so that the load epitaxial transistor 34 is turned on. Become. Further, by setting the potential of the selected word line WLs to a high level, the NMOS transistor 24 is turned on.

Then, a voltage is applied to the selected source line SLs via the memory cell 21 selected from the selected bit line BLs, and discharge is started. The discharge is carried out until a predetermined sense period of T2. During the discharge time, the potential of the node SEN and the voltage of the reference voltage VREF are continuously compared, and while the potential of the node SEN exceeds the reference voltage VREF, the Tout outputs the GND level, but the potential of the node SEN is the reference voltage. As soon as it falls below VREF, Tout reverses from GND to the power supply voltage VDD. The period (discharge time) from the start of discharge to the rise (rising edge) of Tout depends on the resistance value of the connected memory cell 21. The higher the resistance value of the resistance changing element 23 at the time of reading, the longer the discharge time. This discharge time is an example of time information based on a discharge phenomenon or a charge phenomenon that depends on the resistance value of the memory cell 21.

During the standby period of T3, the node SEN is fixed to GND, the precharge control signal PRE is at a low level, the precharging epitaxial transistor 33 is in the ON state, while the load control signal LOAD is at a high level, and the loading ProLiant transistor is at a high level. 34 is in the off state. The potential of the selected word line WLs is low and the transistor 24 is turned off.

It is also possible to adjust the discharge time by adjusting the capacity of the capacitor 136 described above. If the capacitance of the capacitor 136 is large, the discharge time of the node SEN is long, and if the capacitance is small, the discharge time of the node SEN is short. The capacitor 136 is effective, for example, when it is desired to improve the detection accuracy of a low resistance level having a fast discharge time. However, in the case of a low resistance value, the discharge time may exceed the resolution of the count value, so that it may not be distinguishable. Therefore, by adding a capacitive load to the node SEN and extending the discharge time, it is possible to intentionally adjust the discharge characteristics to a level that can be detected with resolution. However, in principle, in the case of the discharge method, the higher the resistance, the longer the discharge time, and the slope of the discharge changes gently accordingly, so that the resolution of the time information with respect to the count value is improved. That is, in the case of the discharge method, the high resistance side can obtain highly accurate time information.

Further, as shown in FIG. 7, since the read circuit 11 has k sense amplifier circuits 30 in the non-volatile memory device 10 of the present embodiment, a maximum of k sense amplifier circuits 30 can be operated in parallel at the same time. It becomes possible to make it.

FIG. 10 shows the rising edge of each Tout when different memory cells 21 in the digital ID data area 8 configured in the same resistance state are connected to k sense amplifier circuits 30 and discharge is started at the same timing. A timing chart showing (that is, time information) is shown. Although there are k nodes SEN, FIG. 10 shows the nodes SEN in an superimposed manner for the sake of explanation. As shown in FIG. 10, even in the same resistance state, there is a slight variation in resistance value for each memory cell, so that it can be confirmed that the timing of the rising edge of Tout is different. That is, by operating k sense amplifier circuits 30 of the present embodiment at the same time, the variation (ranking of resistance values) of each resistance value in the k memory cell group (that is, the memory group) can be adjusted with high accuracy and high speed. It is possible to detect.

(System operation of resistance-changing non-volatile memory device)
FIG. 11 is a flowchart showing an operation example of the non-volatile memory device 10 of the embodiment. Hereinafter, the operation of the non-volatile memory device 10 will be described with reference to FIG. Here, the generation processing of digital ID data (individual identification information) by the reading circuit 11 and the data generation circuit 25 (data conversion circuit 28 and data processing circuit 29) is shown.

In step S31, the mode / processing is selected by inputting the conversion signal and the processing signal to the data generation circuit 25. Each of these modes and processes will be described in detail later. Subsequently, in step S32, the data conversion circuit 28 sets one bit as a reference memory cell from the memory group consisting of k memory cells 21 in parallel operation based on the mode selection selected in step S31. .. In step S33, the k sense amplifier circuits 30 start discharging at the same time, and each Tout outputs a rising edge. In step S34, the data conversion circuit 28 includes the rising edge of the Tout of the reference memory cell set in step S32 and the rising edge of the Tout of the other memory cell (that is, the data generation memory cell) from the memory group. Is compared, and one data (“1”) is allocated to the bits (that is, the memory cell for data generation) output by Tout earlier than the output of Tout in the reference memory cell, as in step S35, and the reference memory is used. 0 data (“0”) is assigned to the bits (that is, the data generation memory cell) output by Tout later than the cell output, as in step S36. That is, the data conversion circuit 28 sets at least one of the plurality of memory cells in the memory group as the reference memory cell, and sets the time information of the data generation memory cell excluding the reference memory cell among the plurality of memory cells. When comparing with the time information of the reference memory cell, if the time information of the data generation memory cell is smaller than the time information of the reference memory cell, the first data is assigned to the data generation memory cell and the data is generated. If the time information of the memory cell is larger than the time information of the reference memory cell, data conversion for allocating the second data to the data generation memory cell is performed.

In step S37, the data conversion circuit 28 determines whether all the bits other than the reference memory cell in the memory group have been compared with the reference memory cell and data allocation has been completed. If not, the next step is in step S38. Update to the address of and execute data allocation for the remaining memory cells. In step S39, the data processing circuit 29 further performs data processing on the digital data assigned by the data conversion circuit 28 based on the data processing method selected in step S31. In step S40, the data generation circuit 25 determines whether or not the execution of data allocation has been completed for all the memory groups in the digital ID data area 8, and if it is the final memory group, the process is completed. If it is not completed, as shown in step S41, the mode of S31 and the data processing method are selected in the next memory group. By completing the data processing for the final memory group in this way, digital ID data (individual identification information) is generated from the data generation circuit 25.

Next, in the process of generating the digital ID data of the non-volatile memory device 10 according to the embodiment, the mode / process selection in step S31 in FIG. 11 described above, the reference memory cell setting in step S32 reflected after the process, and step S37 The data processing of the above will be described in detail. FIG. 12 shows the relationship between the conversion signal input to the data conversion circuit 28 and each mode executed by the data conversion circuit 28. The mode selection here indicates a method of data conversion by the data conversion circuit 28 in step S32, and more specifically, a method of selecting and setting a reference memory cell by the data conversion circuit 28. Specifically, when a digital ID is generated for a memory group consisting of k memory cells that are read in parallel, the conversion signal is a conversion signal α (or signal β) that selects a mode. ) And the parameter value i required for mode execution are input to the data conversion circuit 28, so that the reference memory cell that serves as the reference for binarization is determined. Specifically, when the signal α is input, the Tout output mode is selected, and when the signal β is input, the SA address mode is selected. The signal including the signal α or the signal β and the parameter value i may be a conversion signal.

[When Toout output mode (signal α) is selected]
The data conversion in the data conversion circuit 28 when the signal α in the Tou output mode and the parameter value j are input to the data conversion circuit 28 will be described with reference to the timing chart of FIG. A memory group consisting of k memory cells in the same resistance state in the digital ID data area 8 is connected to each of k sense amplifier circuits 30, and discharge is started at the same timing in the sense period of T2. Although each memory cell is in the same resistance state, the discharge characteristics (that is, the time information output from each sense amplifier circuit 30) are different depending on each memory cell because there is a slight resistance variation. That is, since the rising edge output when the potential of the node SEN falls below the VREF is also different, it is possible to rank the magnitude of the resistance value in the memory group consisting of k memory cells. In this Tout output mode, the memory cell that outputs the rising edge at the jth parameter value from the k memory groups is assigned as the reference memory cell. In the example shown in FIG. 13, the memory cell of Tout_1 rises to the jth position and outputs an edge. Therefore, in binary data output, the rising edge of Tout_1 is used as a reference, 1 data is assigned to Tout that rises earlier than the rising edge of Tout_1, and 0 data is assigned to Tout that rises later. Will be assigned. As described above, in the Tout output mode, the reference memory cell corresponds to the upper M (M is 2 or more) th time information from the time information of the plurality of memory cells in the memory group depending on the parameter value. Assigned to a memory cell.

[When SA address mode (signal β) is selected]
The data conversion in the data conversion circuit 28 when the signal β which is the conversion signal indicating the SA address mode and the parameter value h are input to the data conversion circuit 28 will be described with reference to the timing chart of FIG. Similar to the Tout output mode, the memory groups in the same resistance state in the digital ID data area 8 are operated at the same timing to rank the magnitude of each resistance value. As for the parameter value h input in the SA address mode, the memory cell connected to the Tout_hth sense amplifier circuit 30 in Tout_0 to Tout_k is assigned as the reference memory cell. As shown in FIG. 14, in the sense period T2, rising edges are output from Tout at different timings. In the example shown in FIG. 14, the rising edge of Tout_h is output to the fifth memory group. In the SA address mode, since the memory cell of Tout_h is allocated as the reference memory cell, one data is allocated to the memory cell that started up earlier than Tout_h (1st to 4th), and the timing is late (6 to 6 to 4). 0 data is allocated to the kth) memory cell. As described above, in the SA address mode, the reference memory cell becomes the memory cell corresponding to the upper N (N is a natural number) th address among the addresses of the plurality of memory cells in the memory group, depending on the parameter value. Assigned.

Note that the handling of the reference memory cell as data in the present embodiment shows an example in which it is not treated as data, but the present invention is not limited to this. 0 data may be assigned or 1 data may be assigned to the memory cell assigned as the reference memory cell. That is, the data conversion circuit 28 may allocate the first data or the second data to the reference memory cell.

Next, the data processing by the data processing circuit 29 executed in step S37 in FIG. 11 will be described. FIG. 15 is an explanatory diagram of the relationship between the processing signal input to the data processing circuit 29 and the data processing method executed by the data processing circuit 29. The data processing circuit 29 adds additional data processing to the binary digital data output from the data conversion circuit 28, depending on the processing signal A (or B or C). The processing signal A indicates an even / odd system, the processing signal B indicates a majority voting system, and the processing signal C indicates that processing is not performed.

[When even / odd number method (signal A) is selected]
When the signal A is input to the data processing circuit 29 as a processing signal, the data processing circuit 29 executes the even / odd method. The even / odd number method will be described with reference to the example of FIG. In the example of FIG. 16, a memory cell (that is, a memory group) that simultaneously executes parallel reading is set to 4 bits, a signal α (a signal for selecting the Tou output mode) is input to the data conversion circuit 28, and a parameter value 3 is set. It has been entered. After the reading circuit 11 starts reading the four bits at the same time, the rising edge of the Tout is output in order according to the variation in the resistance value. In the data conversion circuit 28, since the parameter value is set to 3, the memory cell that outputs the third rising edge is assigned as the reference memory cell, and other memory cells (that is, data) are allocated according to the reference memory cell. The output of the generation memory cell) is converted into digital data of 1 and 0. In the even / odd system, the data processing circuit 29 calculates the sum of the digital data of the memory groups output from the data conversion circuit 28, and performs data processing depending on whether the calculated value is even or odd. In the present embodiment, an even number is 0 and an odd number is 1. In the example of FIG. 16, since the sum of the data conversion circuits 28 is an even number, the final output of the data processing circuit 29 is output as 0.

As described above, in the even / odd method, the data processing circuit 29 calculates the total of the first data and the second data allocated to the plurality of memory cells by the data conversion circuit 28, and if the total number is odd. Data processing is performed to output the first data, and if it is an even number, output the second data. One of the first data and the second data is an even number, and the other is an odd number.

[When the majority voting method (signal B) is selected]
When the signal B is input to the data processing circuit 29 as the processing signal, the data processing circuit 29 executes the majority decision method. The majority voting method will be described with reference to the example of FIG. The results of the preconditions (number of parallel read bits, conversion mode, and output order of the rising edge of Tout) up to the data processing circuit 29 of FIG. 17 are all the same as those of FIG. In the majority decision method, the data processing circuit 29 calculates the number of 1's and the number of 0's of the digital data output from the data conversion circuit 28, and compares the number difference. Then, the data processing circuit 29 outputs 1 if the number of 1s is large, and outputs 0 if the number of 0s is large. In the example shown in FIG. 17, the number of 1s is 2, the number of 0s is 1, and the number of 1s exceeds the number of 0s, so that the final output of the data processing circuit 29 is output as 1.

As described above, in the majority decision method, the data processing circuit 29 calculates the number of the first data and the number of the second data allocated to the plurality of memory cells by the data conversion circuit 28, and the number of the first data is the first. If the number of data is larger than the number of 2 data, the first data is output, and if the number of the first data is smaller than the number of the second data, the second data is output.

As described above, depending on how the data processing method is selected, there are cases where different data is output even if the output from the data conversion circuit 28 is the same. By adding the data processing circuit 29, it becomes difficult to predict the data output from the data conversion circuit 28 and the output data of the data processing circuit 29, which improves security and a random number of digital ID data for the occurrence of a circuit failure. The effect of maintaining sexuality is expected.

This circuit defect indicates, for example, a defect of the sense amplifier circuit 30 at the initial stage after manufacturing. It is assumed that a problem occurs in the xth sense amplifier circuit 30 among the k sense amplifier circuits 30, and the rising edge is always output with the longest delay regardless of the resistance state of the memory cell. At this time, in the reproduction of the digital ID data, the digital data of each memory group is generated in the order of the address, but due to the problem of the xth sense amplifier, the same value is always output to the xth memory cell, so this is the data. As a result of giving periodicity to the data, the randomness is reduced. In the data processing circuit 29 described in the present embodiment, even if a problem occurs in the sense amplifier circuit 30 that outputs fixed data, if another sense amplifier circuit 30 that operates in parallel is operating, Since the data is enriched by the processing and the finally output data can be changed, the randomness can be maintained.

When the signal C of FIG. 15 is input, the data processing circuit 29 may output the data as it is unprocessed. When it is not processed, the data of the accessed memory cell can be output by one playback because the enrichment by data processing is not added, and the amount of information is large. In terms of data output speed, there are merits.

[System application example of the resistance change type non-volatile memory device of this embodiment]
The digital ID data generation method described in the present embodiment can be applied to, for example, a challenge-response authentication technique between a host side such as a server and a device side of a terminal. Challenge-response authentication is to send a challenge (input) registered in advance on the host side to the terminal side, and the receiving terminal side responds to the input and returns the response (output) unique to that terminal to the host side. , The host side is a method of authenticating by comparing the registered expected value and the response value. An example of using the challenge-response authentication method in the present embodiment will be described with reference to FIGS. 18 and 19. As shown in FIG. 18, the server side transmits a plurality of challenge values to a specific terminal (ReRAM device Z) side before shipping to the market, and after obtaining a unique response value for them, the response value is set. to register. In the digital ID data generation method described in the present embodiment, the challenge value corresponds to a conversion signal, a parameter value, and a processing signal input to the data generation circuit 25 included in the terminal (ReRAM device Z). Further, the response value corresponds to the digital ID data (individual identification information) output by the data generation circuit 25 included in the terminal (ReRAM device Z).

As shown in FIG. 19, in the authentication of the terminal after shipping to the market, the server side arbitrarily selects the challenge value from the challenge values registered before shipping, sends it to the terminal side, and receives the terminal. , Returns the response value according to the challenge value. The server that receives the response value collates with the response value registered in advance, and if they match, the authentication is completed.

In this example, the authentication is completed by collating the challenge value and the response value once, but if security is to be improved, the authentication may be performed by repeating the challenge value and the response value multiple times. possible.

As described above, when the non-volatile memory device 10 is applied to the challenge response authentication, the data generation circuit 25 receives the challenge signal including at least the conversion signal and the processing signal at the time of reproducing the digital ID data (individual identification information). Based on the above, the data conversion circuit 28 and the data processing circuit 29 are used to generate digital ID data (individual identification information).

Further, the digital ID data generation method described in the present embodiment can also be applied to the unique ID data technology. An example of application to the unique ID data technology in this embodiment will be described with reference to FIGS. 20 and 21. As shown in FIG. 20, a predetermined fixed value is stored in the user data area 7 of the non-volatile memory device 10 of the embodiment. The fixed values here are conversion signals, parameter values, and processed signals used when reproducing digital ID data. In the unique ID data, the resistance value information (specifically, time information) read from the digital ID data area 8 which is the PUF area is reproduced by the data generation circuit 25 using the fixed value, so that challenge response authentication is performed. Unlike the challenge, there is no external input, and the same ID is always output during playback. In FIG. 20, the reading circuit 11 is not shown for the sake of brevity. This unique ID data uses the common private key data as a key for encryption. The common secret key data encrypted with the unique ID data is stored in the user data area 7 as the secret encryption key data.

Next, FIG. 21 shows an example of data transmission / reception according to this embodiment. Both the device A on the transmitting side and the device B on the receiving side have the non-volatile memory device 10 of the present embodiment, and each of them is a user as secret key encrypted data in which common secret key data is encrypted with unique ID data. It is stored in the data area 7. When transmitting a message, the device A on the transmitting side has a data generation circuit in which a fixed value stored in the user data area 7 and time information obtained from the digital ID data area 8 which is the PUF area via the read circuit 11 are used. The secret key encryption data is input to the encryption circuit 1 using the unique ID data A obtained by being input to the 25, and is decrypted as the common secret key data. The decrypted common private key data inputs a plaintext message into the encryption circuit 2 and transmits it to the device B as an encrypted message. On the device B side as well as the device A, the unique ID data B obtained from the data generation circuit 25 is decrypted from the common secret key data via the encryption circuit 1. The received encrypted message is decrypted into a plaintext message via the encryption circuit 2 by using the common private key.

By the method of using the unique ID data described above, it is possible to more strongly protect the common private key. For example, even if the secret encryption key data in the user data area 7 is stolen and forged and copied to another device, it cannot be decrypted because the unique ID data for decrypting the secret encryption key data is different for each device. That is, it is possible to prevent the spread of counterfeit devices after data leakage.

As described above, when the non-volatile memory device 10 is applied to the unique ID data, the data generation circuit 25 receives a predetermined fixed conversion signal and processing signal at the time of reproducing the digital ID data (individual identification information). Are input to the data conversion circuit 28 and the data processing circuit 29, respectively, to generate digital ID data (individual identification information).

As described above, the non-volatile memory device 10 according to the present embodiment has a memory cell array 20 composed of a plurality of resistance-changing memory cells 21 capable of holding data by utilizing a change in resistance value, and a memory. A read circuit that simultaneously performs a read operation for acquiring time information from the cell array 20 in units of a memory group consisting of a plurality of memory cells 21 based on a discharge phenomenon or a charge phenomenon that depends on the resistance values of the plurality of memory cells 21. 11 and a data generation circuit 25 that generates individual identification information by comparing the time information of a plurality of memory cells 21 obtained by the read operation by the read circuit 11 with each other.

As a result, the time information depending on the resistance values of the plurality of resistance-changing memory cells read by the read-out circuit 11 is compared with each other in the data generation circuit 25, and individual identification information is generated. Therefore, individual identification information as PUF data based on low resistance variation in memory cells in the same resistance state is generated. Further, the circuit for generating individual identification information can be shared with the circuit mounted as a normal non-volatile memory device, which has a function as a PUF capable of realizing low power consumption and area saving. A non-volatile memory device is realized.

In the above embodiment, the read circuit 11 simultaneously performs read operations for acquiring time information for a plurality of memory cells 21, but it is not always necessary to perform read operations at the same time.

FIG. 22 is a diagram showing a read operation from a plurality of memory cells in the non-volatile memory device according to the first modification of the above embodiment. Here, an example is shown in which reading time information and generating individual identification information are performed in units of a memory group consisting of a plurality of 32-bit memory cells, but reading operations are not necessarily performed for all 32-bits at the same time. Shown.

As shown in FIG. 22, in this non-volatile memory device, a read operation is performed in units of a memory group consisting of a memory cell 20 to a 32-bit memory cell 21, but all of the 32-bit memory cells 21 are read at the same time. Instead, the read operation is sequentially performed in units of eight divided 4-bits (subgroups) (division 0 to division 7). It should be noted that the read operation is performed at the same time in each 4-bit (subgroup) unit.

Further, in the example shown in FIG. 22, one bit belonging to the division 1 is set in the reference memory cell 21a, and the data conversion circuit 28 provides time information smaller than the time information (resistance count value) of the reference memory cell 21a. "1" is assigned to the data, and "0" is assigned to the time information larger than the time information of the reference memory cell 21a.

FIG. 23 is a timing chart showing the order of reading time information and data conversion in the non-volatile memory device according to this modification. The 32-bit memory cell 21 is sequentially subjected to a read operation in units of eight 4-bits (subgroups) divided, and then converted into 32-bit data by the data conversion circuit 28. That is, the data conversion circuit 28 performs a process of assigning "0" or "1" to 32-bit data ("0/1 conversion").

FIG. 24 is a flowchart showing an operation example of the non-volatile memory device according to this modification. In this flowchart, “PUF region resistance value reading (S33)” in the flowchart of FIG. 11 showing an operation example of the above embodiment is performed in eight steps (“division 0 reading resistance value storage (S33a)” to “division 7 reading”. It corresponds to the one replaced by the resistance value storage (S33c) "). The eight steps (“division 0 read resistance value storage (S33a)” to “division 7 read resistance value storage (S33c)”) are sequentially performed in units of eight 4-bits (subgroups) shown in FIG. Corresponds to the read operation of.

As described above, as shown in this modification, the operation of reading the time information in units of the memory group composed of the plurality of memory cells 21 does not need to be read simultaneously for all the plurality of memory cells 21. All the plurality of memory cells 21 may be read out at different timings, or may be sequentially read out in units of subgroups obtained by dividing a memory group composed of the plurality of memory cells 21.

Further, in the above embodiment, the data generation circuit 25 generates individual identification information by comparing the time information of the plurality of memory cells 21 obtained by the read operation by the read circuit 11 with each other, but the time information is not necessarily generated by each other. It is not necessary to compare, and individual identification information may be generated based on the order of the time information of the plurality of memory cells 21 in ascending or descending order.

FIG. 25A is a block diagram showing a detailed configuration of the control circuit 15a included in the non-volatile memory device according to the second modification of the above embodiment. Here, the configuration of the control circuit 15a suitable for generating individual identification information based on the order of the time information of the plurality of memory cells in the ascending or descending order is shown.

The control circuit 15a has a sense amplifier control circuit 40 that performs predetermined control based on control signals (set value signal T1 and signal X) input from the outside, in addition to the functions of the control circuit 15 in the above embodiment. .. The sense amplifier control circuit 40 selects whether to perform sense start (discharge start timing) simultaneously for each sense amplifier circuit 30 constituting the read circuit 11 or at a time set for each sense amplifier circuit 30.

The signal X switches between the sense start at the same time (fixed time mode) and the set time for each sense amplifier circuit 30 (time adjustment mode) for each sense amplifier circuit 30 constituting the read circuit 11. Mode selection signal.

The set value signal T1 is a signal indicating information indicating a sense start time for each sense amplifier circuit 30 in the time adjustment mode.

The sense amplifier control circuit 40 includes a timer circuit 41 and SA0 control circuits 42a to 42d.

The timer circuit 41 supplies common time information to the SA0 control circuits 42a to 42d.

The SA0 control circuit 42a to the SAk control circuit 42d are provided corresponding to the respective sense amplifier circuits 30 constituting the read circuit 11, and output a signal indicating the timing of the sense start to the corresponding sense amplifier circuit 30. It is a circuit. FIG. 25B is a block diagram showing a detailed configuration of the SA0 control circuit 42a to the SAk control circuit 42d. The SA0 control circuit 42a to the SAk control circuit 42d have a set value holding unit 45 and a signal sequencer 46, respectively.

The set value holding unit 45 is a memory that holds information (set value T1) at a time indicated for the corresponding sense amplifier circuit 30 among the information indicated by the set value T1. When the signal X indicates the fixed time mode, the signal sequencer 46 outputs a signal indicating the start of sense to all the sense amplifier circuits 30 at the same timing according to the time information from the timer circuit 41. On the other hand, when the signal X indicates the time adjustment mode, the signal sequencer 46 outputs a signal indicating the start of sense at the timing when the time information from the timer circuit 41 reaches the set value T1 held in the set value holding unit 45. Output.

FIG. 26 is a timing chart showing an operation example of the read circuit 11 in the non-volatile memory device according to this modification. FIG. 26A shows an operation example in the fixed time mode, and FIG. 26B shows an operation example in the time adjustment mode. In FIGS. 26A and 26B, the timing of discharge in the four sense amplifier circuits 30 (SA0 to SA3) and the “rank” detected by the data conversion circuit 28 are shown.

As shown in FIG. 26 (a), when the signal X indicates a fixed time mode, the sense amplifier circuits 30 (SA0 to SA3) simultaneously start discharging under the control of the sense amplifier control circuit 40. , Signals Tout_0 to Tout_3 indicating the timing T2 of the end of discharge are output. Therefore, the data conversion circuit 28 detects the order in the order of the earliest discharge end timing T2 (that is, the order of the smallest time information based on the discharge, that is, the ascending order). In this example, ranks 1, 2, 3, and 4 are detected in the order of SA1, SA3, SA2, and SA0.

On the other hand, as shown in FIG. 26B, when the signal X indicates the time adjustment mode, the sense amplifier circuits 30 (SA0 to SA3) have the corresponding settings under the control of the sense amplifier control circuit 40. The discharge is started at the time corresponding to the value T1, and the signals Tout_0 to Tout_3 indicating the timing T2 of the end of the discharge are output. Therefore, in the data conversion circuit 28, the order is detected in the order of the earliest discharge end timing T2 (that is, the order of the smallest time information based on the discharge, that is, the ascending order). In this example, ranks 1, 2, 3, and 4 are detected in the order of SA2, SA0, SA1, and SA3. In this modification, the order is given in ascending order of time information, but the order may be given in descending order of time information.

After that, the data conversion circuit 28 outputs the first data (for example, "1") to the memory cell that outputs the time information having a rank smaller than the rank of the time information corresponding to the reference memory cell 21a, as in the above embodiment. ”) Is assigned, and data conversion is performed in which the second data (for example,“ 0 ”) is assigned to the memory cell that outputs the time information having a rank higher than the rank of the time information corresponding to the reference memory cell 21a. The data obtained by the data conversion is output from the data generation circuit 25 as individual identification information after being subjected to data processing in the data processing circuit 29, as in the above embodiment.

As described above, in the present modification, the non-volatile memory device includes a memory cell array 20 composed of a plurality of resistance-changing memory cells 21 capable of holding data by utilizing a change in resistance value, and a memory cell array 20. A read circuit 11 that performs a read operation to acquire time information based on a discharge phenomenon or a charge phenomenon depending on the resistance value of each of the plurality of memory cells 21 in a unit of a memory group composed of the plurality of memory cells 21. A data generation circuit 25 that generates individual identification information based on the order of the time information of the plurality of memory cells 21 obtained by the read operation by the read circuit 11 in the ascending or descending order is provided.

As a result, the individual identification information is generated by the data generation circuit 25 based on the order of the time information depending on the resistance values of the plurality of resistance-changing memory cells 21 read by the reading circuit 11. Therefore, individual identification information as PUF data based on low resistance variation in memory cells in the same resistance state is generated. Further, the circuit for generating individual identification information can be shared with the circuit mounted as a normal non-volatile memory device, which has a function as a PUF capable of realizing low power consumption and area saving. A non-volatile memory device is realized.

Further, the sense amplifier control circuit 40 can start operation at a time set for each sense amplifier circuit 30 based on the signal of the signal X.

This makes it possible to eliminate the dependence of the resistance value of each of the plurality of memory cells 21 on the time information based on the discharge phenomenon or the charging phenomenon. Therefore, for example, the data can be estimated from the acquisition of the resistance value against a physical attack such as probing. Is difficult, so security can be improved.

Further, the data generation circuit 25 sets at least one of the plurality of memory cells 21 in the memory group as the reference memory cell 21a, and the data generation memory cell excluding the reference memory cell 21a among the plurality of memory cells 21. If the order of the time information of the reference memory cell 21a is smaller than the order of the time information of the reference memory cell 21a, the first data is allocated to the data generation memory cell, and the order of the time information of the data generation memory cell is the reference memory cell 21a. It has a data conversion circuit 28 that performs data conversion that allocates second data to the data generation memory cell when it is larger than the order of time information, and individual identification is performed based on the data after data conversion by the data conversion circuit 28. Generate information.

As a result, at least one of the plurality of memory cells 21 constituting the memory group is used as the reference memory cell 21a for comparing the order of time information, so that the reference memory cell 21a is generated as compared with the case where the reference memory cell 21a is fixedly set. The randomness of individual identification information is enhanced.

It should be noted that many improvements and other embodiments of the present disclosure will be apparent to those skilled in the art from the above description. Therefore, the above description should be construed as an example only and is provided for the purpose of teaching those skilled in the art the best embodiments embodying the present disclosure. The details of its structure and / or function can be substantially modified without departing from the spirit of the present disclosure.

The non-volatile memory device according to the present disclosure stably and highly securely generates unique digital ID data that cannot be duplicated due to variations in the resistance values of the resistance change type memory elements contained in the memory device, and uses the digital ID data. It is useful for mounting on ICs, System on Chips, etc. that access data encryption and access to host computers and servers with authentication.

6 Data input / output circuit 7 User data area 8 Digital ID data area 10 Non-volatile memory device 11 Read circuit 14 Write circuit 15, 15a Control circuit 16 Address input circuit 17 Column decoder circuit 18 Row decoder circuit 20 Memory cell array 21 Memory cell 21a See Memory cell 22 Memory body 23 Resistance change element 24 Transistor 25 Data generation circuit 28 Data conversion circuit 29 Data processing circuit 30 Sense amplifier circuit 31 Comparator 33 Precharge plica transistor 34 Load MIMO transistor 36 Clamping NMOS transistor 40 Sense amplifier control Circuit 41 Timer circuit 42a to 42d SA0 to SAk Control circuit 45 Set value holding unit 46 Signal sequencer 90 Memory cell array 91 Memory cell 93 Control device 100 Resistance change type non-volatile memory device 120 Resistance change element 122 Base layer 124 First electrode 126 Resistance Change layer 128 Second electrode 129 Transistor 136 Capsule

Claims (11)

A memory cell array consisting of multiple resistance-changing memory cells that can hold data using changes in resistance value,
A read circuit that performs a read operation to acquire time information from the memory cell array in units of a memory group composed of a plurality of memory cells based on a discharge phenomenon or a charge phenomenon depending on the resistance value of each of the plurality of memory cells. ,
A data generation circuit that generates individual identification information based on the order of the time information of the plurality of memory cells obtained by the read operation by the read circuit in ascending or descending order is provided .
The memory cell array has a user data area in which arbitrary data is stored and a digital ID data area in which one of two resistance states that can be reversibly transitioned is written.
The read circuit and the data generation circuit perform the read operation and the generation of the individual identification information for the digital ID data area, respectively.
Non-volatile memory device. The non-volatile memory device according to claim 1, wherein the read circuit simultaneously reads the time information from at least two or more memory cells among the plurality of memory cells. The data generation circuit
At least one of the plurality of memory cells in the memory group is set as a reference memory cell, and the order of the time information of the data generation memory cell excluding the reference memory cell among the plurality of memory cells is the above. When the time information of the reference memory cell is smaller than the rank, the first data is assigned to the data generation memory cell, and the rank of the time information of the data generation memory cell is the time information of the reference memory cell. It has a data conversion circuit that performs data conversion that allocates second data to the data generation memory cell when it is larger than the above rank.
The non-volatile memory device according to claim 1 or 2, which generates the individual identification information based on the data after data conversion by the data conversion circuit. The data generation circuit
At least one of the plurality of memory cells in the memory group is set as a reference memory cell, and time information of a data generation memory cell excluding the reference memory cell among the plurality of memory cells and the reference memory cell. When the time information of the data generation memory cell is smaller than the time information of the reference memory cell, the first data is assigned to the data generation memory cell and the data generation is performed. It has a data conversion circuit that performs data conversion that allocates second data to the data generation memory cell when the time information of the memory cell for data is larger than the time information of the reference memory cell.
The non-volatile memory device according to claim 1 or 2, which generates the individual identification information based on the data after data conversion by the data conversion circuit. The third or four claim, wherein the reference memory cell is assigned to the memory cell corresponding to the upper M (M is 2 or more) th time information from the time information of the plurality of memory cells in the memory group. Non-volatile memory device. The non-volatile memory device according to claim 3 or 4, wherein the data conversion circuit allocates the first data to the reference memory cell. The non-volatile according to claim 3 or 4, wherein the reference memory cell is assigned to the memory cell corresponding to the upper N (N is a natural number) th address among the addresses of the plurality of memory cells in the memory group. Memory device. One of the first data and the second data is an even number, and the other is an odd number.
The data generation circuit
The total of the first data and the second data allocated to the plurality of memory cells by the data conversion circuit is calculated, the first data is output if the total number is odd, and the second data is output if the total number is even. It has a data processing circuit that processes the data to be output.
The non-volatile memory device according to any one of claims 3 to 7, which generates the individual identification information based on the data after data processing by the data processing circuit. The data generation circuit
The number of first data and the number of second data allocated to the plurality of memory cells by the data conversion circuit are calculated, and if the number of the first data is larger than the number of the second data, the first data Is provided, and if the number of the first data is smaller than the number of the second data, the data processing circuit for performing the data processing for outputting the second data is provided.
The non-volatile memory device according to any one of claims 3 to 7, which generates the individual identification information based on the data after data processing by the data processing circuit. The data conversion circuit selects the data conversion method according to the conversion signal.
The data processing circuit selects the data processing method according to the processing signal and selects the data processing method.
When the individual identification information is reproduced, the data generation circuit generates the individual identification information by using the data conversion circuit and the data processing circuit based on the conversion signal and the challenge signal including the processing signal. The non-volatile memory device according to claim 8 or 9. The data conversion circuit selects the data conversion method according to the conversion signal.
The data processing circuit selects the data processing method according to the processing signal and selects the data processing method.
When the individual identification information is reproduced, the data generation circuit inputs the predetermined fixed conversion signal and the processing signal to the data conversion circuit and the data processing circuit, respectively, so that the individual identification information can be obtained. The non-volatile memory device according to claim 8 or 9.

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