CN108241585A - Large capacity nvm interface controller - Google Patents
Large capacity nvm interface controller Download PDFInfo
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- CN108241585A CN108241585A CN201611213755.5A CN201611213755A CN108241585A CN 108241585 A CN108241585 A CN 108241585A CN 201611213755 A CN201611213755 A CN 201611213755A CN 108241585 A CN108241585 A CN 108241585A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
- G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Software Systems (AREA)
- Storage Device Security (AREA)
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Abstract
This application provides large capacity NVM interface controllers.The NVM interface controller provided, including command queue and NVM command processing unit, NVM command processing unit is coupled to multiple NVM chips, command queue is used to receive I/O command, NVM command processing unit is used to obtain I/O command from command queue, and NVM interface order is sent to NVM chips according to the instruction of I/O command or receives data or state from NVM chips, NVM command processing unit includes multiple processing units, for accessing corresponding NVM chips, it is characterized in that, NVM command processing unit is coupled to the CE ports of NVM chips by one or more CE expanders, NVM command processing unit is additionally operable to by the way that CE expanders is set to send out chip enable signal to specified NVM chips, to access corresponding NVM chips.
Description
Technical field
This application involves technical field of memory more particularly to large capacity NVM interface controllers.
Background technology
Nand flash memory, phase transition storage, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic
Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistance-change memory
Device) etc. be common NVM (Non-Volatile Memory, nonvolatile storage).
Memory target (Target) is that the shared chip in the encapsulation of flash memory particle enables (CE, Chip Enable) signal
One or more logic units (Logic Unit), each logic unit have logical unit number (LUN, Logic Unit
Number).It may include one or more tube cores (DIE) in nand flash memory encapsulation.Typically, logic unit corresponds to single pipe
Core.Logic unit may include multiple planes (Plane).Multiple planes in logic unit can be with parallel access, and nand flash memory
Multiple logic units in chip can perform order and report state independently of one another.http：//www.onfi.org/ ~/media/ONFI/specs/ONFI_3_ 2%20Gold.pdf" the Open NAND Flash Interface obtained
In Specification (Revision 3.2) ", provide about target (target), logic unit, LUN, plane
(Plane) meaning and the order for also providing operation NVM chips.
Solid-state hard disk controller include flash interface controller (or for Media Interface Connector controller, flash memory channel control
Device), flash interface controller is coupled to NVM chips, and is sent out in a manner of following the interface protocol of NVM chips to NVM chips
Order to operate NVM chips, and receives the command execution results exported from NVM chips.Known NVM chip interfaces protocol package
Include " Toggle ", " ONFI " etc..
In the Chinese patent application of Publication No. CN1414468A, provide and handled by performing microinstruction sequence
The scheme of CPU (Central Processing Unit, central processing unit) instructions.When CPU will handle specific instruction, turn
It changes logic circuit and specific instruction is converted into corresponding microinstruction sequence, specific finger is realized by performing microinstruction sequence
The function of order.The template of microinstruction sequence or microinstruction sequence is stored in ROM (Read Only Memory, read-only memory)
In.During specific instruction is converted into microinstruction sequence, microinstruction sequence template can be filled, be allowed to and specific finger
It enables corresponding.
It is provided in Chinese patent application CN201610009789.6 and CN201510253428.1 for flash interface
The microcommand of controller performs method and apparatus, and Chinese patent application CN 201610861793.5 provides microinstruction sequence
Dispatching method and device, its full text is incorporated herein.Flash interface controller is usually coupled to multiple NVM chips, NVM chips
Including multiple LUN (Logic UNit, logic unit) or tube core, multiple LUN and tube core can respond and access parallel NVM lives
It enables, and due to that can have multiple pending NVM commands on each LUN or tube core, NVM controller is needed to multiple NVM
Order or multistage microinstruction sequence are scheduled, and multiple in processes or pending NVM command or multistage is safeguarded to safeguard
For generating the microinstruction sequence of NVM command.
In large capacity solid state disk, controller needs to connect more NVM chips.And also may be used in single NVM chips
Include multiple tube cores or target.Enabled since each tube core on NVM chips or target have chip (Chip Enable,
CE) pin, and when operating each tube core or target, to apply individual CE signals to it, with its in same solid state disk
The operation of its NVM chip/dies/target is mutually distinguished.However numerous CE signals need to consume a large amount of I/O pin of controller
Resource.
The schematic diagram for the storage system with the extension of chip enable signal that Fig. 1 is Chinese patent CN201632269U.Fig. 1
The storage system shown includes Memory Controller 101 (also referred to as solid-state hard disk controller) and flash memory channel 1 (102) to flash memory
Channel m (103) includes one or more pieces flash chip (not shown) on each flash memory channel.In the storage system of Fig. 1, also
Including CE expanders 104.CE expanders 104 are connected to Memory Controller 101.CE expanders 104 and Memory Controller 101
Connection, can be for example, by CE data signal lines and CE control signal wires.IIC (Inter-Integrated can also be passed through
Circuit, IC bus), UART (Universal Asynchronous Receiver/Transmitter, it is general different
Step transmitting-receiving transmission), (communication protocols such as (Local Interconnect Network, Local Interconnect Network) are in CE expanders by LIN
Data are transmitted between 104 and Memory Controller 101.In the embodiment in figure 1,102 and 103 shared data signal of flash memory channel
Line and the control signal wire in addition to chip enables.It it should be appreciated that can between Memory Controller 101 and CE expanders 104
It is coupled using single signal line.
CE expanders 104 enable (CE) signal wire by a plurality of chip, with flash memory channel 1 (102) to flash memory channel m
(103) chip of multiple flash chips or flash memory die on enables (CE) port and is connected, these chips enable (CE) signal
Line uses " flash memory channel 1-CE1 ", " flash memory channel 1-CEn ", " flash memory channel m-CE1 " and " flash memory channel m-CEn " in Fig. 1
It points out.
In the embodiment in figure 1, there is m flash memory channel in storage system, there is 1 flash chip on each flash memory channel,
Each flash chip includes n tube core and enables (CE) port with the corresponding n chip of the n tube core, thus needs in total
Use n*m CE signal wire.These n*m CE signal port is all connected to CE expanders 104, and CE expanders 104 with
It is communicated between Memory Controller 201 by less signal wire (for example, the CE data signal lines and CE in Fig. 1 control
Signal wire).For example, Memory Controller 101 indicates to enable first flash memory on flash memory channel 103 to CE expanders 104
The first die of chip, then the generation on corresponding " flash memory channel m-CE1 " chip enable signal line of CE expanders 104 is effective
Enable signal, and effective enable signal is not generated on other chip enable signal lines.
Still it should be understood that multiple CE expanders can be provided, for Memory Controller to be made to be able to access that more sudden strains of a muscle
Deposit chip.And the technology that Chinese patent CN201632269U is provided can be applied to access other NVM chips.
Invention content
The purpose of the application includes providing I/O command processing method and large capacity NVM interface controller, for supporting to CE
The application of expander and extension mechanism, to access more NVM chips.
According to the first aspect of the invention, the first I/O command processing method according to a first aspect of the present invention is provided, it should
Method includes：I/O command is obtained from command queue；Virtual LUN numbers and/or virtual block address are obtained from I/O command；According to empty
Intend LUN number selection processing units；The processing unit according to virtual block address determine physics LUN that I/O command accessed and
Physical block address on physics LUN；The CE ports of physics LUN accessed to offer I/O command send out effective chip and enable
Signal；And send out NVM interface order to the physics LUN accessed.
The first I/O command processing method according to the first aspect of the invention provides according to a first aspect of the present invention
Two I/O command processing methods address the block of virtual LUN according to the virtual block address, and the quantity of the block of virtual LUN is equal to described
The sum of the quantity of the block of multiple physics LUN included by virtual LUN.
The second I/O command processing method according to the first aspect of the invention provides according to a first aspect of the present invention
Three I/O command processing methods, wherein, the virtual LUN includes multiple physics LUN.
First according to the first aspect of the invention is provided to third I/O command processing method according to first party of the present invention
The 4th I/O command processing method in face provides processing unit for each virtual LUN, with when handling I/O command according to virtual LUN
Number selects corresponding processing unit.
The 4th I/O command processing method according to the first aspect of the invention provides according to a first aspect of the present invention
Five I/O command processing methods, wherein, the processing unit is coupled to multiple physics LUN.
The 5th I/O command processing method according to the first aspect of the invention provides according to a first aspect of the present invention
Six I/O command processing methods, wherein, the processing unit is coupled to the multiple physics LUN by CE expanders；It is and described
The CE ports for the physics LUN that CE expanders are accessed under the control of the processing unit to I/O command, which send out effective chip, to be made
It can signal.
The the 5th or the 6th I/O command processing method according to the first aspect of the invention, provides according to first party of the present invention
The 7th I/O command processing method in face, the object that the CE expanders are also accessed under the control of the processing unit to I/O command
It manages in the virtual LUN belonging to LUN, the CE ports hair corresponding to other each physics LUN in addition to this is accessed physics LUN
Go out invalid chip enable signal.
The the 4th to the 7th I/O command processing method according to the first aspect of the invention, provides according to first party of the present invention
The 8th I/O command processing method in face, processing unit perform its function by performing microinstruction sequence.
The 8th I/O command processing method according to the first aspect of the invention provides according to a first aspect of the present invention
Nine I/O command processing methods, microinstruction sequence have multiple execution contexts, using the multiple when microinstruction sequence performs every time
Perform one of context.
First according to the first aspect of the invention is provided to the 9th I/O command processing method according to first party of the present invention
The tenth I/O command processing method in face, further includes：Obtain the type of I/O command.
The tenth I/O command processing method according to the first aspect of the invention provides according to a first aspect of the present invention
11 I/O command processing methods if I/O command is reset command, obtain all physics LUN corresponding to virtual LUN, and to offer
The CE ports of all these physics LUN send out effective chip enable signal；And send out reset to all these physics LUN
Order；And processing reset command, until confirming that reset command is performed both by completing on all physics LUN.
The tenth I/O command processing method according to the first aspect of the invention provides according to a first aspect of the present invention
12 I/O command processing methods if I/O command is reset command, obtain all physics LUN corresponding to virtual LUN, every time to this
One in a little physics LUN sends out reset command and repeats to send out reset command to each physics LUN, and to providing these
The corresponding CE ports of physics LUN send out chip enable signal；And processing reset command, until having resetted in virtual LUN
All physics LUN.
The tenth I/O command processing method according to the first aspect of the invention provides according to a first aspect of the present invention
If I/O command is program command, the physics to be accessed is determined according to the virtual block address accessed for 13 I/O command processing methods
Physical block address on LUN and physics LUN, and send out chip enable signal to the CE ports for providing physics LUN；With
And send out program command to physics LUN；And processing program command, and the execution state of program command is obtained, until programming
Order performs completion.
First according to the first aspect of the invention is provided to the 13rd I/O command processing method according to the present invention first
14th I/O command processing method of aspect, further includes：In the state that pending order centralized recording order performs.
14th I/O command processing method according to the present invention provides the 15th IO lives according to a first aspect of the present invention
Processing method is enabled, is further included：One of pending order is selected from pending command set, obtains the selected state ordered, and
State according to selected order continues the processing to selected order, wherein each perform to order can perform order
A stage.
The the 14th or the 15th I/O command processing method according to the first aspect of the invention is provided according to the present invention the
16th I/O command processing method of one side, in response to receiving program command, the processing programming life on corresponding physics LUN
It enables；And the processing of pause program command, and in the instruction command process progress of the pending order centralized recording program command
State；And the processing in response to recovering programming order, processing progress of the inquiry program command on corresponding physics LUN；
If the processing of program command is not yet completed, continue the processing of program command；And again pause for the processing of the program command.
The the 14th to the 16th I/O command processing method according to the first aspect of the invention is provided according to the present invention the
17th I/O command processing method of one side, if there is at least two program commands for accessing same virtual LUN in command queue,
Handle the first program command；And the processing of the first program command of pause, and program and order in pending order centralized recording first
The state of the instruction command process progress of order；If there is other the second program commands for not yet starting to perform on virtual LUN, processing the
Two program commands.
The 17th I/O command processing method according to the first aspect of the invention, provides according to a first aspect of the present invention
18th I/O command processing method, if not yet start to perform without other on virtual LUN second orders, from pending command set
The first program command of middle selection and the state for obtaining the first program command；If the execution state instruction of the first program command is
It does not complete, handles the first program command；And continuously the first program command is obtained to the physics LUN that the first program command is accessed
Execution state, until the first program command execution state instruction for processing complete.
The 8th I/O command processing method according to the first aspect of the invention provides according to a first aspect of the present invention
19 I/O command processing methods if the execution state instruction of the first program command is completed for processing, are relayed from pending command set
Continuous selection third program command.
According to the second aspect of the invention, the first I/O command processing method according to a second aspect of the present invention is provided, is wrapped
It includes：I/O command is obtained from command queue；Logic LUN numbers and/or logical block address are obtained from I/O command；According to logic LUN
Number and/or logical block address obtain the number of virtual LUN corresponding with logic LUN；Number selection according to virtual LUN is handled
The physics LUN that unit and I/O command are accessed；The CE ports of physics LUN accessed to offer I/O command are sent out effectively
Chip enable signal；And send out NVM interface order to the physics LUN accessed.
The first I/O command processing method according to the second aspect of the invention provides according to a second aspect of the present invention
Two I/O command processing methods, wherein, virtual LUN includes multiple physics LUN；And it is coupled to one or more of different virtual LUN
A physics LUN is coupled to multiple physical blocks that one or more physics LUN of different virtual LUN are provided and is organized as patrolling
Collect LUN.
The second I/O command processing method according to the second aspect of the invention provides according to a second aspect of the present invention
Three I/O command processing methods, wherein, by logic LUN mapping to multiple virtual LUN.
The second I/O command processing method according to the second aspect of the invention provides according to a second aspect of the present invention
Four I/O command processing methods, wherein, logic LUN is corresponded with physics LUN.
The second I/O command processing method according to the second aspect of the invention provides according to a second aspect of the present invention
Five I/O command processing methods, wherein, by multiple logical block maps with continuous logic block address in same logic LUN to not
Same virtual LUN.
The second I/O command processing method according to the second aspect of the invention provides according to a second aspect of the present invention
Six I/O command processing methods, wherein, by multiple logical block maps with identity logic block address in Different Logic LUN to not
Same virtual LUN.
First according to the second aspect of the invention is provided to the 6th I/O command processing method according to second party of the present invention
The 7th I/O command processing method in face, wherein, processing unit is provided for each virtual LUN, with the foundation void when handling I/O command
Intend LUN numbers and select corresponding processing unit.
According to the third aspect of the invention we, the first NVM interface controller according to a third aspect of the present invention is provided, it should
NVM interface controller includes command queue and NVM command processing unit, and NVM command processing unit is coupled to multiple NVM chips,
For receiving I/O command, NVM command processing unit is used to obtain I/O command from command queue, and according to I/O command for command queue
It indicates to send NVM interface order to NVM chips or receives data or state from NVM chips, NVM command processing unit includes multiple
Processing unit, for accessing corresponding NVM chips, NVM command processing unit is coupled to NVM by one or more CE expanders
The CE ports of chip, NVM command processing unit are additionally operable to, and are made by the way that CE expanders is set to send out chip to specified NVM chips
Energy signal, to access corresponding NVM chips.
The first NVM interface controller according to the third aspect of the invention we provides according to a third aspect of the present invention
Two NVM interface controllers, wherein, the chip that CE expanders are coupled to multiple NVM chips enables (CE) port, NVM command processing
Unit is enabled with a transmission chip into multiple NVM chips by setting CE expanders or chip disables signal.
The first NVM interface controller according to the third aspect of the invention we provides according to a third aspect of the present invention
Three NVM interface controllers, wherein, multiple processing units are coupled to the CE ports of multiple NVM chips by multiple CE expanders, more
A processing unit is by setting corresponding CE expanders, to be disabled to specified NVM chip transmission chip enable signals or chip
Signal.
First according to the third aspect of the invention we is provided to third NVM interface controller according to third party of the present invention
The 4th NVM interface controller in face, wherein, the I/O command obtained from command queue indicates virtual LUN numbers, virtual LUN numbers
Virtual LUN is used to indicate, the virtual LUN includes multiple physics LUN.
First to fourth NVM interface controller according to the third aspect of the invention we, provides according to third party of the present invention
The 5th NVM interface controller in face, wherein, the NVM processing units are coupled to multiple physics LUN, and NVM interface controller is also used
In one of multiple processing units being selected to handle I/O command according to virtual LUN numbers.
First according to the third aspect of the invention we is provided to the 5th NVM interface controller according to third party of the present invention
The 6th NVM interface controller in face, wherein, each NVM chips include multiple physics LUN, and processing unit passes through CE expander couplings
Close multiple physics LUN；And the physics LUN that the CE expanders are accessed under the control of the processing unit to I/O command
CE ports send out effective chip enable signal.
The 6th NVM interface controller according to the third aspect of the invention we provides according to a third aspect of the present invention
Seven NVM interface controllers, wherein, the CE expanders couple also under the control of the processing unit to the CE expanders
Multiple physics LUN in, the CE ports corresponding to other physics LUN in addition to I/O command accesses physics LUN are sent out in vain
Chip enable signal.
First according to the third aspect of the invention we is provided to the 7th NVM interface controller according to third party of the present invention
The 8th NVM interface controller in face, wherein, processing unit performs its function by performing microinstruction sequence.
The 8th NVM interface controller according to the third aspect of the invention we provides according to a third aspect of the present invention
Nine NVM interface controllers, wherein, microinstruction sequence has multiple execution contexts, using described when microinstruction sequence performs every time
One of multiple execution contexts.
First according to the third aspect of the invention we is provided to the 9th NVM interface controller according to third party of the present invention
The tenth NVM interface controller in face, NVM command processing unit are additionally operable to, and virtual LUN numbers and/or void are obtained from I/O command
Intend block address；And selection processing unit is numbered according to virtual LUN, the processing unit determines I/O command according to virtual block address
The physical block address on physics LUN and physics LUN accessed.
The tenth NVM interface controller according to the third aspect of the invention we provides according to a third aspect of the present invention
11 NVM interface controllers, NVM command processing unit access the block of virtual LUN by the virtual block address, virtual LUN's
The quantity of block is equal to the sum of the quantity of the block of multiple physics LUN included by the virtual LUN.
First according to the third aspect of the invention we is provided to the 11st NVM interface controller according to third of the present invention
12nd NVM interface controller of aspect, NVM command processing unit are additionally operable to obtain the type of I/O command.
The 12nd NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
13rd NVM interface controller, if I/O command is reset command, NVM command processing unit is additionally operable to, obtains and compiled by virtual LUN
All physics LUN indicated by number, and pass through and CE expanders is set to send out chip to the CE ports for providing these physics LUN and make
It can signal；And send out reset command to these physics LUN；And processing reset command, until confirming reset command all
It is performed both by completing on physics LUN.
The 12nd NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
14th NVM interface controller, if I/O command is reset command, NVM command processing unit is additionally operable to, obtains and compiled by virtual LUN
All physics LUN indicated by number, every time one into these physics LUN send out reset command and repeat to each object
Reason LUN sends out reset command, and sends out chip enable signal to the corresponding CE ports for providing these physics LUN；And processing
Reset command, until having resetted all physics LUN in virtual LUN.
The 12nd NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
15th NVM interface controller, if I/O command is program command, NVM command processing unit is additionally operable to, virtual according to being accessed
Block address determines the physical block address on the physics LUN to be accessed and physics LUN, and to the CE ends for providing physics LUN
Mouth sends out chip enable signal；And send out program command to physics LUN；And processing program command, and obtain programming life
The execution state of order, until program command performs completion.
First according to the third aspect of the invention we is provided to the 15th NVM interface controller according to third of the present invention
16th NVM interface controller of aspect, NVM interface controller also store pending command set, for recording order execution
State.
The 16th NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
17th NVM interface controller, NVM command processing unit are additionally operable to, and one of pending order is selected from pending command set,
And the selected state ordered is obtained, and ordered selected by execution, wherein each perform to order can perform order
A stage.
The the 16th or the 17th NVM interface controller according to the third aspect of the invention we is provided according to the present invention the
18th NVM interface controller of three aspects, NVM command processing unit is additionally operable to, in response to receiving program command, in correspondence
Physics LUN on handle program command；And the execution of pause program command, and ordered in pending order centralized recording programming
The state of the instruction command process progress of order；And the execution in response to recovering programming order, inquiry program command is corresponding
Processing progress on physics LUN；If the processing of program command is not yet completed, continue the processing of program command；And it again pauses for
The processing of the program command.
The 16th to 18 NVM interface controllers according to the third aspect of the invention we, provide according to third of the present invention
19th NVM interface controller of aspect, if having at least two program commands for accessing the first virtual LUN, NVM in command queue
Command process unit is additionally operable to, and handles the first program command；And the processing of the first program command of pause, and in pending order
The state of the instruction command process progress of the first program command of centralized recording；If there are other not yet to start to hold on the first virtual LUN
The second capable program command handles the second program command.
The 19th NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
20th NVM interface controller, if not yet start to perform without other on the first virtual LUN second orders, NVM command processing
Unit is additionally operable to, and the first program command is selected from pending command set and obtains the state of the first program command；If first
The execution state instruction of program command is unfinished, handles the first program command；And accessed from the first program command
One physics LUN inquires the execution state of the first program command, until the execution state instruction of the first program command is completed for processing.
The 19th NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
21st NVM interface controller, if the execution state instruction of the first program command is completed for processing, NVM command processing unit
It is additionally operable to, third program command is selected from pending command set.
First to fourth NVM interface controller according to the third aspect of the invention we, provides according to third party of the present invention
The 22nd NVM interface controller in face, wherein the I/O command instruction logic LUN numbers that obtain from command queue and wherein
It will be coupled into one or more physics LUN of different virtual LUN or be coupled to one or more physics of different virtual LUN
Multiple physical blocks that LUN is provided are organized as logic LUN.
The 22nd NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
The 23rd NVM interface controller, wherein, NVM Media Interface Connectors controller is by logic LUN mapping to multiple virtual LUN.
The 22nd NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
The 24th NVM interface controller, wherein, logic LUN with physics LUN correspond.
The 22nd NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
The 25th NVM interface controller, wherein, NVM Media Interface Connectors controller will in same logic LUN have continuous logical blocks
Multiple logical block maps of address are to different virtual LUN.
The 22nd NVM interface controller according to the third aspect of the invention we, provides according to a third aspect of the present invention
The 26th NVM interface controller, wherein, NVM Media Interface Connectors controller will in Different Logic LUN have same logical block
Multiple logical block maps of address are to different virtual LUN.
The 12nd to 26 NVM interface controllers according to the third aspect of the invention we, provide according to the present invention
27th NVM interface controller of the third aspect, NVM command processing unit are additionally operable to, and logic LUN is obtained from I/O command and is compiled
Number and/or logical block address；Obtain virtual LUN's corresponding with logic LUN according to logic LUN numbers and/or logical block address
Number；Number according to virtual LUN selects processing unit；Selected processing unit is used to order to IO is provided by CE expanders
The CE ports of accessed physics LUN is enabled to send out effective chip enable signal；And send out NVM to the physics LUN accessed
Interface command.
According to the fourth aspect of the invention, a kind of solid storage device according to a fourth aspect of the present invention is provided, this is solid
State storage device includes control unit and multiple NVM chips, and for control unit for accessing multiple NVM chips, NVM chips include one
A or multiple physics LUN, the control unit include the NVM interface control as described in the first to 17 of third aspect present invention
Device and one or more CE expanders, wherein NVM interface controller pass through one or more CE expanders and multiple NVM cores
Piece couples, for sending out chip enable signal to the CE ports for the NVM chips for providing accessed physics LUN.
According to the fifth aspect of the invention, a kind of journey including instruction code according to a fifth aspect of the present invention is provided
Sequence, when being loaded into solid storage device and when being performed on the controller of solid storage device, described program makes the controller
It performs such as first aspect present invention first to the 19th and at second aspect of the present invention first to the I/O command as described in the 7th
Reason method.
According to the sixth aspect of the invention, a kind of solid storage device according to a sixth aspect of the present invention is provided, this is solid
State storage device includes one or more processors and memory, and one or more of processors pass through in run memory
Program is performed such as first aspect present invention first to the 19th and the IO as described in second aspect of the present invention first to the 7th
Command handling method.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, embodiment will be described below
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description be only the present invention some
Embodiment, for those of ordinary skill in the art, without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the schematic diagram of the storage system of the prior art with the extension of chip enable signal；
Fig. 2 is the block diagram according to the NVM interface controller of the solid-state hard disk controller of the embodiment of the present invention；
Fig. 3 is the block diagram according to the NVM interface controller of the solid-state hard disk controller of further embodiment of this invention；
Fig. 4 is the schematic diagram according to the virtual LUN of the embodiment of the present invention；
Fig. 5 is the block diagram according to the NVM interface controller of the solid-state hard disk controller of another embodiment of the present invention；
Fig. 6 is the flow chart according to the NVM command processing unit processes order of the embodiment of the present invention；
Fig. 7 is the flow chart according to the NVM command processing unit processes order of further embodiment of this invention；
Fig. 8 is the flow chart according to the thread process order of the NVM command processing unit of further embodiment of this invention；
Fig. 9 is the block diagram according to the NVM interface controller of the solid-state hard disk controller of still another embodiment of the present invention；
Figure 10 is the logic LUN (and block) according to the embodiment of the present invention to the mapping table of virtual LUN and physics LUN
Schematic diagram.
Figure 11 is the block diagram according to the NVM interface controller of the solid-state hard disk controller of the still another embodiment of the present invention；
And
Mappings of the Figure 12 for the logic LUN (and block) according to another embodiment of the present invention to virtual LUN and physics LUN
The schematic diagram of table.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is part of the embodiment of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, the every other implementation that those of ordinary skill in the art are obtained without making creative work
Example, shall fall within the protection scope of the present invention.
Embodiment one
Fig. 2 is the block diagram of the NVM interface controller of solid-state hard disk controller according to embodiments of the present invention.NVM in Fig. 2
Interface controller includes command queue 201 and NVM command processing unit 202.According to an embodiment of the invention, command queue 201
For receiving the order from user or upper-level system.Order from user or upper-level system may include reading, be written, delete
It removes, labeled as the orders such as invalid, can also include reading NVM chip status, reading or setting NVM chip features (Feature)
Deng order and user defined command can also be included.NVM command processing unit 202 is used to obtain from command queue 201 and order
It enables, and the NVM interface order of NVM chip interface standards is met or according to NVM chips to the transmission of NVM chips according to the instruction of order
Interface standard receives data or state from NVM.NVM command processing unit 202 is coupled to multiple NVM chips.In the embodiment of Fig. 2
In, NVM command processing unit 202 is coupled to 4 NVM chips by 2 channels, and each NVM chips include 2 LUN.In channel
1 NVM chips provide LUN0-LUN3, and LUN4-LUN7 is provided in the NVM chips of channel 2.It should be understood that NVM interface control
Device processed can couple more channels, and access more NVM chips and more LUN.
According to an embodiment of the invention, multiple processing units, the multiple place are provided in NVM command processing unit 202
Reason unit accesses corresponding NVM chips by performing microinstruction sequence.Wherein, the microinstruction sequence that can be performed is referred to as line
Journey.Since same microinstruction sequence possesses the execution state of oneself in each perform, so as to be based on same microinstruction sequence
Create multiple threads.In NVM command processing unit 202 also execution state is stored for per thread.In reality according to the present invention
It applies in example, is created or using thread based on the LUN to be accessed.Such as access LUN1 and/or using line using thread 1
Journey 2 accesses LUN2.
Embodiment two
Fig. 3 is the block diagram according to the NVM interface controller of the solid-state hard disk controller of further embodiment of this invention.In Fig. 3
NVM interface controller include command queue 201 and NVM command processing unit 202.NVM processing units 202 include multiple processing
Unit (not shown), multiple processing units access corresponding NVM chips by performing microinstruction sequence.Wherein, it can be performed
Microinstruction sequence be referred to as thread.Multiple execution threads that are scheduled in NVM interface controller are also shown in Fig. 3.
Thread be scheduled execution when, NVM processing units 202 are by setting CE expanders, to access multiple NVM chips.
In one example, referring to Fig. 3, NVM interface controller is coupled to multiple NVM chips by a CE expander
CE ports and by performing microcommand, to set any one (or the mesh therein of CE expanders into multiple NVM chips
Mark one of (Target)) generate chip enable signal or chip disabling signal, other similar ports of these multiple NVM chips
(for example, DQ, DQS, ALE, CLE etc.) shares signal wire.For example, by performing Set_CE microcommands, institute is informed to CE expanders
Access NVM chips.For example, to access LUN3, thread 1 performs Set_CE microcommands so that CE expanders are to 1 chips of NVM
CE ports send effective chip enable signal, and invalid chip signal is generated to the CE ports of NVM 0, NVM2 and NVM3,
So as to which the order of access NVM chips for sending out thread 1 comes into force to NVM1 chips.By this method, thread can access multiple NVM cores
Piece, multiple LUN or multiple targets.
As another example, NVM interface controller is coupled to multiple NVM chips by multiple CE expanders, by holding
Row microcommand, setting each CE expanders to specified NVM chips (alternatively, LUN or target) transmission chip enable signal or
Chip disables signal.
Embodiment three
Fig. 4 is the schematic diagram of virtual LUN according to embodiments of the present invention.As an example, thread 2 is coupled by CE expanders
To 2 NVM chips, each NVM chips include two LUN (for purposes of clarity, being referred to as " physics LUN "), so as to line
Journey 2 may have access to 4 physics LUN.Referring to Fig. 4, each physics LUN includes 1024 for storing the physical block of data, provides void
Intend LUN to represent the 4 physics LUN that can be accessed by thread 2 by CE expanders, so as to which virtual LUN is included by 4 physics LUN
4096 physical blocks provided.In an embodiment according to the present invention, it is visited in the block address ranging from address space of 0-4095
Ask virtual LUN, and thread 2 obtains the physics LUN for providing the block (for example, object according to the block address (for example, 4000) of virtual LUN
Manage LUN3), and indicate that CE expanders send enabled letter to the CE ports of 3 place NVM chips (for example, NVM chips 1) of physics LUN
Number, and send disabling signal to other CE ports.
Example IV
Fig. 5 is the block diagram of the NVM interface controller of solid-state hard disk controller according to another embodiment of the present invention.According to this
The embodiment of invention, NVM interface controller receive the order from user or upper-level system (for example, User_ by command queue
CMD_Post (LUN, block)), the LUN to be accessed and block (block) are indicated in order.Indicated LUN is empty in order
Intend LUN, and block is the block provided by virtual LUN.For example, the block 2047 of the virtual LUN 3 of command access.
According to an embodiment of the invention, in response to receiving I/O command, the virtual LUN, NVM to be accessed are indicated in order
Command process unit provides thread and when handling order for each virtual LUN, and NVM command processing unit is according to virtual LUN
Number select corresponding thread.For example, the order for accessing virtual LUN3 is handled by thread 3.Thread 3 is accessed according to order
Block (address 2047), the determining address by physics LUN3-2 (referring to Fig. 5) provide the block accessed by 1023 physical block,
It is provided by setting (for example, performing Set_CE microcommands) CE expanders to the NVM chips or target that provide physics LUN3-2
Effective chip enable signal, and send out NVM interface order to physics LUN 3-2.
As described above, according to an embodiment of the invention, by the way that multiple physics LUN are organized as virtual LUN so that be not required to
In the case of increase number of threads (access of per thread management virtual LUN to one), NVM interface controller can access more
Physics LUN, so as to fulfill the solid state disk of more capacity.And in the upper-level system of NVM interface controller, NVM connects
The access mode of mouth controller does not change, and only the quantity of the block included by virtual LUN increases, so as to the series of strata on not changing
In the case of system or change very little, the access ability to more NVM chips is obtained.
Embodiment five
Fig. 6 is the flow chart of NVM command processing unit processes order according to embodiments of the present invention, for Processing Example
I/O command in four.According to an embodiment of the invention, the command process unit of NVM interface controller obtains IO from command queue
Order, the virtual LUN numbers and/or the information of block address command type is indicated in order, to be accessed.Command type includes compiling
Journey, erasing, reading, reset etc..
In one example, command process unit obtains I/O command from command queue, and order indicates the class of I/O command
Type is reset command, and the virtual LUN to be accessed numbers (such as LUN3) are further indicated in order.Optionally, in reset command not
Including block address information (601).Next, NVM command processing unit judges the type (602) of I/O command and judges that IO is ordered
It enables as reset command (613), in response to receiving reset command, NVM command processing unit is numbered selection according to virtual LUN and corresponded to
Thread 4 (614).Thread 4 is designated to the order that processing accesses virtual LUN3.
Next, NVM command processing unit obtains the indicated all physics LUN (615) of virtual LUN numbers, and pass through
Setting (for example, performing Set_CE microcommands) CE expanders carry out the CE to the NVM chips or target for providing all these physics LUN
Pin sends out enable signal and sends out reset command (616) to all these physics LUN.And on these physics LUN
Reset command is managed, and confirms that reset command performs completion (617).
Optionally, one every time into these physics LUN of NVM command processing unit sends out reset command and repeats
Reset command is sent out to each physics LUN, and passes through setting (for example, performing Set_CE microcommands) CE expanders and these is being provided
Enable signal is sent on the corresponding CE pins of physics LUN.And reset command is handled on each physics LUN, until resetting
All physics LUN in virtual LUN.
In another example, command process unit obtains I/O command from command queue, and I/O command is indicated in order
Type for program command, the virtual LUN to be accessed numbers (such as LUN3) and block are further indicated in order, wherein block is by void
Intend the block (601) that LUN is provided.Next, NVM command processing unit judges the type (602) of I/O command and judges I/O command
For reset command (623), in response to receiving program command, NVM command processing unit is corresponding according to virtual LUN number selections
Thread 4 (624).Thread 4 is according to ordering on the physics LUN and physics LUN that accessed block determines that program command accessed
Physical block address and the NVM chips of physics LUN or the corresponding CE ports of tube core (625) are provided.
Next, thread 4 is by setting (for example, performing Set_CE microcommands) CE expanders to offer physics LUN's
The CE pins of NVM chips or tube core send enable signal (626) and send out program command to physics LUN.In response to receiving
To program command, NVM command processing unit handles program command on corresponding physics LUN and obtains holding for program command
Row state, until program command performs completion (627).
Embodiment six
Fig. 7 is the flow chart according to the NVM command processing unit processes order of further embodiment of this invention.For handling IO
Order.Since virtual LUN includes multiple physics LUN, and multiple physics LUN can be empty to accessing so as to need by concurrent access
The order for intending different physics LUN on LUN provides parallel processing capability.Pending command history is provided, need not temporarily be accounted for record
With the state of the instruction processing progress of the I/O command of flash memory channel.
According to embodiments of the present invention, the command process unit of NVM interface controller obtains IO lives from command queue
It enables (701), the command type of I/O command is indicated in I/O command, virtual LUN is numbered and/or the information of block address.At NVM command
Reason unit also has recorded the state (702) of the instruction command process progress of order in pending command history and from treating
One of pending order (703) are selected in reason command history, obtain the selected state ordered, and perform selected order.
Wherein, can be an exectorial stage (704) to each perform of order.
For example, command process unit obtains I/O command from command queue, the type of I/O command is indicated in order to compile
Journey order further indicates the virtual LUN to be accessed numbers (such as LUN3) and block in order, wherein block is provided by virtual LUN
Block.In response to receiving program command, NVM command processing unit selects corresponding thread 5 according to virtual LUN numbers.Thread 5
According to the physical block address ordered on the physics LUN and physics LUN that accessed block determines that program command accessed, with
And provide the NVM chips or tube core of physics LUN.Next, thread 5 passes through setting (for example, performing Set_CE microcommands) CE
Expander sends enable signal to the NVM chips or the CE pins of tube core for providing physics LUN and is sent out to physics LUN
Program command.
In the first stage for performing the program command, NVM command processing unit is to the corresponding physics LUN of the program command
The data for sending the address of program command and/or being written then record the shape of the program command in pending command history
State (for example, storage location of processing progress, the address accessed and/or data to be written).And when performing the program command,
The program command is obtained from pending command history, using pending command history provide the program command state, really
Surely the second stage of the order is performed, then inquires whether physics LUN completes the processing of the program command.
It is performing between the first stage of the program command and second stage, NVM command processing unit can be from command queue
It obtains one or more I/O commands to be handled, can also be obtained from pending command history from one or more I/O commands carry out
Reason.So as to which multiple I/O commands are supplied to virtual LUN.
Preferably, each physics LUN only handles an I/O command in synchronization.NVM command processing unit also records
It is no to have issued I/O command to a physics LUN, and select to access the I/O command of the physics LUN of I/O command for being not present and handling
To handle.
Embodiment seven
Fig. 8 is according to the flow chart of the thread process order of the NVM command processing unit of further embodiment of this invention, is used for
The two or more pieces programming life of the same virtual LUN of access occurred in I/O command and processing command queue in processing queue
It enables.
In one example, the command process unit of NVM interface controller obtains I/O command (801) from command queue,
I/O command is indicated in order as program command, further indicates virtual LUN numbers and the block to be accessed in order, wherein block be by
The block that virtual LUN is provided.In response to receiving program command, NVM command processing unit is corresponding according to virtual LUN number selections
Thread 6.Thread 6 is according to the object ordered on the physics LUN and physics LUN that accessed block determines that program command accessed
Manage block address.Next, thread 6 is by setting (for example, perform Set_CE microcommands) CE expanders, to the physics to be accessed
The CE pins of NVM chips or target where LUN send out enable signal, and to the physics LUN to be accessed send out program command and/
Or data.And program command (802) is handled on corresponding physics LUN.
Next, the pause of NVM command processing unit to the processing of the current command (for example, being sent out to accessed physics LUN
Program pause command), and record in pending command history the state of the instruction command process progress in relation to the current command
(803).And judge the order (804) for whether there are other not yet to start to perform on current virtual LUN.If on current virtual LUN
The I/O command for having other not yet to start to perform, repeats the above process, to obtain I/O command, on corresponding physics LUN
I/O command and optionally is managed, suspends processed I/O command.
If there is no other on current virtual LUN not yet to start the I/O command performed, NVM command processing unit selects to wait to locate
Manage one of the program command (805) in command history, and obtain the program command state (for example, extraction instruction command type,
The information of virtual LUN numbers and/or block address), the virtual LUN numbers then accessed according to the program command select corresponding
Thread 7.Thread 7 is according to the object ordered on the physics LUN and physics LUN that accessed block determines that program command accessed
Manage block address (806).Next, thread 7 is by setting (for example, perform Set_CE microcommands) CE expanders, and to accessing
Physics LUN where NVM chips or the CE pins of target send out enable signal, and inquiry is sent out to the physics LUN to be accessed
Status command, and judge whether current program command handles completion (807).If inquire the corresponding order (example of status command instruction
Such as, program command) completion is performed, continue to select other orders in pending command history, until in pending command history
Order all have been processed into (808).If the corresponding order (for example, program command) of inquiry status command instruction is not yet completed,
Then the status information according to corresponding order sends out inquiry status command to the physics LUN to be accessed again.
Embodiment eight
Fig. 9 is the block diagram according to the NVM interface controller of the solid-state hard disk controller of still another embodiment of the present invention.Root
According to the embodiment of the present invention, NVM interface controller receives the order from user or upper-level system by command queue, in order
Indicate the LUN and block to be accessed.Indicated LUN is logic LUN in order, and block is the block provided by logic LUN.Example
Such as, the block 2047 of command access logic LUN 3.
In the embodiment in fig. 9, logic LUN is formed by the physics LUN for being coupled to different CE expanders, so as to be conducive to
The multiple orders for accessing identity logic LUN are performed simultaneously on multiple physics LUN.
In the embodiment in fig. 9, logic LUN is made of 4 physics LUN.Each physics LUN provides 1024 blocks, so as to
The block 2047 of logic LUN3 can be provided by the 2nd physics LUN (being denoted as logic LUN 3-1) for forming logic LUN3.Referring also to figure
10, logic LUN 0 (are denoted as virtual LUN0, virtual LUN1, virtual LUN2 and void respectively including being respectively coupled to 4 CE expanders
Intend LUN3) physics LUN (being denoted as physics LUN 0-0, physics LUN 1-0, physics LUN 2-0 and physics LUN 3-0 respectively),
And logic LUN 3 include being respectively coupled to 4 CE expanders (be denoted as respectively virtual LUN0, virtual LUN1, virtual LUN2 with it is virtual
LUN3 physics LUN (being denoted as physics LUN 0-3, physics LUN 1-3, physics LUN 2-3 and physics LUN 3-3 respectively)).Root
According to the embodiment of the present invention, by NVM command processing unit safeguard such as Figure 10 logic LUN (and block) to virtual LUN and
The mapping relations of physics LUN.It is ordered in response to being obtained from command queue, command process unit is according to the logic indicated in order
LUN is numbered and block address, and the virtual LUN of institute's access block is provided (or for accessing by mapping table such as shown in Fig. 10
The thread of the virtual LUN) and physics LUN, and indicate to be associated with the thread process of the virtual LUN order.
As an example, in response to the I/O command received, the block address 2047 for the logic LUN3 to be accessed is indicated in order,
NVM command processing unit determines to provide accessed block by the physics LUN3 associated by thread 8 (referring to Fig. 9, virtual LUN1)；And
If the I/O command instruction received accesses the block 1023 of logic LUN3, NVM command processing unit determine by thread 9 (referring to Fig. 9,
Virtual LUN0) associated by physics LUN3 accessed block is provided.According to an embodiment of the invention, thread 8 and thread 9 are right simultaneously
Order is handled.Thread 8, according to the physics LUN accessed, passes through setting (for example, performing Set_CE microcommands) with thread 9
CE expanders to provide effective CE enable signals to the NVM chips or target that provide physics LUN, and to corresponding physics LUN
Send out NVM interface order.Since thread 8 accesses the CE expanders of corresponding virtual LUN1, and thread 9 accesses corresponding virtual LUN0's
CE expanders, thus there is no resources (for example, CE expanders, physics LUN etc.) with processing of the thread 9 to I/O command for thread 8
Conflict, can be carried out at the same time.
As still another example, NVM Media Interface Connectors controller in different ways maps logic LUN (and block)
To virtual LUN (and physics LUN) so that the access to the continuous blocks of logic LUN is mapped to different virtual LUN, so as to
Further promote the concurrency of command process.
As still another example, NVM Media Interface Connectors controller will access the command mapping of the continuous blocks in logic LUN
To the command mapping of different virtual LUN or the block with identical address that multiple logic LUN will be accessed to different virtual LUN.
As described above, by providing logic LUN, will be ordered with block address for No. LUN according to logic by NVM command processing unit
It is distributed to different threads.The processing order of multiple thread parallels, enhance NVM interface controller NVM chips are accessed it is parallel
Property.
Embodiment nine
Figure 11 is the block diagram according to the NVM interface controller of the solid-state hard disk controller of the still another embodiment of the present invention.
According to an embodiment of the invention, NVM interface controller receives the order from user or upper-level system, order by command queue
In indicate the LUN and block to be accessed.Indicated LUN is logic LUN in order.In the embodiment in figure 11, logic LUN with
Physics LUN is of the same size, and each logic LUN is provided by a physics LUN.
In the embodiment in figure 11, logic LUN is formed by the physics LUN for being coupled to different CE expanders, so as to advantageous
It is performed simultaneously on multiple physics LUN in the multiple orders for accessing identity logic LUN.Logic is arrived referring to Figure 12, logic LUN 0
LUN3 (is denoted as physics LUN 0-0, physics LUN respectively by each physics LUN0 offers of virtual LUN0 to virtual LUN3 respectively
1-0, physics LUN 2-0 and physics LUN 3-0, wherein preceding virtual No. LUN of a instructions in label " a-b ", and posterior b
Indicate the physics LUN numbers in virtual LUN), and logic LUN 4 to logic LUN7 is respectively by virtual LUN0 to the every of virtual LUN3
A physics LUN2 provides (being denoted as physics LUN 0-2, physics LUN 1-2, physics LUN 2-2 and physics LUN 3-2 respectively).
As an example, each NVM chips provide two physics LUN, and NVM interface controller arrives continuous multiple logic LUN mappings
Physics LUN from different NVM chips is advantageous, because this can be reduced when NVM chips break down, data can not be extensive
Multiple risk.And by continuous multiple logic LUN mappings to the NVM chip makes physical pages for being coupled to different CE expanders so that
Accessing the order of continuous multiple logic LUN can be handled simultaneously, without resource (CE expanders, physics LUN etc.)
Conflict.
According to an embodiment of the invention, by the logic LUN (and block) of NVM command processing unit maintenance such as Figure 12 to void
Intend the mapping relations of LUN and physics LUN.It is ordered in response to being obtained from command queue, command process unit is according to order middle finger
The logic LUN numbers shown are provided the virtual LUN of institute's access block (or for accessing by all mapping tables as shown in figure 12
The thread of the virtual LUN) and physics LUN, and indicate that the thread 10 for being associated with the virtual LUN accessed handles the order.Root
According to the embodiment of the present invention, thread 10 handles order, and thread 10 is according to the physics LUN accessed, by setting (example
Such as, Set_CE microcommands are performed) CE expanders enable letter to provide effective CE to the NVM chips or target that provide physics LUN
Number, and send out NVM interface order to physics LUN.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in change or replacement, should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. a kind of I/O command processing method, which is characterized in that including：
I/O command is obtained from command queue；
Logic LUN numbers and/or logical block address are obtained from I/O command；
The number of virtual LUN corresponding with logic LUN is obtained according to logic LUN numbers and/or logical block address；
Number according to virtual LUN selects the physics LUN that processing unit and I/O command are accessed；
The CE ports of physics LUN accessed to offer I/O command send out effective chip enable signal；And
NVM interface order is sent out to the physics LUN accessed.
2. I/O command processing method as described in claim 1, which is characterized in that wherein, virtual LUN includes multiple physics LUN；
And
It is coupled to one or more physics LUN of different virtual LUN or is coupled to one or more objects of different virtual LUN
Multiple physical blocks that reason LUN is provided are organized as logic LUN.
3. I/O command processing method as claimed in claim 2, which is characterized in that wherein, logic LUN is a pair of with physics LUN mono-
It should.
4. such as claim 1-3 any one of them I/O command processing methods, which is characterized in that wherein, carried for each virtual LUN
For processing unit, to select corresponding processing unit according to virtual LUN numbers when handling I/O command.
5. a kind of NVM interface controller, including command queue and NVM command processing unit, NVM command processing unit is coupled to more
A NVM chips, for receiving I/O command, NVM command processing unit is used to obtain I/O command, and root from command queue for command queue
NVM interface order being sent to NVM chips according to the instruction of I/O command or receiving data or state from NVM chips, NVM command processing is single
Member include multiple processing units, for accessing corresponding NVM chips, which is characterized in that NVM command processing unit by one or
Multiple CE expanders are coupled to the CE ports of NVM chips, and NVM command processing unit is additionally operable to, by setting CE expanders to finger
Fixed NVM chips send out chip enable signal, to access corresponding NVM chips.
6. NVM interface controller as claimed in claim 5, wherein, the I/O command obtained from command queue indicates that virtual LUN is compiled
Number, virtual LUN numbers are used to indicate virtual LUN, and the virtual LUN includes multiple physics LUN.
7. such as NVM interface controller described in claim 5 or 6, wherein, the NVM processing units are coupled to multiple physics
LUN, NVM interface controller are additionally operable to, and one of multiple processing units are selected to handle I/O command according to virtual LUN numbers.
8. such as claim 5-7 any one of them NVM interface controllers, which is characterized in that NVM command processing unit is also used
In obtaining virtual LUN number and/or virtual block address from I/O command；And selection processing unit is numbered according to virtual LUN,
The processing unit is with determining the physical block on physics LUN that I/O command accessed and physics LUN according to virtual block address
Location.
9. such as claim 5-8 any one of them NVM interface controllers, which is characterized in that NVM interface controller, which also stores, to be treated
Command set is handled, for recording the state that order performs.
10. NVM interface controller as claimed in claim 9, which is characterized in that NVM command processing unit is additionally operable to, from treating
One of pending order and the selected state ordered of acquisition are selected in reason command set, and performs selected order, wherein right
Each perform of order can be an exectorial stage.
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