CN108241483B - Leading zero detection structure and method - Google Patents
Leading zero detection structure and method Download PDFInfo
- Publication number
- CN108241483B CN108241483B CN201611208564.XA CN201611208564A CN108241483B CN 108241483 B CN108241483 B CN 108241483B CN 201611208564 A CN201611208564 A CN 201611208564A CN 108241483 B CN108241483 B CN 108241483B
- Authority
- CN
- China
- Prior art keywords
- current
- data stream
- bit
- binary data
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Dc Digital Transmission (AREA)
- Inverter Devices (AREA)
Abstract
The invention provides a leading zero detection structure and a method, wherein the structure comprises the following steps: the detection structure of leading zero formed by an extension fan-out unit, a current processing unit and a correction low-order data unit is provided, and the current processing unit is connected between the extension fan-out unit and the correction low-order data unit; the expansion fan-out unit is used for acquiring a binary data stream and generating an expanded binary data stream; a current processing unit for generating data values corresponding to respective bits of the binary data stream according to the expanded binary data stream; and a correction lower-order data unit for correcting data values corresponding to respective bits of the binary data stream to generate position information of the first 1 of the binary data stream. Leading zero detection can be carried out on the binary data stream, the position information of the first 1 of the binary data stream is determined, the input port of the leading zero detection circuit cannot be wasted, the time from the input of the data stream to the output of the result is shortened, and the calculation efficiency is improved.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a leading zero detection structure and a leading zero detection method.
Background
In the semiconductor field, leading zeros are the positions where the first 1 appears, which are scanned from the most significant bits of the binary data stream; and scanning from the highest bit of the binary data stream can acquire the number of 0's that appear by the first 1. Leading zeros are widely used in modern integrated circuit designs, such as floating point operations, out-of-order issue queues, multimedia instructions, etc. For example, the floating-point arithmetic process is complex, wherein detection of leading zero in the mantissa of the floating-point number is a key link in the floating-point arithmetic, and has an important influence on the entire arithmetic speed, the currently commonly used floating-point number format is the Institute of Electrical and Electronics Engineers (IEEE 754) standard, and the floating-point number precision includes 32-bit single precision, 64-bit double precision and more than 80-bit extended double precision; the procedure of detecting leading zeros of mantissas of floating-point numbers with these precisions is that the circuit can calculate the number of bits to be left-shifted by detecting the position of the first "1" of the two mantissas addition/subtraction results through a first zero counter, so that the left shift operation is performed immediately after the result is calculated, and the first "1" is shifted to the leftmost end. For another example, an important structure of out-of-order issue techniques in superscalar processors is issue queues; the state of the instruction in the queue is judged and the to-be-sent instruction is selected, which is generally the time sequence bottleneck of the sending queue, leading zeros of the sending queue can be detected through a leading zero circuit, and then a flag bit '1' of the sending queue is inquired, so that a queue vacancy or the to-be-sent instruction is judged, the entering and the sending of the instruction are scheduled, and the inquiring speed determines the performance of the sending queue.
In the prior art, an Nbit leading zero detection circuit may be adopted, N is the total number of bits of a binary data stream, fig. 1 is a schematic structural diagram of a 32-bit leading zero detection circuit in the prior art, as shown in fig. 1, taking the 32-bit leading zero detection circuit as an example, the structure includes two 16-bit LOPD structures, an and gate structure, a selector and an inverter, and the two 16-bit LOPD structures are respectively connected with the and gate structure, the selector and the inverter; each 16-bit LOPD structure consists of two 8-bit LOPD structures, an AND gate structure, a selector and an inverter, wherein the two 8-bit LOPD structures are respectively connected with the AND gate structure, the selector and the inverter; each 8-bit LOPD structure consists of two 4-bit LOPD structures, an AND gate structure, a selector and an inverter, wherein the two 4-bit LOPD structures are respectively connected with the AND gate structure, the selector and the inverter; and so on. It can be known that the value of N in the leading zero detection circuit of Nbit is determined by the total bit number of the binary data stream, the leading zero detection circuit of Nbit includes two N/2-bit LOPD structures, an and gate structure, a selector and an inverter, the two N/2-bit LOPD structures are respectively connected with the and gate structure, the selector and the inverter; each N/2-bit LOPD structure consists of two N/4-bit LOPD structures, an AND gate structure, a selector and an inverter, wherein the two N/4-bit LOPD structures are respectively connected with the AND gate structure, the selector and the inverter; and so on. Therefore, the Nbit leading zero detection circuit can receive the binary data stream with the number of N bits, detect the leading zero of the binary data stream, and determine the position where the first 1 of the binary data stream appears.
However, in the prior art, a structure is provided for repeatedly using a low-bit-number coded signal to continuously expand into a multi-bit sequence to search leading zeros, if the total bit number of an input binary data stream is within N but the total bit number is not N power of 2, a leading zero detection circuit of N power of 2bit can only be selected, for example, the total bit number of the input binary data stream is 17, a structure of a leading zero detection circuit of 32bit can only be selected, a structure of a leading zero detection circuit of 16bit can not be selected, and a leading zero detection circuit for 17 bit is not provided. Therefore, the input port of the leading zero detection circuit is wasted, the time from the input of the data stream to the output of the data stream is long, and meanwhile, the time is proportional to the evolution of the bits of the input binary data stream, and the calculation efficiency is low.
Disclosure of Invention
The invention provides a leading zero detection structure and a leading zero detection method, which are used for solving the problems that the input port of a leading zero detection circuit is wasted, the time from the input of a data stream to the output of a result is longer, meanwhile, the time is in direct proportion to the evolution of the bit number of an input binary data stream, and the calculation efficiency is lower in the prior art.
One aspect of the present invention provides a leading zero detection structure, including:
the fan-out unit, the current processing unit and the correction low-bit data unit are expanded;
the current processing unit is connected between the extension fan-out unit and the correction low-order data unit;
the extension fan-out unit is used for acquiring a binary data stream, performing extension processing on the binary data stream, and outputting the extended binary data stream to the current processing unit;
the current processing unit is used for generating data values corresponding to each bit of the binary data stream according to the expanded binary data stream and outputting the data values corresponding to each bit of the binary data stream to the correction low-bit data unit, wherein the data values represent whether 1 appears on the current bit of the binary data stream and each bit before the current bit;
and the correction low-bit data unit is used for correcting the data value corresponding to each bit of the binary data stream and generating the position information of the first 1 of the binary data stream.
Another aspect of the present invention provides a method for detecting leading zeros, including:
acquiring a binary data stream, and performing expansion processing on the binary data stream to generate an expanded binary data stream;
generating data values corresponding to each bit of the binary data stream according to the expanded binary data stream, wherein the data values represent whether 1 appears on the current bit and each bit before the current bit of the binary data stream;
the data values corresponding to the bits of the binary data stream are modified to generate position information of the first 1 of the binary data stream.
The invention has the technical effects that: the detection structure of leading zero formed by an extension fan-out unit, a current processing unit and a correction low-order data unit is provided, and the current processing unit is connected between the extension fan-out unit and the correction low-order data unit; the expansion fan-out unit is used for acquiring a binary data stream, performing expansion processing on the binary data stream and outputting the expanded binary data stream to the current processing unit; the current processing unit is used for generating data values corresponding to each bit of the binary data stream according to the expanded binary data stream and outputting the data values corresponding to each bit of the binary data stream to the correction low-bit data unit, wherein the data values represent whether 1 appears on the current bit of the binary data stream and each bit before the current bit; and a correction lower-order data unit for correcting data values corresponding to respective bits of the binary data stream to generate position information of the first 1 of the binary data stream. Therefore, leading zero detection can be carried out on the binary data stream, the position information of the first 1 of the binary data stream is determined, and the expansion fan-out unit carries out expansion processing on the binary data stream, so that the specific number of each subunit in the expansion fan-out unit can be correspondingly adjusted according to the total digit of the binary data stream, and the input port of the leading zero detection circuit cannot be wasted; the extended fan-out unit and the current processing unit can process the data on each bit of the binary data stream in parallel, and in the process, the calculation time of the process cannot be prolonged no matter the total number of bits of the binary data stream, so that the time from the input of the data stream to the output of the result is reduced, and the calculation efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a 32-bit leading zero detection circuit in the prior art;
fig. 2 is a schematic structural diagram of a leading zero detection structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a leading zero detection structure according to a second embodiment of the present invention;
FIG. 4 is a first circuit diagram of a leading zero detection structure according to a second embodiment of the present invention;
fig. 5 is a second circuit diagram of a leading zero detection structure according to a second embodiment of the present invention;
fig. 6 is a flowchart of a leading zero detection method according to a third embodiment of the present invention;
fig. 7 is a flowchart of a leading zero detection method according to a fourth embodiment of the present invention.
Reference numerals:
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 2 is a schematic structural diagram of a leading zero detection structure according to an embodiment of the present invention, and as shown in fig. 2, the leading zero detection structure according to this embodiment includes:
the fan-out extension unit 1, the current processing unit 2 and the correction low-order data unit 3;
the current processing unit 2 is connected between the extension fan-out unit 1 and the correction low-order data unit 3;
the expansion fan-out unit 1 is used for acquiring a binary data stream, performing expansion processing on the binary data stream, and outputting the expanded binary data stream to the current processing unit 2;
a current processing unit 2, configured to generate a data value corresponding to each bit of the binary data stream according to the expanded binary data stream, and output the data value corresponding to each bit of the binary data stream to a modified low-order data unit 3, where the data value represents whether or not 1 appears in a current bit of the binary data stream and each bit before the current bit;
and a correction lower-order data unit 3 for correcting a data value corresponding to each bit of the binary data stream to generate position information of the first 1 of the binary data stream.
In the embodiment, specifically, the leading zero detection structure is composed of an extended fan-out unit 1, a current processing unit 2 and a corrected lower data unit 3, and the current processing unit 2 is connected between the extended fan-out unit 1 and the corrected lower data unit 3.
After a terminal or other device outputs a binary data stream, the extension fan-out unit 1 may acquire the binary data stream, and then the extension fan-out unit 1 generates an extended binary data stream after the binary data stream is extended, and then outputs the extended binary data stream to the current processing unit 2. After receiving the expanded binary data stream, the current processing unit 2 generates a data value corresponding to each bit of the binary data stream according to the expanded binary data stream, and outputs the data value corresponding to each bit of the binary data stream to the modified lower data unit 3, where the data value indicates whether or not 1 appears in the current bit of the binary data stream and each bit before the current bit. Finally, the correction lower data unit 3 corrects the data value corresponding to each bit of the binary data stream, thereby generating the position information of the first 1 of the binary data stream.
For example, the extension fan-out unit 1 obtains a binary data stream 0010, generates the extended binary data streams 0, 00, 111, and 0000 after extension, and then the current processing unit 2 generates a data value 0 corresponding to a first bit according to the extended binary data stream, where the current bit is the first bit, and the data value 0 corresponding to the first bit represents that no 1 appears on the first bit of the current bit; generating a data value 0 corresponding to the second bit, wherein the current bit is the second bit, and the data value 0 corresponding to the second bit represents the second bit of the current bit and no 1 appears on each bit before the second bit of the current bit; generating a data value 1 corresponding to the third bit, wherein the current bit is the third bit, and the data value 1 corresponding to the third bit represents that 1 appears on the third bit of the current bit; and generating a data value 1 corresponding to the fourth bit, wherein the current bit is the fourth bit, and the data value 1 corresponding to the fourth bit represents the fourth bit of the current bit and 1 appears on each bit before the fourth bit of the current bit, so that 0011 is obtained. Finally, the correction low-order data unit 3 corrects 0011, and can determine that the third bit of the binary data stream is the position where the first 1 appears, so as to obtain the position information of the first 1 of the binary data stream 0010.
The embodiment provides a detection structure of leading zeros composed of an extended fan-out unit 1, a current processing unit 2 and a correction low-order data unit 3, wherein the current processing unit 2 is connected between the extended fan-out unit 1 and the correction low-order data unit 3; the expansion fan-out unit 1 is used for acquiring a binary data stream, performing expansion processing on the binary data stream, and outputting the expanded binary data stream to the current processing unit 2; a current processing unit 2, configured to generate a data value corresponding to each bit of the binary data stream according to the expanded binary data stream, and output the data value corresponding to each bit of the binary data stream to a modified low-order data unit 3, where the data value represents whether or not 1 appears in a current bit of the binary data stream and each bit before the current bit; and a correction lower-order data unit 3 for correcting a data value corresponding to each bit of the binary data stream to generate position information of the first 1 of the binary data stream. Therefore, leading zero detection can be carried out on the binary data stream, the position information of the first 1 of the binary data stream is determined, and the expansion fan-out unit 1 carries out expansion processing on the binary data stream, so that the specific number of each subunit in the expansion fan-out unit 1 can be correspondingly adjusted according to the total digit of the binary data stream, and the input port of the leading zero detection circuit cannot be wasted; in addition, the extended fan-out unit 1 and the current processing unit 2 can perform parallel processing on the data on each bit of the binary data stream, and in the process, the calculation time in the process cannot be prolonged no matter how many total bits of the binary data stream are, so that the time from the input of the data stream to the output of the data stream is reduced, and the calculation efficiency is improved.
Fig. 3 is a schematic structural diagram of a leading zero detection structure provided in a second embodiment of the present invention, fig. 4 is a first circuit diagram of the leading zero detection structure provided in the second embodiment of the present invention, and fig. 5 is a second circuit diagram of the leading zero detection structure provided in the second embodiment of the present invention, and on the basis of the first embodiment, as shown in fig. 3, fig. 4 and fig. 5, the extended fan-out unit 1 of the leading zero detection structure provided in the present embodiment includes:
the inverter chains 4 have the same number of stages;
each inverter chain 4 is configured to obtain data on one bit of the binary data stream, perform expansion processing on the data on the current bit, and copy and generate N expanded data of the current bit to form an expanded binary data stream, where N is the bit number of the current bit, N is an element [1, N ], and N is a positive integer.
The current processing unit 2 includes: a current source network subunit 5, a current output subunit 6 and a current comparison subunit 7;
the current source network subunit 5 and the current output unit subunit are respectively connected with the current comparison subunit 7, and the current comparison subunit 7 is connected with the correction low-bit data unit 3;
the current source network subunit 5 is configured to convert the expanded binary data stream into a current sum value, and output the current sum value to the current comparison subunit 7;
a current output subunit 6, configured to generate a comparison current value, and output the comparison current value to the current comparison subunit 7;
and a current comparison subunit 7 configured to compare the current sum value and the comparison current value and generate a data value corresponding to each bit of the binary data stream.
Current source network subunit 5, comprising:
n current source modules 8;
each current source module 8 corresponds to one inverter chain 4, each current source module 8 is provided with n current source sub-modules 9, and each current source sub-module 9 in each current source module 8 is connected in parallel;
the current source submodule 9 comprises a first current source 10 and a switch 11 connected in series;
the input end of each current source submodule 9 of each current source module 8 is connected with each inverter chain 4 in a staggered way, and the output end of each current source module 8 is connected with the first input end of the current comparison subunit 7;
each current source module 8 is adapted to determine the value of the current sum corresponding to the current bit n of the binary data stream.
A current output subunit 6 comprising:
a reference current generation module 12 and a threshold current generation module 13;
the output end of the reference current generation module 12 is connected with the output end of the threshold current generation module 13, and the threshold current generation module 13 is connected with the second input end of the current comparison subunit 7;
a reference current generation module 12 for generating a reference current value and outputting the reference current value to the threshold current generation module 13;
and a threshold current generation module 13, configured to generate a threshold current value, generate a comparison current value according to the reference current value and the threshold current value, and output the comparison current value to the current comparison subunit 7.
A reference current generation module 12, comprising:
n reference current generation sub-modules 14; each reference current generation submodule 14 comprises a second current source 15 and a resistor 16;
the second current source 15 is connected with one end of a resistor 16, and the other end of the resistor 16 is connected with the output end of the threshold current generation module 13;
and a second current source 15, for turning off to generate no current when the data of the current bit n of the binary data stream is 0, and for turning on to generate current when the data of the current bit n of the binary data stream is 1.
A threshold current generation module 13 comprising: n threshold current generation submodules 17; the threshold current generation submodule 17 comprises a third current source 18 and an adjustable resistor 19;
the third current source 18 is connected to one end of the adjustable resistor 19, and the other end of the adjustable resistor 19 is connected to the current comparison subunit 7.
A current comparison subunit 7, comprising:
n sense current amplifiers 20;
the first input end of each sense current amplifier 20 is connected with the output end of the current source network subunit 5 corresponding to the sense current amplifier 20 one by one, the second input end of each sense current amplifier 20 is connected with the output end of the threshold current generation submodule 17 corresponding to the sense current amplifier 20 one by one, and the output end of each sense current amplifier 20 is connected with the correction low-bit data unit 3;
each sense current amplifier 20 is configured to generate a data value 1 corresponding to a current bit n of the binary data stream when it is determined that the value of the current sum is greater than the comparison current value, and generate a data value 0 corresponding to the current bit n of the binary data stream when it is determined that the value of the current sum is equal to or less than the comparison current value.
The corrected lower data unit 3 includes:
n discharge network subunits 21;
each discharge network subunit 21 includes N parallel discharge modules 22, and each discharge module 22 includes an nmos (N-Metal-Oxide-Semiconductor, nmos for short) module 23 and a grounding module 24 connected in series;
the output end of each sense current amplifier 20 is connected with the first input end of the discharge module 22 in each discharge network subunit 21, which is located on the value of the number n of bits of each discharge network subunit 21, and the output end of each sense current amplifier 20 is connected with the second input end of each discharge module 22 in the discharge network subunit 21, which corresponds to the sense current amplifier 20 one by one;
each discharge network subunit 21 is configured to, when a data value 1 corresponding to a current bit n of the binary data stream is output from the sense current amplifier 20 corresponding to the discharge network subunit 21, not modify the data value of the current bit and determine that all data subsequent to the current bit is invalid, and when a data value 0 corresponding to the current bit n of the binary data stream is output from the sense current amplifier 20 corresponding to the discharge network subunit 21, not modify the data value, so as to generate position information of a first 1 of the binary data stream.
The structure still includes: a data compression unit 25;
the output end of each sense current amplifier 20 is connected with the second input end of each discharge module 22 in the discharge network subunit 21 corresponding to the sense current amplifier 20 one by one, and then is connected with the input end of the data compression unit 25;
and a data compressing unit 25 for compressing the data stream composed of the data values outputted from the correction lower data unit 3 to generate the number information of 0 before the first 1 of the binary data stream.
In this embodiment, specifically, the extended fan-out unit 1 includes N inverter chains 4, where the value of N is the same as the total number of bits of the binary data stream, and N is a positive integer; the inverter chains 4 have the same number of stages. Each inverter chain 4 can acquire data on one bit of the binary data stream, perform expansion processing on the data on the current bit, and copy and generate N expanded data of the current bit, thereby forming an expanded binary data stream, where N is the bit number of the current bit, N belongs to [1, N ], and N is a positive integer.
As shown in fig. 4, for a binary data stream 010 with three bits, 3 inverter chains 4 are included in the extended fan-out unit 1, and the number of stages of each inverter chain 4 is the same; the first inverter chain 4 acquires a first bit 0 of the binary data stream 010, and the first inverter chain 4 comprises three inverters connected in series and can output a 0; a second inverter chain 4 acquires a second bit 1 of the binary data stream 010, and the second inverter chain 4 has two inverters connected in series and two inverters connected in parallel in series and can output two 1 s; a third inverter chain 4, comprising one inverter and then two parallel inverters in series, then each of the parallel inverters is connected in series with two parallel inverters, may output three 0 s, obtaining the third bit 0 of the binary data stream 010. For a binary data stream with N digits, the structure of the expanding fan-out unit 1 is analogized according to the principle, so that an equal-delay inverter chain 4 is constructed for each bit of input data of the binary data stream, the same number of inverter stages among bits is ensured, and the fan-out quantity is different.
The current processing unit 2 comprises a current source network subunit 5, a current output subunit 6 and a current comparison subunit 7; the current source network subunit 5 and the current output unit subunit are respectively connected with the current comparison subunit 7, and the current comparison subunit 7 is connected with the correction low-order data unit 3. The current source network subunit 5 converts the expanded binary data stream into a current sum value, and outputs the current sum value to the current comparison subunit 7; and the current output subunit 6 may generate a comparison current value and output the comparison current value to the current comparison subunit 7; thus, the current comparison subunit 7 can generate data values corresponding to each bit of the binary data stream after comparing the current sum value and the comparison current value.
Specifically, the current source network subunit 5 is composed of N current source modules 8, each current source module 8 corresponds to one inverter chain 4, and there are N current source submodules 9 in each current source module 8, and the current source submodules 9 in each current source module 8 are connected in parallel. The current source submodule 9 comprises a first current source 10 and a switch 11 connected in series. As shown in fig. 5, the current source network subunit 5 is formed by N current source modules 8, and one current source submodule 9 in each current source module 8 has a first current source 10 and a switch 11, where the first current source 10 is a pmos transistor. The input of each current source submodule 9 of each current source module 8 may be connected to each inverter chain 4 in a staggered manner, and the output of each current source module 8 may be connected to the first input of the current comparison subunit 7. Each current source module 8 obtains the value of the current sum of the bit at the port of the current source module 8 based on kirchhoff's current law, that is, determines the value of the current sum corresponding to the current bit n of the binary data stream. As shown in fig. 4, for a binary data stream 010 with three bits, the current source network subunit 5 is formed by 3 current source modules 8, the first current source module 8 corresponds to the first inverter chain 4, the first current source module 8 has n-1 current source submodules 9, and the value of the current sum corresponding to the current bit n-1 of the binary data stream can be determined at the port of the first current source module 8 based on kirchhoff's current law; a second current source module 8 corresponds to the second inverter chain 4, the second current source module 8 having n-2 parallel current source submodules 9, and a value of a current sum corresponding to the current bit n-2 of the binary data stream may be determined at a port of the second current source module 8 based on kirchhoff's current law; a third current source module 8 corresponds to the third inverter chain 4, the third current source module 8 has n-3 parallel current source submodules 9, and a value of a current sum corresponding to the current bit n-3 of the binary data stream may be determined at a port of the third current source module 8 based on kirchhoff's current law; for a binary data stream of N bits, and so on. For a binary data stream 010 with three bits, an output end of a first inverter chain 4 of the extended fan-out unit 1 is connected to an input end of a 3 rd current source submodule 9 in a third current source module 8, an output end of a second inverter chain 4 is connected to an input end of a 2 nd current source submodule 9 in the second current source module 8 and an input end of a 2 nd current source submodule 9 in the third current source module 8, respectively, and an output end of the third inverter chain 4 is connected to an input end of a 1 st current source submodule 9 in the first current source module 8, an input end of a 1 st current source submodule 9 in the second current source module 8 and an input end of a 1 st current source submodule 9 in the third current source module 8, respectively; for a binary data stream of N bits, and so on; therefore, the high-order inverter chain 4 and the low-order inverter chain 4 are realized, the number of the switches 11 in the current source network subunit 5 is controlled to be different, the signal of the inverter chain 4 at the highest order can control all the switches 11 at the input order, the signal of the inverter chain 4 at the lowest order only controls one-order switch 11, and the fan-out number is different according to the number of the switches 11 in the current source network subunit 5 connected with the inverter chain 4.
In addition, the current source submodule 9 in each current source module 8 in the current source network subunit 5, wherein the first current source 10 adopts a pmos (Positive Channel Metal Oxide Semiconductor, referred to as pmos) tube as a power supply current source, and the current size of each current source submodule 9 and the current size of each current source module 8 can be changed by adjusting the size of the pmos tube. The larger the point current of the current source module 8 is, the higher the noise margin is, the smaller the current of the current source module 8 is, and the lower the power consumption of the whole structure is. Meanwhile, another pmos transistor may be used as the switch 11 to connect the input signal of the expanded binary data stream to the current source module 8, so as to convert the input signal into a current signal. Thus, from the high bit to the low bit of the sequence of the input binary data stream, one switch 11 is added to the current source network subunit 5 bit by bit, for example, a string of 8-bit input signals, where the highest bit, i.e., the first bit, is 1 switch 11, the 2 nd bit is two switches 11, and so on, and the 8 th bit is 8 switches.
The current output subunit 6 is composed of a reference current generating module 12 and a threshold current generating module 13, an output end of the reference current generating module 12 is connected with an output end of the threshold current generating module 13, and the threshold current generating module 13 is connected with a second input end of the current comparing subunit 7. Reference current generation module 12 may generate reference current value I1 and output reference current value I1 to threshold current generation module 13; the threshold current generation module 13 may generate the threshold current value I2, generate a comparison current value I3 according to the reference current value I1 and the threshold current value I2, and output the comparison current value I3 to the current comparison subunit 7.
Specifically, the reference current generation module 12 includes N reference current generation sub-modules 14; each reference current generating submodule 14 comprises a second current source 15 and a resistor 16. As shown in fig. 5, the second current source 15 in the reference current generation module 12 may employ a pmos transistor. The threshold current generation module 13 includes N threshold current generation submodules 17, and each threshold current generation submodule 17 includes a third current source 18 and an adjustable resistor 19. As shown in fig. 5, the third current source 18 in the threshold current generation module 13 may employ a pmos transistor. The current comparison subunit 7 includes N sense current amplifiers 20.
In each reference current generation submodule 14, the second current source 15 is connected to one end of a resistor 16, and the other end of the resistor 16 is connected to an output end of a threshold current generation submodule 17 corresponding to the reference current generation submodule 14 in the threshold current generation module 13. In each threshold current generation submodule 17, the third current source 18 is connected to one end of the adjustable resistor 19, and the other end of the adjustable resistor 19 is connected to the current comparison subunit 7, specifically, the other end of the adjustable resistor 19 is connected to a second input terminal of the sensitive current amplifier 20 corresponding to the threshold current generation submodule 17 in the current comparison subunit 7. That is, a first input terminal of each sense current amplifier 20 is connected to an output terminal of the current source network subunit 5 corresponding to the sense current amplifier 20 one to one, a second input terminal of each sense current amplifier 20 is connected to an output terminal of the threshold current generation submodule 17 corresponding to the sense current amplifier 20 one to one, and an output terminal of each sense current amplifier 20 is connected to the correction low-bit data unit 3.
Wherein the second current source 15 in the reference current generation block 12 is the same size as the pmos transistor in the current source network subunit 5, the resistor 16 in the reference current generation block 12 is used to simulate a current switch, and the size of the resistor 16 is the same as that of the switch 11 in the current source network subunit 5. Each threshold current generation submodule 17 in the threshold current generation module 13 is equivalent to a threshold current regulation valve, the size of a pmos transistor in the current source network subunit 5 is completely the same as the third current source 18 in the threshold current generation submodule 17, one pmos transistor is adopted as the adjustable resistor 19, the size of the threshold current value can be adjusted by the adjustable resistor 19, when the threshold current value is set to be half of the reference current value, the fault tolerance of the whole structure is the highest, and the smaller the threshold current value is set, the smaller the power consumption of the whole structure is.
The second current source 15 is turned off to generate no current when the data of the current bit n of the binary data stream is 0, and is turned on to generate current when the data of the current bit n of the binary data stream is 1. Each sense current amplifier 20 may generate a data value 1 corresponding to a current bit n of the binary data stream when the value of the current sum is determined to be greater than the comparative current value, and may generate a data value 0 corresponding to the current bit n of the binary data stream when the value of the current sum is determined to be less than or equal to the comparative current value.
As shown in fig. 4, for a binary data stream 010 with three bits, the current output subunit 6 includes a reference current generating module 12 and a threshold current generating module 13, the reference current generating module 12 includes 3 reference current generating sub-modules 14, and the threshold current generating module 13 includes 3 threshold current generating sub-modules 17; each reference current generation submodule 14 is provided with a second current source 15 and a resistor 16 which are connected in series, and each threshold current generation submodule 17 is provided with a third current source 18 and an adjustable resistor 19 which are connected in series; the current comparison subunit 7 includes 3 sense current amplifiers 20. The other end of the resistor 16 of the first reference current generation module 12 is connected to the other end of the adjustable resistor 19 of the first threshold current generation submodule 17, the other end of the adjustable resistor 19 of the first threshold current generation submodule 17 is connected to the second input end of the first sense current amplifier 20, and the output end of the first current source network subunit 5 is connected to the first input end of the first sense current amplifier 20; the other end of the resistor 16 of the second reference current generation module 12 is connected to the other end of the adjustable resistor 19 of the second threshold current generation submodule 17, the other end of the adjustable resistor 19 of the second threshold current generation submodule 17 is connected to the second input end of the second sense current amplifier 20, and the output end of the second current source network subunit 5 is connected to the first input end of the second sense current amplifier 20; the other end of the resistor 16 of the third reference current generating module 12 is connected to the other end of the adjustable resistor 19 of the third threshold current generating submodule 17, the other end of the adjustable resistor 19 of the third threshold current generating submodule 17 is connected to the second input end of the third sense current amplifier 20, and the output end of the third current source network subunit 5 is connected to the first input end of the third sense current amplifier 20. For the binary data stream of N bits, the reference current generation module 12, the threshold current generation module 13, the structure and the connection relationship of the current comparison subunit 7 are referred to, and so on.
The first reference current generation submodule 14 is turned off when the data according to the first bit of the binary data stream is 0 so as not to generate a current, and is turned on when the data according to the first bit of the binary data stream is 1 so as to generate a current, thereby obtaining a reference current value I1, the first threshold current generation submodule 17 generates a threshold current value I2, and simultaneously obtains a comparison current value I3 after accumulating in combination with the reference current value I1, and the first threshold current generation submodule 17 outputs the comparison current value I3 to the first sense current amplifier 20; the first sense current amplifier 20 generates a data value 1 corresponding to the current bit n of the binary data stream being 1, that is, a data value 1 corresponding to the first bit of the binary data stream when it is determined that the value xI of the current sum is greater than the comparison current value I3, based on the value xI of the current sum output from the first current source network subunit 5 and the comparison current value I3, and when it is determined that the value xI of the current sum is equal to or less than the comparison current value I3, generates a data value 0 corresponding to the current bit n of the binary data stream being 2, that is, generates a data value 0 corresponding to the second bit of the binary data stream when it is determined that the value xI of the current sum is equal to or less than the comparison current value I3, and indicates that no 1 is present in the first bit and the previous bits. And so on.
The modified low bit data unit 3 comprises N discharge network sub-units 21. Each discharge network subunit 21 comprises n parallel discharge modules 22, each discharge module 22 comprising a series-connected nmos module 23 and a ground module 24. As shown in fig. 5, each of the nmos tubes used for nmos module 23 in discharge module 22. The output terminal of each sense current amplifier 20 is connected to a first input terminal of a discharge module 22 in each discharge network subunit 21, which is located at the value of the number n of bits of each discharge network subunit 21, and the output terminal of each sense current amplifier 20 is connected to a second input terminal of each discharge module 22 in the discharge network subunit 21, which corresponds to the sense current amplifier 20 one to one. The structure provided by this embodiment further includes a data compression unit 25, and the data compression unit 25 may adopt an encoder; the output terminal of each sense current amplifier 20 is connected to the second input terminal of each discharge module 22 in the discharge network subunit 21 corresponding to the sense current amplifier 20 one by one, and then connected to the input terminal of the data compression unit 25. Each discharge network subunit 21 may not correct the data value of the current bit and determine that all data after the bit is invalid when it is determined that the data value 1 corresponding to the current bit n of the binary data stream is output from the sense current amplifier 20 corresponding to the discharge network subunit 21 one to one, and may not correct the data value when it is determined that the data value 0 corresponding to the current bit n of the binary data stream is output from the sense current amplifier 20 corresponding to the discharge network subunit 21 one to one, thereby generating the position information of the first 1 of the binary data stream; then, the data compressing unit 25 compresses the data stream composed of the data values outputted from the corrected lower data unit 3 to generate the number information of 0 before the first 1 of the binary data stream.
As shown in fig. 4 and 5, for a binary data stream 0010 of four bits, the modified lower data unit 3 includes 4 discharge network sub-units 21, 1 discharge module 22 in the first discharge network sub-unit 21, 2 parallel discharge modules 22 in the second discharge network sub-unit 21, 3 parallel discharge modules 22 in the third discharge network sub-unit 21, and 4 parallel discharge modules 22 in the fourth discharge network sub-unit 21. There are also 1 data compression unit 25. Each discharge module 22 comprises an nmos module 23 and a ground module 24 connected in series, the ground module 24 being used for grounding. The output of the first sense current amplifier 20 is connected to the input of the data compression unit 25, and the output of the first sense current amplifier 20 is connected to the first input of the nmos module 23 in the first discharge module 22 in the first discharge network subunit 21, the first input of the nmos module 23 in the first discharge module 22 in the second discharge network subunit 21, and the first input of the nmos module 23 in the first discharge module 22 in the third discharge network subunit 21, respectively. The output of the second sense current amplifier 20 is connected to the input of the data compression unit 25, the output of the second sense current amplifier 20 is connected to the first input of the nmos module 23 in the second discharging module 22 in the second discharging network subunit 21, the first input of the nmos module 23 in the second discharging module 22 in the third discharging network subunit 21, and the output of the second sense current amplifier 20 is connected to the second input of the nmos module 23 in the first discharging module 22 in the first discharging network subunit 21. The output of the third sense current amplifier 20 is connected to the input of the data compression unit 25, the output of the third sense current amplifier 20 is connected to the first input of the nmos module 23 in the third discharge module 22 in the third discharge network subunit 21 and the first input of the nmos module 23 in the third discharge module 22 in the fourth discharge network subunit 21, respectively, and the output of the third sense current amplifier 20 is connected to the second input of the nmos module 23 in the second discharge module 22 in the second discharge network subunit 21 and the second input of the nmos module 23 in the second discharge module 22 in the second discharge network subunit 21, respectively. And for the binary data stream of N bits, modifying the structure and connection relation of the lower data unit 3, and so on.
For example, for a binary data stream 0010 with four bits, the expansion fan-out unit 1 obtains one binary data stream 0010, and generates expanded binary data streams 0, 00, 111, and 0000 after expansion; the current processing unit 2 generates a data value 0 corresponding to the first bit, which indicates that 1 does not appear on the first bit, generates a data value 0 corresponding to the second bit, which indicates that 1 does not appear on the second bit and previous bits, generates a data value 1 corresponding to the third bit, which indicates that 1 appears on the third bit, and generates a data value 1 corresponding to the fourth bit, which indicates that 1 appears on the fourth bit and previous bits, to obtain 0011. Then, the modified lower data unit 3 may determine, for the data 0 of the first bit, that when the data value 0 corresponding to the first bit of the current bit of the binary data stream is output from the first sense current amplifier 20, the data value 0 is not modified; for the data 0 of the second bit, it can be determined that when the data value 0 corresponding to the second bit of the current bit of the binary data stream is output from the second sense current amplifier 20, the data value 0 is not corrected; for the data 1 of the third bit, when the data value 1 corresponding to the third bit of the current bit of the binary data stream is output from the third sense current amplifier 20, it may be determined that all data after the bit is invalid, and at this time, the data value 0 is not corrected, but all data values after the bit are corrected to 0, so that 0010 is obtained, and it may be determined that the position information of the first 1 of the binary data stream 0010 is the position where the first 1 of the third bit appears. Finally, the data compression unit 25 compresses a data stream 0010 made up of the data values outputted by the correction lower data unit 3 to obtain the number of 0's appearing until the first 1, and the data compression unit 25 obtains and outputs the number information of 0's before the first 1's of the binary data stream.
The embodiment provides a detection structure of leading zeros composed of an extended fan-out unit 1, a current processing unit 2 and a correction low-order data unit 3, wherein the current processing unit 2 is connected between the extended fan-out unit 1 and the correction low-order data unit 3; the expansion fan-out unit 1 is used for acquiring a binary data stream, performing expansion processing on the binary data stream, and outputting the expanded binary data stream to the current processing unit 2; a current processing unit 2, configured to generate a data value corresponding to each bit of the binary data stream according to the expanded binary data stream, and output the data value corresponding to each bit of the binary data stream to a modified low-order data unit 3, where the data value represents whether or not 1 appears in a current bit of the binary data stream and each bit before the current bit; and a correction lower-order data unit 3 for correcting a data value corresponding to each bit of the binary data stream to generate position information of the first 1 of the binary data stream. Therefore, leading zero detection can be carried out on the binary data stream, the position information of the first 1 and the number information of 0 before the first 1 of the binary data stream are determined, the binary data stream is expanded by the expanding fan-out unit 1, the expanding fan-out unit 1 adopts N parallel inverter chains 4, the current source network subunit 5 adopts N parallel current source modules 8, the reference current generation module 12 in the current output subunit 6 adopts N parallel reference current generation submodules 14, the threshold current generation module 13 in the current output subunit 6 adopts N parallel threshold current generation submodules 17, the current comparison subunit 7 adopts N parallel sensitive current amplifiers 20, and only parallel expansion is needed when expanding each unit, each subunit and each module according to the binary data streams with different total digits, furthermore, the extended fan-out unit 1 and the current processing unit 2 can perform parallel processing on the data on each bit of the binary data stream, and in the process, the calculation time in the process is not prolonged regardless of the total number of bits of the binary data stream, and only the correction low-bit data unit 3 has a certain time prolongation, so that the time from the input of the data stream to the output of the result is reduced, and the calculation efficiency is improved; meanwhile, according to binary data streams with different total digits, expansion of units, subunits and modules with corresponding quantity can be carried out, and therefore the input port of the leading zero detection circuit cannot be wasted.
Fig. 6 is a flowchart of a leading zero detection method according to a third embodiment of the present invention, and as shown in fig. 6, the method according to the third embodiment includes:
In this embodiment, specifically, after a terminal or other device outputs a binary data stream, the extension fan-out unit may acquire the binary data stream, and then generate an extended binary data stream after the extension fan-out unit performs extension processing on the binary data stream, and then output the extended binary data stream to the current processing unit.
In this embodiment, specifically, after receiving the expanded binary data stream, the current processing unit generates data values corresponding to each bit of the binary data stream according to the expanded binary data stream, and outputs the data values corresponding to each bit of the binary data stream to the modified lower-order data unit, where the data values indicate whether or not 1 appears in the current bit of the binary data stream and each bit before the current bit.
In the present embodiment, specifically, the correction lower data unit corrects the data value corresponding to each bit of the binary data stream, thereby generating the position information of the first 1 of the binary data stream.
The leading zero detection method provided in this embodiment adopts a leading zero detection structure provided in the first embodiment, and the structure and principle are the same.
In this embodiment, a binary data stream is obtained, and the binary data stream is expanded to generate an expanded binary data stream; generating data values corresponding to each bit of the binary data stream according to the expanded binary data stream, wherein the data values represent whether 1 appears on the current bit of the binary data stream and each bit before the current bit; the data values corresponding to the bits of the binary data stream are modified to generate position information of the first 1 of the binary data stream. Therefore, leading zero detection can be carried out on the binary data stream, the position information of the first 1 of the binary data stream is determined, and the expansion fan-out unit carries out expansion processing on the binary data stream, so that the specific number of each subunit in the expansion fan-out unit can be correspondingly adjusted according to the total digit of the binary data stream, and the input port of the leading zero detection circuit cannot be wasted; the extended fan-out unit and the current processing unit can process the data on each bit of the binary data stream in parallel, and in the process, the calculation time of the process cannot be prolonged no matter the total number of bits of the binary data stream, so that the time from the input of the data stream to the output of the result is reduced, and the calculation efficiency is improved.
Fig. 7 is a flowchart of a leading zero detection method according to a fourth embodiment of the present invention, and based on the third embodiment, as shown in fig. 7, the method provided in this embodiment, step 101, specifically includes:
acquiring data on one bit of a binary data stream by adopting each preset N inverter chains, expanding the data on the current bit, copying and generating N current bits of expanded data to form the expanded binary data stream, wherein N is the bit number of the current bit, N belongs to [1, N ], N is a positive integer, and N is a positive integer; the value of N is the same as the total number of bits in the binary data stream and the number of stages in each inverter chain is the same.
The specific implementation manner of step 1021 is as follows:
the method comprises the steps of determining a current sum value corresponding to a current bit N of a binary data stream by adopting each preset current source module of N current source modules, wherein each current source module corresponds to one inverter chain, each current source module is provided with N current source submodules, each current source submodule in each current source module is connected in parallel and comprises a first current source and a switch which are connected in series, and the input end of each current source submodule of each current source module is connected with each inverter chain in a staggered mode.
The specific implementation manner of step 1022 is: generating a reference current value; generating a threshold current value; a comparison current value will be generated from the reference current value and the threshold current value.
Generating a reference current value comprising: and each second current source in the preset N reference current generation sub-modules is adopted, the current generation sub-module is closed to generate no current when the data of the current bit N of the binary data stream is 0, and the current generation sub-module is closed to generate current when the data of the current bit N of the binary data stream is 1, wherein each reference current generation sub-module comprises a second current source and a resistor, and the second current source is connected with one end of the resistor.
After comparing the current sum value and the comparison current value, step 1023 generates a data value corresponding to each bit of the binary data stream.
The specific implementation manner of step 1023 is as follows:
and when the value of the current sum is determined to be less than or equal to the comparative current value, generating a data value 0 corresponding to the current bit N of the binary data stream.
when each preset discharge network subunit in the N discharge network subunits is adopted to determine a data value 1 corresponding to a current bit N of the binary data stream, not correcting the data value of the current bit and determining all data after the bit to be invalid, and when a data value 0 corresponding to the current bit N of the binary data stream is determined, not correcting the data value to generate position information of a first 1 of the binary data stream; each discharging network subunit comprises n discharging modules connected in parallel, and each discharging module comprises an nmos module and a grounding module which are connected in series.
After step 103, further comprising:
The leading zero detection method provided in this embodiment adopts a leading zero detection structure similar to that provided in the second embodiment, and the structure and principle are the same, and are not described herein again.
In this embodiment, an expansion fan-out unit is provided to obtain a binary data stream, and the binary data stream is expanded to generate an expanded binary data stream; a current processing unit which generates data values corresponding to each bit of the binary data stream according to the expanded binary data stream, wherein the data values represent whether 1 appears on the current bit and each bit before the current bit of the binary data stream; and a correction lower-order data unit for correcting the data value corresponding to each bit of the binary data stream to generate the position information of the first 1 of the binary data stream. The method comprises the steps of detecting leading zeros of a binary data stream, determining position information of a first 1 and number information of 0 before the first 1 of the binary data stream, expanding the binary data stream by an expanding fan-out unit, adopting N parallel inverter chains by the expanding fan-out unit, adopting N parallel current source modules by a current source network subunit, adopting N parallel reference current generation submodules by a reference current generation module in a current output subunit, adopting N parallel threshold current generation submodules by a threshold current generation module in the current output subunit, adopting N parallel sensitive current amplifiers by a current comparison subunit, expanding each unit, each subunit and each module according to the binary data stream with different total digits, and further expanding the fan-out unit, The current processing unit can process the data on each bit of the binary data stream in parallel, in the process, the calculation time in the process is not prolonged no matter the total number of bits of the binary data stream, and only the time in the correction low-bit data unit is prolonged to a certain extent, so that the time from the input of the data stream to the output of the data stream is reduced, and the calculation efficiency is improved; meanwhile, according to binary data streams with different total digits, expansion of units, subunits and modules with corresponding quantity can be carried out, and therefore the input port of the leading zero detection circuit cannot be wasted.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (14)
1. A leading zero detection architecture, comprising:
the fan-out unit, the current processing unit and the correction low-bit data unit are expanded;
the current processing unit is connected between the extension fan-out unit and the correction low-order data unit;
the extension fan-out unit is used for acquiring a binary data stream, performing extension processing on the binary data stream, and outputting the extended binary data stream to the current processing unit;
the current processing unit is used for generating data values corresponding to each bit of the binary data stream according to the expanded binary data stream and outputting the data values corresponding to each bit of the binary data stream to the correction low-bit data unit; wherein the data values characterize whether a 1 is present on a current bit of the binary data stream and on bits preceding the current bit;
and the correction low-bit data unit is used for correcting the data value corresponding to each bit of the binary data stream and generating the position information of the first 1 of the binary data stream.
2. The structure of claim 1, wherein the extended fan-out unit comprises:
n inverter chains, wherein the value of N is the same as the total number of bits of the binary data stream, and N is a positive integer;
the series of each inverter chain is the same;
each inverter chain is used for acquiring data on one bit of the binary data stream, expanding the data on the current bit, and copying and generating N current bits of expanded data to form the expanded binary data stream, wherein N is the bit number of the current bit, N belongs to [1, N ], and N is a positive integer.
3. The structure of claim 2, wherein the current handling unit comprises: the current source network comprises a current source network subunit, a current output subunit and a current comparison subunit;
the current source network subunit and the current output unit subunit are respectively connected with the current comparison subunit, and the current comparison subunit is connected with the correction low-bit data unit;
the current source network subunit is configured to convert the expanded binary data stream into a current sum value, and output the current sum value to the current comparison subunit;
the current output subunit is used for generating a comparison current value and outputting the comparison current value to the current comparison subunit;
and the current comparison subunit is used for comparing the current sum value and the comparison current value and then generating a data value corresponding to each bit of the binary data stream.
4. The structure of claim 3, wherein the current source network subunit comprises:
n current source modules;
each current source module corresponds to one inverter chain, each current source module is provided with n current source sub-modules, and each current source sub-module in each current source module is connected in parallel;
the current source submodule comprises a first current source and a switch which are connected in series;
the input end of each current source submodule of each current source module is connected with each inverter chain in a staggered mode, and the output end of each current source module is connected with the first input end of the current comparison subunit;
each current source module is used for determining the value of the current sum corresponding to the current bit n of the binary data stream.
5. The structure of claim 3, wherein the current output subunit comprises:
a reference current generation module and a threshold current generation module;
the output end of the reference current generation module is connected with the output end of the threshold current generation module, and the threshold current generation module is connected with the second input end of the current comparison subunit;
the reference current generation module is used for generating a reference current value and outputting the reference current value to the threshold current generation module;
the threshold current generation module is used for generating a threshold current value, generating a comparison current value according to the reference current value and the threshold current value, and outputting the comparison current value to the current comparison subunit.
6. The structure of claim 5, wherein the reference current generation module comprises:
n reference current generation sub-modules; each reference current generation submodule comprises a second current source and a resistor;
the second current source is connected with one end of the resistor, and the other end of the resistor is connected with the output end of the threshold current generation module;
and the second current source is used for turning off so as not to generate current when the data of the current bit n of the binary data stream is 0, and turning on so as to generate current when the data of the current bit n of the binary data stream is 1.
7. The structure of claim 5 or 6, wherein the threshold current generation module comprises:
n threshold current generation submodules; the threshold current generation submodule comprises a third current source and an adjustable resistor;
the third current source is connected with one end of the adjustable resistor, and the other end of the adjustable resistor is connected with the current comparison subunit.
8. The structure of claim 5, wherein the current comparison subunit comprises:
n sense current amplifiers;
the first input end of each sensitive current amplifier is connected with the output ends of the current source network subunits corresponding to the sensitive current amplifiers one by one, the second input end of each sensitive current amplifier is connected with the output ends of the threshold current generation submodules corresponding to the sensitive current amplifiers one by one, and the output end of each sensitive current amplifier is connected with the correction low-bit data unit;
each sensitive current amplifier is used for generating a data value 1 corresponding to the current bit n of the binary data stream when the current sum is determined to be larger than the comparison current value, and generating a data value 0 corresponding to the current bit n of the binary data stream when the current sum is determined to be smaller than or equal to the comparison current value.
9. The structure of claim 8, wherein said modified lower data element comprises:
n discharge network subunits;
each discharging network subunit comprises n discharging modules connected in parallel, and each discharging module comprises an nmos module and a grounding module which are connected in series;
the output end of each sensitive current amplifier is connected with the first input end of a discharge module in each discharge network subunit, which is positioned on the value of the number n of bits of each discharge network subunit, and the output end of each sensitive current amplifier is connected with the second input end of each discharge module in the discharge network subunit, which corresponds to the sensitive current amplifier one by one;
each discharge network subunit is used for not correcting the data value of the current bit and determining that all data after the bit is invalid when the data value 1 corresponding to the current bit n of the binary data stream is output from the sensitive current amplifier corresponding to the discharge network subunit one by one, and not correcting the data value when the data value 0 corresponding to the current bit n of the binary data stream is output from the sensitive current amplifier corresponding to the discharge network subunit one by one, so as to generate the position information of the first 1 of the binary data stream.
10. The structure of claim 9, further comprising: a data compression unit;
the output end of each sensitive current amplifier is connected with the second input end of each discharging module in the discharging network sub-unit which corresponds to the sensitive current amplifier one by one, and then is connected with the input end of the data compression unit;
and the data compression unit is used for compressing the data stream formed by the data values output by the correction low-order data unit and generating the number information of 0 before the first 1 of the binary data stream.
11. A method for detecting leading zeros, comprising:
acquiring a binary data stream, and performing expansion processing on the binary data stream to generate an expanded binary data stream;
generating data values corresponding to each bit of the binary data stream according to the expanded binary data stream, wherein the data values represent whether 1 appears on the current bit and each bit before the current bit of the binary data stream;
the data values corresponding to the bits of the binary data stream are modified to generate position information of the first 1 of the binary data stream.
12. The method of claim 11, wherein generating data values corresponding to bits of the binary data stream from the expanded binary data stream comprises:
converting the expanded binary data stream into a current sum value;
generating a comparison current value;
after comparing the current sum value and the comparison current value, a data value corresponding to each bit of the binary data stream is generated.
13. The method of claim 12, wherein generating the comparative current value comprises:
generating a reference current value;
generating a threshold current value;
a comparison current value will be generated from the reference current value and the threshold current value.
14. The method of claim 13, wherein the generating the reference current value comprises:
and each second current source in the preset N reference current generation sub-modules is adopted, the current generation sub-module is closed to generate no current when the data of the current bit N of the binary data stream is 0, and the current generation sub-module is closed to generate current when the data of the current bit N of the binary data stream is 1, wherein each reference current generation sub-module comprises a second current source and a resistor, and the second current source is connected with one end of the resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611208564.XA CN108241483B (en) | 2016-12-23 | 2016-12-23 | Leading zero detection structure and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611208564.XA CN108241483B (en) | 2016-12-23 | 2016-12-23 | Leading zero detection structure and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108241483A CN108241483A (en) | 2018-07-03 |
| CN108241483B true CN108241483B (en) | 2020-09-22 |
Family
ID=62704250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611208564.XA Active CN108241483B (en) | 2016-12-23 | 2016-12-23 | Leading zero detection structure and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108241483B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6697828B1 (en) * | 2000-06-01 | 2004-02-24 | Sun Microsystems, Inc. | Optimized method and apparatus for parallel leading zero/one detection |
| CN201628951U (en) * | 2009-12-31 | 2010-11-10 | 西北工业大学 | High-speed floating point normalization arithmetic unit |
| CN102664637A (en) * | 2012-04-12 | 2012-09-12 | 北京中科晶上科技有限公司 | Method and device for confirming leading zero number of binary data |
| CN105786444A (en) * | 2014-12-26 | 2016-07-20 | 联想(北京)有限公司 | Detection method and apparatus for leading zeros in mantissas of floating-point number |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013210838A (en) * | 2012-03-30 | 2013-10-10 | Fujitsu Ltd | Arithmetic circuit and arithmetic method |
-
2016
- 2016-12-23 CN CN201611208564.XA patent/CN108241483B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6697828B1 (en) * | 2000-06-01 | 2004-02-24 | Sun Microsystems, Inc. | Optimized method and apparatus for parallel leading zero/one detection |
| CN201628951U (en) * | 2009-12-31 | 2010-11-10 | 西北工业大学 | High-speed floating point normalization arithmetic unit |
| CN102664637A (en) * | 2012-04-12 | 2012-09-12 | 北京中科晶上科技有限公司 | Method and device for confirming leading zero number of binary data |
| CN105786444A (en) * | 2014-12-26 | 2016-07-20 | 联想(北京)有限公司 | Detection method and apparatus for leading zeros in mantissas of floating-point number |
Non-Patent Citations (1)
| Title |
|---|
| "Low-power leading-zero counting and anticipation logic for high-speed floating point units";Giorgos Dimitrakopoulos等;《IEEE Transactions on Very Large Scale Integration (VLSI) Systems》;20080731;第16卷(第7期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108241483A (en) | 2018-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3857353B1 (en) | Apparatuses and methods to accelerate matrix multiplication | |
| WO2017048474A1 (en) | Low-power double error correcting-triple error detecting (deb-ted) decoder | |
| CN106940638B (en) | Hardware architecture of binary original code addition and subtraction arithmetic unit | |
| CN105320491B (en) | Apparatus and method for achieving efficient division performance | |
| Sheng-Ju | Implementation of cyclic redundancy check in data communication | |
| CN108241483B (en) | Leading zero detection structure and method | |
| CN110073604B (en) | Data decompressor and integrated circuit and method for decompressing data | |
| US20200192633A1 (en) | Arithmetic processing device and method of controlling arithmetic processing device | |
| TWI520053B (en) | A hardware integer saturation detector, a detecting saturation method and a detecting saturation hardware apparatus | |
| CN114201140B (en) | Exponential function processing unit, method and neural network chip | |
| Kornerup | Correcting the normalization shift of redundant binary representations | |
| CN112350716B (en) | Complement operation method and device and operation method of complement operation device | |
| KR101922462B1 (en) | A data processing apparatus and method for performing a shift function on a binary number | |
| US9280316B2 (en) | Fast normalization in a mixed precision floating-point unit | |
| CN115833845B (en) | Position output device and position output method | |
| US20070094318A1 (en) | Method and system for hardware efficient systematic approximation of square functions for communication systems | |
| US20110122964A1 (en) | Binary Arithmetic Coding Device | |
| US20200067522A1 (en) | Decoder circuit and decoder circuit design method | |
| US9455743B2 (en) | Dedicated arithmetic encoding instruction | |
| US20060277246A1 (en) | Multiplication circuitry | |
| CN112671411B (en) | Bidirectional conversion circuit of floating point data format based on IEEE754 and POSIT | |
| US8954833B2 (en) | Half width counting leading zero circuit using comparators | |
| TWI489374B (en) | System and method for determination of a horizontal minimum of digital values | |
| US20220091820A1 (en) | Storage medium and operation device | |
| US10003360B2 (en) | Device and method for finding error location |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |