CN108241483A - The detection structure and method of leading zero - Google Patents
The detection structure and method of leading zero Download PDFInfo
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Abstract
The present invention provides a kind of detection structure and method of leading zero, which includes：By providing the detection structure of leading zero being made of extension fan out unit, current processing unit and amendment low data unit, current processing unit is connected between extension fan out unit and amendment low data unit；Fan out unit is extended, for obtaining binary data stream, the binary data stream after generation extension；Current processing unit, for according to the binary data stream after extension, generating everybody corresponding data value with binary data stream；Low data unit is corrected, is modified with everybody corresponding data value of binary data stream for Dui, generates first 1 location information of binary data stream.The detection of leading zero can be carried out to binary data stream, determines first 1 location information of binary data stream, the input port of leading zero detection circuit will not be wasted, the time that data flow is input to output result is reduced, improves computational efficiency.
Description
Technical field
The present invention relates to semiconductor integrated circuit field more particularly to the detection structures and method of a kind of leading zero.
Background technology
In semiconductor applications, leading zero is that first 1 appearance is scanned since the highest order of binary data stream
Position；And scanned since the highest order of binary data stream, occur between can getting until first 1
0 number.Leading zero in the design of modern integrated circuits using very extensive, such as floating-point operation, out of order transmitting queue, more matchmakers
Body instruction etc..For example, floating point arithmetic process is complicated, the detection of wherein floating number mantissa leading zero is one in floating point arithmetic
The key link, has entire arithmetic speed important influence, and currently used floating number format is U.S. electric and electronics work
Association of Engineers (Institute of Electrical and Electronics Engineers, abbreviation IEEE754) standard,
Floating number precision includes 32 single precisions, and 64 double precisions and 80 or more extend double precision；To the floating number of these precision
The process of mantissa leading zero detection is circuit by detecting the position of first " 1 " of Liang Ge mantissa plus/minus result, so as to can
With the digit moved to left by the calculating of first to-zero counter, so as to carry out shift left operation immediately after result is calculated, make first " 1 "
Move to left end.For another example the important feature of the out of order lift-off technology in superscalar processor is exactly to emit queue；Judge queue
It the state of middle instruction and selects to wait to send instructions, typically emits the sequential bottleneck of queue, leading zero circuit pair can be passed through
The leading zero of transmitting queue is detected, and then inquires the flag bit " 1 " of transmitting queue, so as to judge queue vacancy or treat
Send instructions, the entrance and transmitting of dispatch command, inquiry velocity determine the performance of transmitting queue.
In the prior art, a kind of leading zero detection circuit of N bit may be used, N is the total bit of binary data stream,
Fig. 1 is the structure diagram of the leading zero detection circuit of 32bit of the prior art, as shown in Figure 1, the leading zero with 32bit
For detection circuit, it is anti-that which includes the LOPD structures of two 16-bit, one and door, a selector and one
Phase device, the LOPD structures of two 16-bit are connect respectively and with door, selector, phase inverter；The LOPD of each 16-bit
Structure by two 8-bit LOPD structures, one formed with door, a selector and a phase inverter, two 8-bit's
LOPD structures are connect respectively and with door, selector, phase inverter；And the LOPD structures of each 8-bit are by two 4-bit's
LOPD structures, one formed with door, a selector and phase inverter, the LOPD structures of two 4-bit respectively and with
Door, selector, phase inverter connection；And so on.It is found that in the leading zero detection circuit of N bit N value, by binary system
The total bit of data flow determines that the leading zero detection circuit of N bit includes the LOPD structures of two N/2-bit, one and door
Structure, a selector and a phase inverter, the LOPD structures of two N/2-bit respectively and with door, selector, phase inverter
Connection；The LOPD structures of each N/2-bit by two N/4-bit LOPD structures, one with door, a selector and
One phase inverter is formed, and the LOPD structures of two N/4-bit are connect respectively and with door, selector, phase inverter；With such
It pushes away.So as to which the leading zero detection circuit of the N bit can receive the binary data stream within N digits, to binary data stream
The detection of leading zero is carried out, determines the position of first 1 appearance of binary data stream.
However in the prior art, it is a kind of encoded signal for reusing lower-order digit to provide, and goes constantly to be extended to multidigit sequence
Arrange and search the structure of leading zero, if input binary data stream total bit is within N but total bit is not 2 n times
Side can only also select the leading zero detection circuit of 2 n times side bit, such as the total bit of the binary data stream of input is 17,
The structure of the leading zero detection circuit of 32bit can only be selected, it is impossible to select the structure of the leading zero detection circuit of 16bit, and not have
There is the leading zero detection circuit for 17.So as to which the input port of leading zero detection circuit can be wasted, and causes data flow
The time for being input to output result can be longer, while the time can be with the evolution of the digit of the binary data stream of input into just
Than computational efficiency is relatively low.
Invention content
The present invention provides a kind of detection structure and method of leading zero, to solve to waste leading zero inspection in the prior art
The input port of slowdown monitoring circuit, and data flow is caused to be input to time of output result can be longer, while the time can be with input
Binary data stream digit evolution it is directly proportional, the problem of computational efficiency is relatively low.
It is an aspect of the present invention to provide a kind of detection structure of leading zero, including：
It extends fan out unit, current processing unit and corrects low data unit；
The current processing unit is connected between the extension fan out unit and the amendment low data unit；
For obtaining binary data stream, processing is extended to the binary data stream for the extension fan out unit,
And the binary data stream after extension is exported to the current processing unit；
The current processing unit, for according to the binary data stream after extension, generating each with binary data stream
The corresponding data value in position, and everybody the corresponding data value with binary data stream is exported to the amendment low data list
Whether member occurs 1 on everybody before the present bit and present bit of data value characterization binary data stream；
The amendment low data unit, is modified for Dui with everybody corresponding data value of binary data stream,
Generate first 1 location information of binary data stream.
Another aspect of the present invention is to provide a kind of detection method of leading zero, including：
Binary data stream is obtained, processing, the binary number after generation extension are extended to the binary data stream
According to stream；
According to the binary data stream after extension, everybody corresponding data value with binary data stream, the number are generated
According to value characterization binary data stream present bit and present bit before everybody on whether occur 1；
It pair is modified with everybody corresponding data value of binary data stream, generates first the 1 of binary data stream
Location information.
The solution have the advantages that：By providing by extension fan out unit, current processing unit and correcting low data
The detection structure for the leading zero that unit is formed, current processing unit be connected to extension fan out unit with correct low data unit it
Between；Fan out unit is extended, for obtaining binary data stream, processing is extended to binary data stream, and will be after extension
Binary data stream, which exports, gives current processing unit；Current processing unit, for according to the binary data stream after extension, generation
With everybody corresponding data value of binary data stream, and everybody the corresponding data value with binary data stream is exported to repairing
Whether positive low data unit occurs 1 on everybody before the present bit and present bit of data value characterization binary data stream；
Low data unit is corrected, is modified with everybody corresponding data value of binary data stream for Dui, generates binary number
According to first 1 location information of stream.So as to carry out the detection of leading zero to binary data stream, binary data is determined
First 1 location information of stream, and since extension fan out unit is extended binary data stream processing, and then can root
The specific number of each subelement in extension fan out unit is adjusted accordingly according to the total bit of binary number data flow, before will not wasting
Lead the input port of zero detection circuit；And extend fan out unit, current processing unit can be to each of binary data stream
Data on position carry out parallel processing, in this process, no matter the total bit of binary data stream is how many, this process
The calculating time will not extend, so as to reduce data flow be input to output result time, improve computational efficiency.
Description of the drawings
Fig. 1 is the structure diagram of the leading zero detection circuit of 32bit of the prior art；
Fig. 2 is the structure diagram of the detection structure of leading zero that the embodiment of the present invention one provides；
Fig. 3 is the structure diagram of the detection structure of leading zero provided by Embodiment 2 of the present invention；
Fig. 4 is the circuit diagram one of the detection structure of leading zero provided by Embodiment 2 of the present invention；
Fig. 5 is the circuit diagram two of the detection structure of leading zero provided by Embodiment 2 of the present invention；
Fig. 6 is the flow chart of the detection method of leading zero that the embodiment of the present invention three provides；
Fig. 7 is the flow chart of the detection method of leading zero that the embodiment of the present invention four provides.
Reference numeral：
Specific embodiment
Purpose, technical scheme and advantage to make the embodiment of the present invention are clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
All other embodiments obtained without making creative work shall fall within the protection scope of the present invention.
Fig. 2 is the structure diagram of the detection structure of leading zero that the embodiment of the present invention one provides, as shown in Fig. 2, this reality
The detection structure of the leading zero of offer is provided, including：
It extends fan out unit 1, current processing unit 2 and corrects low data unit 3；
Current processing unit 2 is connected between extension fan out unit 1 and amendment low data unit 3；
Fan out unit 1 is extended, for obtaining binary data stream, processing is extended to binary data stream, and will expand
Binary data stream after exhibition is exported to current processing unit 2；
Current processing unit 2, for according to the binary data stream after extension, generate with binary data stream everybody is right
The data value answered, and everybody the corresponding data value with binary data stream is exported and gives amendment low data unit 3, data value
Characterize binary data stream present bit and present bit before everybody on whether occur 1；
Low data unit 3 is corrected, is modified with everybody corresponding data value of binary data stream for Dui, is generated
First 1 location information of binary data stream.
In the present embodiment, specifically, the detection structure of leading zero is by extension fan out unit 1, current processing unit 2 and repaiies
Positive low data unit 3 is formed, by current processing unit 2 be connected to extension fan out unit 1 with correct low data unit 3 it
Between.
After terminal or other devices output a binary data stream, extension fan out unit 1 can get this
Then binary data stream is extended after fan out unit 1 is extended processing to binary data stream, two after generation extension into
Then data flow processed exports the binary data stream after extending to current processing unit 2.Current processing unit 2 receives
After binary data stream after extension, generated according to the binary data stream after extension every corresponding with binary data stream
Data value, and by everybody the corresponding data value with binary data stream export give correct low data unit 3, wherein, number
According to value characterization binary data stream present bit and present bit before everybody on whether occur 1.Finally, low data is corrected
3 pairs of unit is modified with everybody corresponding data value of binary data stream, so as to generate first the 1 of binary data stream
Location information.
For example, extension fan out unit 1 gets a binary data stream 0010, and two after generation extends after expansion
Binary data stream 0,00,111,0000, then current processing unit 2 is according to the binary data stream after extension, generation and first
The corresponding data value 0 in position, present bit at this time is first, and data value 0 corresponding with first characterizes present bit first at this time
Without occurring 1 on position；Generation data value 0 corresponding with second, present bit at this time is second, corresponding with second at this time
Data value 0 characterize present bit second and present bit second before everybody is upper without occurring 1；Generation is right with third position
The data value 1 answered, present bit at this time is third position, and data value 1 corresponding with third position is characterized on present bit third position at this time
Occur 1；Corresponding with the 4th data value 1 of generation, present bit at this time is the 4th, at this time with the 4th corresponding data
Value 1 characterize present bit the 4th and present bit the 4th before everybody on occur 1, obtained 0011.Finally, it corrects low
Position data cell 3 is modified to 0011, it may be determined that and the third position of binary data stream is the position of first 1 appearance, into
And obtain first 1 location information of binary data stream 0010.
The present embodiment is made of by providing extension fan out unit 1, current processing unit 2 and amendment low data unit 3
Leading zero detection structure, current processing unit 2 is connected to extension fan out unit 1 and corrects between low data unit 3；Expand
Open up fan out unit 1, for obtaining binary data stream, be extended processing to binary data stream, and by two after extension into
Data flow processed is exported to current processing unit 2；Current processing unit 2, for according to the binary data stream after extension, generation with
Everybody corresponding data value of binary data stream, and everybody the corresponding data value with binary data stream is exported to amendment
Low data unit 3, data value characterization binary data stream present bit and present bit before everybody on whether occur 1；
Low data unit 3 is corrected, is modified with everybody corresponding data value of binary data stream for Dui, generates binary number
According to first 1 location information of stream.So as to carry out the detection of leading zero to binary data stream, binary data is determined
First 1 location information of stream, and since extension fan out unit 1 is extended binary data stream processing, and then can be with
Adjust the specific number of each subelement in extension fan out unit 1, Bu Huilang accordingly according to the total bit of binary number data flow
Take the input port of leading zero detection circuit；And extend fan out unit 1, current processing unit 2 can be to binary data stream
Each on data carry out parallel processing, in this process, no matter the total bit of binary data stream is how many, this
The calculating time of one process will not extend, and so as to reduce the time that data flow is input to output result, improve computational efficiency.
Fig. 3 is the structure diagram of the detection structure of leading zero provided by Embodiment 2 of the present invention, and Fig. 4 is implemented for the present invention
The circuit diagram one of the detection structure for the leading zero that example two provides, Fig. 5 are the detection knot of leading zero provided by Embodiment 2 of the present invention
The circuit diagram two of structure, on the basis of embodiment one, as shown in Fig. 3, Fig. 4 and Fig. 5, the detection knot of leading zero provided by the embodiment
Structure extends fan out unit 1, including：
N number of chain of inverters 4, the wherein numerical value of N are identical with the total bit of binary data stream, and N is positive integer；
The series of each chain of inverters 4 is identical；
Each chain of inverters 4, for obtaining the data on binary data stream position, and to the number in present bit
According to processing is extended, the data after the extension of n present bit of generation are replicated, to form the binary data stream after extending,
In, n is the digit of present bit, and n ∈ [1, N], n are positive integer.
Current processing unit 2, including：Current Sources subelement 5, electric current output subelement 6 and electric current comparing subunit
7；
Current Sources subelement 5, current output unit are connect respectively with electric current comparing subunit 7, and electric current is more sub
Unit 7 is connect with correcting low data unit 3；
Current Sources subelement 5, for the value that the binary data stream after extending is electric current sum, and by electric current
The value of sum is exported to electric current comparing subunit 7；
Electric current exports subelement 6, compares current value for generating, and will compare current value and export and give electric current comparing subunit
7；
Electric current comparing subunit 7, for electric current sum value, compare after current value is compared, generation and binary system
Everybody corresponding data value of data flow.
Current Sources subelement 5, including：
N number of current source module 8；
Each current source module 8 is corresponding with a chain of inverters 4, has the electricity of n in each current source module 8
Stream source submodule 9, each current source submodule 9 is in parallel in each current source module 8；
Current source submodule 9 includes the first current source 10 of series connection and switch 11；
The input terminal of each current source submodule 9 of each current source module 8 is connected with the dislocation of each chain of inverters 4, each
The output terminal of a current source module 8 is connect with the first input end of electric current comparing subunit 7；
Each current source module 8, for determine electric current corresponding with binary data stream present bit n and value.
Electric current exports subelement 6, including：
Reference current generation module 12 and threshold current generation module 13；
The output terminal of reference current generation module 12 is connect with the output terminal of threshold current generation module 13, threshold current life
It is connect into module 13 with the second input terminal of electric current comparing subunit 7；
Reference current generation module 12 for generating reference current value, and reference current value is exported and is given birth to threshold current
Into module 13；
Threshold current generation module 13 for generating threshold current value, and is given birth to according to reference current value and threshold current value
Into current value is compared, current value will be compared and exported to electric current comparing subunit 7.
Reference current generation module 12, including：
N number of reference current generates submodule 14；Each reference current generation submodule 14 includes 15 He of the second current source
Resistance 16；
Second current source 15 is connect with one end of resistance 16, and the other end of resistance 16 is defeated with threshold current generation module 13
Outlet connects；
Second current source 15, for being closed not generate electricity when the data of binary data stream present bit n are 0
Stream is closed to generate electric current when the data of binary number data flow present bit n are 1.
Threshold current generation module 13, including：N number of threshold current generates submodule 17；Threshold current generates submodule 17
Including third current source 18 and adjustable resistance 19；
Third current source 18 is connect with one end of adjustable resistance 19, the other end and the electric current comparing subunit of adjustable resistance 19
7 connections.
Electric current comparing subunit 7, including：
N number of sensitive current amplifier 20；
The first input end of each sensitive current amplifier 20 and with sensitive 20 one-to-one electric current of current amplifier
Source network subelement 5 output terminal connection, the second input terminal of each sensitive current amplifier 20 and with sensitive Current amplifier
The output terminal connection of 20 one-to-one threshold current of device generation submodule 17, the output terminal of each sensitive current amplifier 20
It is connect with correcting low data unit 3；
Each sensitive current amplifier 20, for determine the value of electric current sum be more than compare current value when, generation with two into
The corresponding data values 1 of present bit n of data flow processed determine that the value of electric current sum is less than or equal to when comparing current value, generation with two into
The corresponding data values 0 of present bit n of data flow processed.
Low data unit 3 is corrected, including：
N number of discharge network subelement 21；
Each discharge network subelement 21 includes n discharge module 22 in parallel, and discharge module 22 includes series connection
Nmos (N-Metal-Oxide-Semiconductor, abbreviation nmos) module 23 and earthing module 24；
It is located at each discharge network in the output terminal of each sensitive current amplifier 20 and each discharge network subelement 21
Discharge module 22 in the value of the digit n of subelement 21 first input end connection, each sensitive current amplifier 20 it is defeated
Outlet and the second input with each discharge module 22 in sensitive 20 one-to-one discharge network subelement 21 of current amplifier
End connection；
Each discharge network subelement 21, for the one-to-one sensitive current amplifier of discharge network subelement 21
When the corresponding data value 1 with the present bit n of binary data stream is outputed in 20, the data value of present bit is not corrected and determines to be somebody's turn to do
All data invalids after position are determined with being outputed in the one-to-one sensitive current amplifier 20 of discharge network subelement 21
During the data value 0 of n corresponding with the present bit of binary data stream, data value is not corrected, to generate first the 1 of binary data stream
Location information.
Structure further includes：Data compression unit 25；
The output terminal of each sensitive current amplifier 20 and with sensitive 20 one-to-one discharge network of current amplifier
After the second input terminal connection of each discharge module 22 in subelement 21, it is connect with the input terminal of data compression unit 25；
Data compression unit 25, the data flow that each data value for being exported to correcting low data unit 3 is formed carry out
Compression generates before first the 1 of binary data stream 0 number information.
In the present embodiment, specifically, extension fan out unit 1 includes N number of chain of inverters 4, wherein the numerical value of N and two into
The total bit of data flow processed is identical, and N is positive integer；Also, the series of each chain of inverters 4 is identical.Each chain of inverters 4, can
To obtain the data on binary data stream position, and processing is extended to the data in present bit, life can be replicated
Data into after the extension of n present bit, and then the binary data stream after extension is formed, wherein, digits of the n for present bit, n
∈ [1, N], n are positive integer.
As shown in figure 4, for for the binary data stream 010 of three, extend in fan out unit 1 and include 3 reverse phases
Device chain 4, the series of each chain of inverters 4 are identical；First chain of inverters 4 obtains first 0 of binary data stream 010,
First chain of inverters 4 includes the phase inverter of three series connection, can export one 0；Second chain of inverters 4 obtains binary system
The second 1 of data flow 010, tool is there are two upper two of the phase inverter and series connection connected in parallel in second chain of inverters 4
Phase inverter can export two 1；Third chain of inverters 4 obtains the third position 0 of binary data stream 010, third phase inverter
Chain 4 includes a phase inverter, upper two phase inverters in parallel of then connecting, then each reverse phase in phase inverter in parallel
Upper two phase inverters in parallel of device series connection, can export three 0.For the binary data stream of N digits, extension is fanned out to list
The structure of member 1 is analogized according to principle above, so as to which binary data stream is the delays such as each input data structure
Chain of inverters 4, phase inverter series is identical between ensureing everybody, and be fanned out to quantity difference.
Current processing unit 2 includes Current Sources subelement 5, electric current output subelement 6 and electric current comparing subunit
7；Current Sources subelement 5, current output unit are connect respectively with electric current comparing subunit 7, electric current comparing subunit 7 with
Low data unit 3 is corrected to connect.Wherein, the binary data stream after extension is electric current by Current Sources subelement 5
The value of sum, and the value of electric current sum is exported to electric current comparing subunit 7；And electric current output subelement 6 can generate and compare electric current
Value, and current value will be compared and exported to electric current comparing subunit 7；So as to electric current comparing subunit 7, can to the value of electric current sum,
Compare after current value is compared, generate everybody corresponding data value with binary data stream.
Specifically, Current Sources subelement 5 is made of N number of current source module 8, each current source module 8 and one
A chain of inverters 4 is corresponding, and has the current source submodule 9 of n, each current source in each current source module 8
Each current source submodule 9 is in parallel in module 8.Current source submodule 9 includes the first current source 10 of series connection and switch 11.Such as Fig. 5
Shown, Current Sources subelement 5 is made of N number of current source module 8, and current source in each current source module 8
Have in module 9 there are one the first current source 10 and a switch 11, wherein, the first current source 10 is managed using pmos.It can will be every
The input terminal of each current source submodule 9 of one current source module 8 is connected with the dislocation of each chain of inverters 4, each current source mould
The output terminal of block 8 is connect with the first input end of electric current comparing subunit 7.Each current source module 8, based on kirchhoff electricity
Law is flowed, the value of the electric current sum of this is obtained in the port of current source module 8, that is, is determined and binary data stream present bit n
The value of corresponding electric current sum.As shown in figure 4, for for the binary data stream 010 of three, Current Sources subelement 5 is by 3
A current source module 8 is formed, and first current source module 8 is corresponding with first chain of inverters 4, first current source module 8
It, can be true in the port of first current source module 8 based on Kirchhoff's current law (KCL) with n=1 current source submodule 9
Make electric current corresponding with binary data stream present bit n=1 and value；Second current source module 8 and second phase inverter
Chain 4 is corresponding, and second current source module 8 has n=2 current source submodule 9 in parallel, can be based on kirchhoff electric current
Law determined in the port of second current source module 8 electric current corresponding with binary data stream present bit n=2 and
Value；Third current source module 8 is corresponding with third chain of inverters 4, third current source module 8 have n=3 parallel connection
Current source submodule 9, can be determined based on Kirchhoff's current law (KCL) in the port of the third current source module 8 with two into
The value of the corresponding electric current sum of data flow present bit n=3 processed；For the binary data stream of N, and so on.For three
For binary data stream 010, extend in the output terminal of the first chain of inverters 4 of fan out unit 1 and third current source module 8
The 3rd current source submodule 9 input terminal connection, the output terminal of the second chain of inverters 4 respectively with second current source module 8
In the 2nd current source submodule 9 input terminal, the 2nd current source submodule 9 in third current source module 8 input
End connection, the output terminal of third chain of inverters 4 are defeated with the 1st current source submodule 9 in first current source module 8 respectively
Enter the 1st in end, the input terminal of the 1st current source submodule 9 in second current source module 8, third current source module 8
The input terminal connection of a current source submodule 9；For the binary data stream of N, and so on；So as to fulfill high-order and low level
Chain of inverters 4, controls the number difference of the switch 11 in Current Sources subelement 5, and the signal of the chain of inverters 4 of highest order can be controlled
The switch 11 of all input bits is made, 4 signal of chain of inverters of lowest order only controls One-position switch 11, and then according to chain of inverters 4
11 quantity of switch in the Current Sources subelement 5 connected is fanned out to quantity difference.
Also, the current source submodule 9 in each current source module 8 in Current Sources subelement 5, the first electricity therein
Stream source 10 is using pmos (Positive Channel Metal Oxide Semiconductor, abbreviation pmos) pipes using as confession
Electric current source, can be by adjusting the sizes of pmos pipes, to change the size of current of each current source submodule 9 and every
The size of current of one current source module 8.The point electric current of current source module 8 is bigger, then noise margin is higher, current source module 8
Electric current is smaller, and the power consumption of total is lower.Meanwhile another pmos pipes may be used as switch 11, by two after extension into
The input signal of data flow processed is linked into current source module 8, so as to which input signal is converted to current signal.Thus from defeated
A high position for the sequence of the binary data stream entered can increase a switch 11, such as to low level by turn in Current Sources subelement 5
The input signal of a string of 8bit, highest order i.e. first are that 1 the 11, the 2nd, switch is two switches 11, and so on, the 8th
For 8 switches.
Electric current output subelement 6 is made of reference current generation module 12 and threshold current generation module 13, reference current
The output terminal of generation module 12 is connect with the output terminal of threshold current generation module 13, threshold current generation module 13 and electric current ratio
The second input terminal compared with subelement 7 connects.Reference current generation module 12 can generate reference current value I1, and by reference current
Value I1 is exported to threshold current generation module 13；Threshold current generation module 13 can generate threshold current value I2, and according to ginseng
It examines current value I1 and threshold current value I2 generations and compares current value I3, current value I3 will be compared and exported to electric current comparing subunit 7.
Specifically, reference current generation module 12 includes N number of reference current generation submodule 14；Each is with reference to electricity
Stream generation submodule 14 includes the second current source 15 and resistance 16.As shown in figure 5, the second electricity in reference current generation module 12
Pmos pipes may be used in stream source 15.Threshold current generation module 13 includes N number of threshold current generation submodule 17, each threshold
It is worth electric current generation submodule 17 and includes third current source 18 and adjustable resistance 19.As shown in figure 5, in threshold current generation module 13
Third current source 18 may be used pmos pipe.Electric current comparing subunit 7 includes N number of sensitive current amplifier 20.
In each reference current generates submodule 14, the second current source 15 is connect with one end of resistance 16, resistance 16
The other end in threshold current generation module 13 with reference current generation submodule 14 corresponding threshold current generation
The output terminal connection of module 17.In each threshold current generation submodule 17, third current source 18 and the one of adjustable resistance 19
End connection, the other end of adjustable resistance 19 connect with electric current comparing subunit 7, specifically, the other end of adjustable resistance 19 and
Second input terminal of sensitive current amplifier 20 corresponding with threshold current generation submodule 17 connects in electric current comparing subunit 7
It connects.That is, the first input end of each sensitive current amplifier 20 and with sensitive 20 one-to-one current source of current amplifier
Network subelement 5 output terminal connection, the second input terminal of each sensitive current amplifier 20 and with sensitive current amplifier
The output terminal connection of 20 one-to-one threshold currents generation submodules 17, the output terminal of each sensitive current amplifier 20 with
Low data unit 3 is corrected to connect.
Wherein, the second current source 15 in reference current generation module 12, with pmos pipes in Current Sources subelement 5
Size is identical, and the resistance 16 in reference current generation module 12 goes analog current to switch, the resistance 16 and current source
The size of switch 11 in network subelement 5 is identical.Each threshold current generation submodule in threshold current generation module 13
Block 17 is equivalent to a threshold current control valve, and threshold current generates third current source 18 and current source net in submodule 17
The size of pmos pipes is identical in string bag unit 5, and adjustable resistance 19 employs a pmos pipe, and adjustable resistance 19 can be adjusted
The size of threshold current value, when threshold current value is set as the half of reference current value, the fault-tolerance highest of total, threshold
It is worth the smaller of current value setting, the power consumption of total is smaller.
Second current source 15 is closed when the data of binary data stream present bit n are 0 not generate electric current,
The data of binary number data flow present bit n are closed to generate electric current when being 1.And each sensitive current amplifier 20 is true
The value of constant current sum can generate data value 1 corresponding with the present bit n of binary data stream more than when comparing current value,
When determining that the value of electric current sum is less than or equal to compare current value, data corresponding with the present bit n of binary data stream can be generated
Value 0.
As shown in figure 4, for for the binary data stream 010 of three, electric current output subelement 6 includes a reference
Electric current generation module 12 and a threshold current generation module 13, reference current generation module 12 include 3 reference current lifes
Into submodule 14, threshold current generation module 13 includes 3 threshold current generation submodules 17；Each reference current generates
In submodule 14 there is the second current source 15 of series connection and resistance 16, there is series connection in each threshold current generation submodule 17
Third current source 18 and adjustable resistance 19；Electric current comparing subunit 7 includes 3 sensitive current amplifiers 20.First reference
The other end of the resistance 16 of electric current generation module 12 is another with the adjustable resistance 19 of first threshold current generation submodule 17
End connection, the other end and first sensitive current amplifier 20 of the adjustable resistance 19 of first threshold current generation submodule 17
The connection of the second input terminal, the of the output terminal of first Current Sources subelement 5 and first sensitive current amplifier 20
One input terminal connects；The other end of the resistance 16 of second reference current generation module 12 and second threshold current generation submodule
The other end connection of the adjustable resistance 19 of block 17, the other end of the adjustable resistance 19 of second threshold current generation submodule 17 with
The second input terminal connection of second sensitive current amplifier 20, the output terminal and second of second Current Sources subelement 5
The first input end connection of a sensitive current amplifier 20；The other end of the resistance 16 of third reference current generation module 12 with
The other end connection of the adjustable resistance 19 of third threshold current generation submodule 17, third threshold current generation submodule 17
The second input terminal of the other end and third sensitive current amplifier 20 of adjustable resistance 19 connect, third Current Sources
The output terminal of subelement 5 is connect with the first input end of the sensitive current amplifier 20 of third.For the binary data stream of N
For, reference current generation module 12, threshold current generation module 13, electric current comparing subunit 7 structure and connection relation, with
This analogizes.
First reference current generates submodule 14 and is closed when being 0 according to the primary data of binary data stream
Not generate electric current, it is closed when the primary data of binary number data flow are 1 to generate electric current, so as to obtain one
Reference current value I1, first threshold current generation submodule 17 generates threshold current value I2, in combination with reference current value I1
Carry out it is cumulative after obtain comparing current value I3, first threshold current generation submodule 17 will compare current value I3 and export to the
One sensitive current amplifier 20；What first sensitive current amplifier 20 was exported according to first Current Sources subelement 5
The value xI of electric current sum and compare current value I3, however, it is determined that the value xI of electric current sum is more than and compares current value I3, then generation with two into
The corresponding data values 1 of present bit n=1 of data flow processed, i.e. generation and first corresponding data value 1 of binary data stream, this
When represent occur 1 in first and before everybody, however, it is determined that when the value xI of electric current sum is less than or equal to compare current value I3,
Then generate data value 0 corresponding with the present bit n=2 of binary data stream, i.e. generation and the second pair of binary data stream
The data value 0 answered is represented in first and before everybody at this time without occurring 1.And so on.
It corrects low data unit 3 and includes N number of discharge network subelement 21.Each discharge network subelement 21 includes
N discharge module 22 in parallel, each discharge module 22 include the nmos modules 23 of series connection and earthing module 24.Such as Fig. 5
Nmos pipes shown, that nmos modules 23 use in each discharge module 22.The output terminal of each sensitive current amplifier 20
With first of the discharge module 22 in the value of the digit n positioned at each discharge network subelement 21 in each discharge network subelement 21
Input terminal connect, the output terminal of each sensitive current amplifier 20 and with sensitive current amplifier 20 correspondingly electric discharge net
The second input terminal connection of each discharge module 22 in string bag unit 21.Structure provided in this embodiment further comprises a data
An encoder may be used in compression unit 25, the data compression unit 25；The output terminal of each sensitive current amplifier 20
Connect with the second input terminal of each discharge module 22 in sensitive 20 one-to-one discharge network subelement 21 of current amplifier
After connecing, it is connect with the input terminal of data compression unit 25.Each discharge network subelement 21 can determine and electric discharge net
Data corresponding with the present bit n of binary data stream are outputed in the one-to-one sensitive current amplifier 20 of string bag unit 21
During value 1, the data value of present bit is not corrected and determines all data invalids after this, is being determined and discharge network subelement
When outputing the data value 0 of n corresponding with the present bit of binary data stream in 21 one-to-one sensitive current amplifiers 20, no
Data value is corrected, so as to generate first the 1 of binary data stream location information；Then, data compression unit 25 can be right
The data flow that each data value of 3 output of low data unit is formed is corrected to be compressed, generate binary data stream first 1 it
Preceding 0 number information.
As shown in Figure 4 and Figure 5, it for for the binary data stream 0010 of four, corrects low data unit 3 and includes 4
A discharge network subelement 21,1 discharge module 22 in first discharge network subelement 21, second discharge network subelement
2 discharge modules 22 in parallel in 21,3 discharge modules 22 in parallel in third discharge network subelement 21, the 4th puts
4 discharge modules 22 in parallel in electric network subelement 21.Also there is 1 data compression unit 25.Each discharge module 22
Nmos modules 23 and earthing module 24 including series connection, earthing module 24 are used to be grounded.First sensitive current amplifier 20
Output terminal is connected with the input terminal of data compression unit 25, also, the output terminal of first sensitive current amplifier 20, respectively and
The first input end of the nmos modules 23 in first discharge module 22 on first discharge network subelement 21, second put
First input end, third discharge network of the nmos modules 23 in first discharge module 22 on electric network subelement 21
The first input end connection of the nmos modules 23 in first discharge module 22 on unit 21.Second sensitive current amplifier
20 output terminal is connected with the input terminal of data compression unit 25, also, the output terminal of second sensitive current amplifier 20, point
The first input end of nmos modules 23 not and in second discharge module 22 on second discharge network subelement 21, third
The first input end connection of the nmos modules 23 in second discharge module 22 on a discharge network subelement 21, also, the
In first discharge module 22 on the output terminal and first discharge network subelement 21 of two sensitive current amplifiers 20
Second input terminal of nmos modules 23.The third output terminal of sensitive current amplifier 20 and the input terminal of data compression unit 25
Connection, also, the output terminal of third sensitive current amplifier 20, respectively with the third on third discharge network subelement 21
Third electric discharge mould on the first input end of nmos modules 23 in a discharge module 22, the 4th discharge network subelement 21
The first input end connection of nmos modules 23 in block 22, also, the output terminal of third sensitive current amplifier 20, respectively and
Second input terminal of the nmos modules 23 in second discharge module 22 on second discharge network subelement 21, second put
Second input terminal of the nmos modules 23 in second discharge module 22 on electric network subelement 21.Be directed to the two of N into
Data flow processed corrects the structure and connection relation of low data unit 3, and so on.
For example, the binary data stream 0010 for four, extension fan out unit 1 get a binary data
Stream 0010, the binary data stream 0,00,111,0000 after expansion after generation extension；After current processing unit 2 is according to extension
Binary data stream generates data value 0 corresponding with first, characterizes first upper no appearance 1, and generation is corresponding with second
Data value 0, characterize second and before everybody is upper without occurring 1, generate data value 1 corresponding with third position, characterize
Occur 1 on third position, generate data value 1 corresponding with the 4th and characterize the 4th and everybody upper appearance 1 before, obtain
0011.Then, it corrects low data unit 3 and is directed to primary data 0, it may be determined that in the first sensitive current amplifier 20
When outputing with first corresponding data value 0 of the present bit of binary data stream, then the data value 0 is not corrected；It is directed to
The data 0 of two, it may be determined that the present bit second with binary data stream is outputed in the second sensitive current amplifier 20
During corresponding data value 0, then the data value 0 is not corrected；It is directed to the data 1 of third position, it may be determined that the sensitive electric current of third is put
When outputing the corresponding data value 1 with the present bit third position of binary data stream in big device 20, determine all after this
Data invalid does not correct the data value 0, but data value all after this is modified to 0 at this time, so as to obtain 0010,
First 1 location information that can determine binary data stream 0010 is the position that third position is first 1 appearance.Finally, number
It compresses, is cut to correcting the data flow 0010 that each data value that low data unit 3 exports is formed according to compression unit 25
Only until first 1 between 0 number that occurs, and then data compression unit 25 obtains and binary data output stream
0 number information before first 1.
The present embodiment is made of by providing extension fan out unit 1, current processing unit 2 and amendment low data unit 3
Leading zero detection structure, current processing unit 2 is connected to extension fan out unit 1 and corrects between low data unit 3；Expand
Open up fan out unit 1, for obtaining binary data stream, be extended processing to binary data stream, and by two after extension into
Data flow processed is exported to current processing unit 2；Current processing unit 2, for according to the binary data stream after extension, generation with
Everybody corresponding data value of binary data stream, and everybody the corresponding data value with binary data stream is exported to amendment
Low data unit 3, data value characterization binary data stream present bit and present bit before everybody on whether occur 1；
Low data unit 3 is corrected, is modified with everybody corresponding data value of binary data stream for Dui, generates binary number
According to first 1 location information of stream.So as to carry out the detection of leading zero to binary data stream, binary data is determined
0 number information before first 1 location information of stream and first 1, and since extension fan out unit 1 is to binary data
Stream carries out extension process, and since extension fan out unit 1 uses N number of parallel chain of inverters 4, Current Sources subelement 5
Using N number of parallel current source module 8, the reference current generation module 12 in electric current output subelement 6 uses N number of parallel ginseng
Electric current generation submodule 14 is examined, the threshold current generation module 13 that electric current is exported in subelement 6 uses N number of parallel threshold current
Submodule 17 is generated, electric current comparing subunit 7 is using N number of parallel sensitive current amplifier 20, for the two of different total bits
Binary data stream, when being expanded to each unit, each subelement, each module, it is only necessary to parallel expansion, and then and extend fan
Go out unit 1, current processing unit 2 can to binary data stream each on data carry out parallel processing, at this
It in the process, only can be low in amendment no matter the total bit of binary data stream is how many, and the calculating time of this process will not extend
In the data cell 3 of position there is the regular hour to extend, so as to reduce the time that data flow is input to output result, improve meter
Calculate efficiency；It can cause the binary data stream according to different total bits simultaneously, each unit, each son for carrying out respective numbers are single
The expansion of first, each module, so as to which the input port of leading zero detection circuit will not be wasted.
Fig. 6 is the flow chart of the detection method of leading zero that the embodiment of the present invention three provides, as shown in fig. 6, the present embodiment
The method of offer, including：
Step 101 obtains binary data stream, is extended processing to binary data stream, generation extend after two into
Data flow processed.
In the present embodiment, specifically, after terminal or other devices output a binary data stream, extension fan
The binary data stream can be got by going out unit, then extend fan out unit and processing is extended to binary data stream
Afterwards, the binary data stream after generation extension, then which is exported give current processing unit.
Step 102, according to the binary data stream after extension, generate everybody corresponding data with binary data stream
Value, data value characterization binary data stream present bit and present bit before everybody on whether occur 1.
In the present embodiment, specifically, current processing unit receive extension after binary data stream after, according to expansion
Binary data stream generation and everybody corresponding data value of binary data stream after exhibition, and will be each with binary data stream
The corresponding data value in position is exported to correcting low data unit, wherein, the present bit of data value characterization binary data stream and
Whether occur 1 on everybody before present bit.
Step 103 pair is modified with everybody corresponding data value of binary data stream, generates binary data stream
First 1 location information.
In the present embodiment, specifically, correcting everybody corresponding data of low data unit pair and binary data stream
Value is modified, so as to generate first the 1 of binary data stream location information.
The detection method of leading zero provided in this embodiment, using the detection knot of the leading zero with being provided in embodiment one
Structure, structure are identical with principle.
The present embodiment is extended binary data stream processing, after generation extension by obtaining binary data stream
Binary data stream；According to the binary data stream after extension, everybody corresponding data value of generation and binary data stream is several
According to value characterization binary data stream present bit and present bit before everybody on whether occur 1；Pair and binary data stream
Everybody corresponding data value be modified, generate first 1 location information of binary data stream.So as to binary system
Data flow carries out the detection of leading zero, determines first 1 location information of binary data stream, and since extension is fanned out to list
Member is extended binary data stream processing, and then can adjust extension fan accordingly according to the total bit of binary number data flow
Go out the specific number of each subelement in unit, the input port of leading zero detection circuit will not be wasted；And it extends and is fanned out to list
Member, current processing unit can to binary data stream each on data carry out parallel processing, in this process,
No matter the total bit of binary data stream is how many, the calculating time of this process will not extend, defeated so as to reduce data flow
Enter the time to output result, improve computational efficiency.
Fig. 7 is the flow chart of the detection method of leading zero that the embodiment of the present invention four provides, on the basis of embodiment three,
As shown in fig. 7, method provided in this embodiment, step 101, specifically includes：
Using each chain of inverters in preset N number of chain of inverters, obtain on a position of binary data stream
Data, and the data in present bit are extended with processing, the data after the extension of n present bit of generation are replicated, are expanded with forming
Binary data stream after exhibition, wherein, n is the digit of present bit, and n ∈ [1, N], n are positive integer, and N is positive integer；The numerical value of N
Identical with the total bit of binary data stream, the series of each chain of inverters is identical.
Step 102, including：
Step 1021, by the binary data stream after extension be electric current sum value.
Wherein, the specific implementation of step 1021 is：
Using each current source module in preset N number of current source module, determine and binary data stream present bit n
The value of corresponding electric current sum, wherein, each current source module is corresponding with a chain of inverters, in each current source module
With the current source submodule of n, each current source submodule is in parallel in each current source module, and current source submodule includes string
The first current source and switch of connection, input terminal and each chain of inverters of each current source submodule of each current source module misplace
Connection.
Current value is compared in step 1022, generation.
Wherein, the specific implementation of step 1022 is：Generate reference current value；Generate threshold current value；It will be according to ginseng
It examines current value and current value is compared in threshold current value generation.
Reference current value is generated, including：Using each second electric current in preset N number of reference current generation submodule
Source is closed not generate electric current when the data of binary data stream present bit n are 0, in binary number data flow present bit n
Data be 1 when be closed to generate electric current, wherein, each reference current generation submodule include the second current source and electricity
One end of resistance, the second current source and resistance connects.
Step 1023, to the value of electric current sum, compare after current value is compared, generation and binary data stream everybody
Corresponding data value.
Wherein, the specific implementation of step 1023 is：
Using each sensitive current amplifier in preset N number of sensitive current amplifier, determine that the value of electric current sum is big
When current value is compared, generate corresponding with the present bit n of binary data stream data value 1, determine the value of electric current sum less than etc.
When current value is compared, data value 0 corresponding with the present bit n of binary data stream is generated.
Step 103, it specifically includes：
Using each discharge network subelement in preset N number of discharge network subelement, determining and binary data
During the corresponding data value 1 of the present bit n of stream, the data value of present bit is not corrected and determines all data invalids after this,
When determining the data value 0 of n corresponding with the present bit of binary data stream, data value is not corrected, to generate binary data stream
First 1 location information；Wherein, each discharge network subelement includes n discharge module in parallel, and discharge module includes
The nmos modules and earthing module of series connection.
After step 103, further include：
Step 201, the data flow formed to each data value are compressed, and are generated 0 before first the 1 of binary data stream
Number information.
The detection method of leading zero provided in this embodiment, using the detection knot of the leading zero with being provided in embodiment two
Structure, structure is identical with principle, and details are not described herein again.
The present embodiment extends fan out unit by offer and obtains binary data stream, and place is extended to binary data stream
Reason, the binary data stream after generation extension；Current processing unit, according to the binary data stream after extension, generation with two into
Everybody corresponding data value of data flow processed, everybody before the present bit and present bit of data value characterization binary data stream
On whether occur 1；Low data unit is corrected, pair is modified with everybody corresponding data value of binary data stream, generation
First 1 location information of binary data stream.So as to carry out the detection of leading zero to binary data stream, two are determined
0 number information before first 1 location information of binary data stream and first 1, and since extension fan out unit is to two
Binary data stream carries out extension process, and since extension fan out unit is using N number of parallel chain of inverters, Current Sources
Unit uses N number of parallel current source module, and the reference current generation module that electric current is exported in subelement uses N number of parallel ginseng
Electric current generation submodule is examined, the threshold current generation module that electric current is exported in subelement is generated using N number of parallel threshold current
Submodule, electric current comparing subunit is using N number of parallel sensitive current amplifier, for the binary data of different total bits
Stream, when being expanded to each unit, each subelement, each module, it is only necessary to parallel expansion, and then and extend fan out unit,
Current processing unit can to binary data stream each on data carry out parallel processing, in this process, no
The total bit of pipe binary data stream is how many, and the calculating time of this process will not extend, and can only correct low data list
In member there is the regular hour to extend, so as to reduce the time that data flow is input to output result, improve computational efficiency；Together
When can cause binary data stream according to different total bits, carry out each units of respective numbers, each subelement, each module
It expands, so as to which the input port of leading zero detection circuit will not be wasted.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above-mentioned each method embodiment can lead to
The relevant hardware of program instruction is crossed to complete.Aforementioned program can be stored in a computer read/write memory medium.The journey
Sequence when being executed, performs the step of including above-mentioned each method embodiment；And aforementioned storage medium includes：ROM, RAM, magnetic disc or
The various media that can store program code such as person's CD.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that：It still may be used
To modify to the technical solution recorded in foregoing embodiments or carry out equivalent replacement to which part technical characteristic；
And these modification or replace, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (14)
1. a kind of detection structure of leading zero, which is characterized in that including：
It extends fan out unit, current processing unit and corrects low data unit；
The current processing unit is connected between the extension fan out unit and the amendment low data unit；
The extension fan out unit for obtaining binary data stream, is extended the binary data stream processing, and will
Binary data stream after extension is exported to the current processing unit；
The current processing unit, for according to the binary data stream after extension, generate with binary data stream everybody is right
The data value answered, and everybody the corresponding data value with binary data stream is exported to the amendment low data unit；Its
In, whether occur 1 on everybody before the present bit and present bit of data value characterization binary data stream；
The amendment low data unit, is modified for Dui with everybody corresponding data value of binary data stream, generates
First 1 location information of binary data stream.
2. structure according to claim 1, which is characterized in that the extension fan out unit, including：
The numerical value of N number of chain of inverters, wherein N is identical with the total bit of binary data stream, and N is positive integer；
The series of each chain of inverters is identical；
Each chain of inverters, for obtaining the data on binary data stream position, and to the data in present bit into
Row extension process replicates the data after the extension of n present bit of generation, to form the binary data stream after extending, wherein, n
For the digit of present bit, n ∈ [1, N], n are positive integer.
3. structure according to claim 2, which is characterized in that the current processing unit, including：Current Sources is single
Member, electric current output subelement and electric current comparing subunit；
The Current Sources subelement, current output unit are connect respectively with the electric current comparing subunit, described
Electric current comparing subunit is connect with the amendment low data unit；
The Current Sources subelement, for the value that the binary data stream after extending is electric current sum, and by electric current
The value of sum is exported to the electric current comparing subunit；
The electric current exports subelement, compares current value for generating, and the relatively current value is exported to the electric current ratio
Compared with subelement；
The electric current comparing subunit, for the value, described after relatively current value is compared to the electric current sum, generation with
Everybody corresponding data value of binary data stream.
4. structure according to claim 3, which is characterized in that the Current Sources subelement, including：
N number of current source module；
Each current source module is corresponding with a chain of inverters, has current source of n in each current source module
Module, each current source submodule is in parallel in each current source module；
The current source submodule includes the first current source and switch of series connection；
The input terminal of each current source submodule of each current source module is connected with the dislocation of each chain of inverters, each current source
The output terminal of module is connect with the first input end of electric current comparing subunit；
Each current source module, for determine electric current corresponding with binary data stream present bit n and value.
5. structure according to claim 3, which is characterized in that the electric current exports subelement, including：
Reference current generation module and threshold current generation module；
The output terminal of the reference current generation module is connect with the output terminal of the threshold current generation module, the threshold value electricity
Stream generation module is connect with the second input terminal of the electric current comparing subunit；
The reference current generation module for generating reference current value, and the reference current value is exported to the threshold value
Electric current generation module；
The threshold current generation module, for generating threshold current value, and according to the reference current value and threshold value electricity
Current value is compared in flow valuve generation, and the relatively current value is exported to the electric current comparing subunit.
6. structure according to claim 5, which is characterized in that the reference current generation module, including：
N number of reference current generates submodule；Each reference current generation submodule includes the second current source and resistance；
Second current source is connect with one end of the resistance, the other end of the resistance and the threshold current generation module
Output terminal connection；
Second current source, for being closed when the data of binary data stream present bit n are 0 not generate electric current,
It is closed to generate electric current when the data of binary number data flow present bit n are 1.
7. structure according to claim 5 or 6, which is characterized in that the threshold current generation module, including：
N number of threshold current generates submodule；Threshold current generation submodule includes third current source and adjustable resistance；
The third current source is connect with one end of the adjustable resistance, and the other end of the adjustable resistance is compared with the electric current
Subelement connects.
8. structure according to claim 5, which is characterized in that the electric current comparing subunit, including：
N number of sensitive current amplifier；
The first input end of each sensitive current amplifier and Current Sources one-to-one with sensitive current amplifier
The output terminal connection of unit, the second input terminal of each sensitive current amplifier and one-to-one with sensitive current amplifier
The output terminal connection of threshold current generation submodule, the output terminal of each sensitive current amplifier and the amendment low data
Unit connects；
Each sensitive current amplifier, during for determining that the value of the electric current sum is more than the relatively current value, generation is with two
The corresponding data values 1 of present bit n of binary data stream, when determining that the value of the electric current sum is less than or equal to the relatively current value,
Generation data value 0 corresponding with the present bit n of binary data stream.
9. structure according to claim 8, which is characterized in that the amendment low data unit, including：
N number of discharge network subelement；
Each discharge network subelement includes n discharge module in parallel, and the discharge module includes the nmos moulds of series connection
Block and earthing module；
It is located at each discharge network subelement in the output terminal of each sensitive current amplifier and each discharge network subelement
Discharge module in the value of digit n first input end connection, the output terminal of each sensitive current amplifier and with sensitive electricity
The second input terminal connection of each discharge module in the one-to-one discharge network subelement of stream amplifier；
Each discharge network subelement, for being outputed in discharge network subelement correspondingly sensitive current amplifier
With the present bit n of binary data stream during corresponding data value 1, the data value of present bit is not corrected and determines the institute after this
There is data invalid, determine to output in sensitive current amplifier correspondingly with discharge network subelement and binary data stream
Present bit when corresponding to the data value 0 of n, data value is not corrected, to generate first the 1 of binary data stream location information.
10. structure according to claim 9, which is characterized in that the structure further includes：Data compression unit；
The output terminal of each sensitive current amplifier and in the one-to-one discharge network subelement of sensitive current amplifier
Each discharge module the second input terminal connection after, connect with the input terminal of data compression unit；
The data compression unit, the data flow formed for each data value to the amendment low data unit output carry out
Compression generates before first the 1 of binary data stream 0 number information.
11. a kind of detection method of leading zero, which is characterized in that including：
Binary data stream is obtained, processing, the binary data stream after generation extension are extended to the binary data stream；
According to the binary data stream after extension, everybody corresponding data value with binary data stream, the data value are generated
Characterize binary data stream present bit and present bit before everybody on whether occur 1；
It pair is modified with everybody corresponding data value of binary data stream, generates first 1 position of binary data stream
Information.
12. according to the method for claim 11, which is characterized in that the binary data stream according to after extension, generation
With everybody corresponding data value of binary data stream, including：
By the value that the binary data stream after extension is electric current sum；
Current value is compared in generation；
After value, the comparison current value to the electric current sum are compared, generate every corresponding with binary data stream
Data value.
13. according to the method for claim 12, which is characterized in that current value is compared in the generation, including：
Generate reference current value；
Generate threshold current value；
To current value be compared according to the reference current value and threshold current value generation.
14. according to the method for claim 13, which is characterized in that the generation reference current value, including：
Using each second current source in preset N number of reference current generation submodule, binary data stream present bit n's
Data are closed when being 0 not generate electric current, are closed to generate when the data of binary number data flow present bit n are 1
Electric current, wherein, each reference current generation submodule includes the second current source and resistance, second current source and the electricity
One end connection of resistance.
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