CN101944009A - Device for processing quotient of divider in integrated circuit - Google Patents
Device for processing quotient of divider in integrated circuit Download PDFInfo
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- CN101944009A CN101944009A CN2009100887048A CN200910088704A CN101944009A CN 101944009 A CN101944009 A CN 101944009A CN 2009100887048 A CN2009100887048 A CN 2009100887048A CN 200910088704 A CN200910088704 A CN 200910088704A CN 101944009 A CN101944009 A CN 101944009A
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Abstract
The invention provides a device for processing a quotient of a divider in an integrated circuit. On the basis of the quotient and a remainder of the divider, values of the quotient and the remainder are further judged so as to realize round-off operation on the quotient of the divider to obtain the more accurate quotient of the divider.
Description
Technical field
The present invention relates to digital signal processing circuit in the integrated circuit, be specifically related to the treating apparatus of divider merchant in a kind of integrated circuit.
Background technology
In the design of integrated circuit, to some arithmetic logic, can use divider, at present, the mode of utilizing the divider computing to obtain discussing mainly contains following two kinds:
First kind, dividend and divisor are input to divider, the merchant that the divider computing is obtained is directly as the final merchant of divider;
Second kind, after the lowest order of dividend, expand a bit 0, the merchant who obtains is cut out lowest bit by the mode that rounds up.For example the dividend of divider is a, and bit wide is the m bit, and divisor is b, and bit wide is the n bit, discusss to be that q, bit wide are t, then a is carried out the bit wide expansion, obtains a1[m:0]=a[m-1:0], 1 ' b0}, and the bit wide that obtains discussing is t+1, i.e. q[t:0].By the mode that rounds up, finally obtain the merchant and be q1[t-1:0];
For first kind of mode,, than higher system, may influence the performance of system to performance requirement because the operation that merchant is not rounded up can make the precision of computing reduce; And for the second way, because the bit wide of dividend has been expanded a bit, make the bit wide of divider computing increase a bit, arithmetic element for this more complicated of divider, increase a bit and can significantly increase logical resource, thereby make chip area become big, and, can not obtain really rounding up accurately the result because the merchant of the t+1 position that obtains has been the data through cut position.
Based on above reason, adopt device of the present invention, can improve the precision of divider, and under the prerequisite that guarantees precision, use less logical resource.
Summary of the invention
The invention provides the symbol two's complement being arranged in the integrated circuit and not having the device that the merchant of symbol divider handles.Utilize this device, can realize the merchant of divider is handled with less logical resource.
The specific implementation method is as described below:
Device to the merchant of divider that the symbol two's complement is arranged in the integrated circuit handles comprises the absolute value comparing unit, not-carry decision unit, forward carry decision unit, negative sense carry decision unit, merchant's operation result output unit; Wherein:
The absolute value comparing unit is by judging the sign bit of remainder and divisor respectively, realize remainder absolute value and divisor signed magnitude arithmetic(al), and the absolute value of remainder and divisor compared, result indicative signal is relatively outputed to the not-carry decision unit respectively, forward carry decision unit and negative sense carry decision unit;
The not-carry decision unit is by to carrying out the judgement of maximum positive and minimum negative from the merchant of IP kernel divider, and in conjunction with the indicator signal from the output of absolute value comparing unit, output not-carry indicator signal is to merchant's operation result output unit;
Forward carry decision unit is judged the difference of the symbol of dividend and divisor, and the indicator signal of judging outputed to negative sense carry decision unit, and in conjunction with the output indicator signal of absolute value comparing unit, output forward carry indicator signal is to merchant's operation result output unit;
The function of negative sense carry decision unit is: according to judgement dividend and the indicator signal of divisor symbol difference and the output indicator signal of absolute value comparing unit from the forward decision unit, output negative sense carry indicator signal is to merchant's operation result output unit;
Merchant's operation result output unit is by to from the not-carry decision unit, and the indicator signal of forward carry decision unit and negative sense carry decision unit judges, and utilizes the merchant of the divider of input, the round up merchant of final divider of computing of output process.
The realization principle is as follows: whether the merchant who judges divider is maximum positive or the minimum negative that its bit wide can be represented, if then the merchant of divider is not carried out carry operation, with the merchant of the divider merchant as final divider; Otherwise, remainder absolute value and divisor absolute value are compared.If the remainder absolute value is less than half of divisor absolute value, then the merchant of divider is not carried out carry operation, with the merchant of divider merchant as final divider; If the remainder absolute value is then judged the symbol of dividend and divisor more than or equal to half of divisor absolute value.If dividend is with to remove numerical symbol inequality, then the merchant to divider carries out the negative sense carry, and the merchant who is about to divider subtracts 1 computing, otherwise, the merchant of divider is carried out the forward carry, the merchant who is about to divider adds 1 computing.
If divider merchant's most significant digit is 0, and except most significant digit all the other everybody be 1, then the merchant of divider is the maximum positive that its bit wide can be represented; If divider merchant's most significant digit is 1, and except most significant digit all the other everybody be 0, then the merchant of divider is the minimum negative that its bit wide can be represented.
A kind of method that remainder absolute value and divisor absolute value are compared is: judge the symbol of remainder and divisor at first respectively, if corresponding sign bit is 0, then with the value of corresponding remainder or divisor as its absolute value; If corresponding sign bit is 1, then with each first negate of corresponding remainder or divisor, add 1, thereby obtain corresponding remainder absolute value or divisor absolute value, fill a bit 0 (be equivalent to the remainder absolute value be multiply by 2) at the lowest order of remainder absolute value then, and this value and divisor absolute value compared, if this value is more than or equal to the divisor absolute value, show that then the remainder absolute value is more than or equal to half of divisor absolute value, otherwise, show that the remainder absolute value is less than half of divisor absolute value.
Judge whether dividend is identical with the symbol of divisor, if the most significant digit of dividend be 1 and the most significant digit of divisor be 0, or the most significant digit of dividend be 0 and the most significant digit of divisor be 1, the symbol that then shows dividend and divisor is inequality, if the most significant digit of dividend and divisor is 0 or be 1, the symbol that then shows dividend and divisor is identical, and this judgement can realize by the most significant digit of dividend and divisor is carried out xor operation.
Device to the merchant of no symbol divider in the integrated circuit handles comprises comparing unit, not-carry decision unit, merchant's operation result output unit.
Comparing unit outputs to the not-carry decision unit respectively, the carry decision unit by remainder and divisor are compared with result indicative signal relatively;
The not-carry decision unit is by to carrying out the judgement of maximum number from the merchant of IP kernel divider, and in conjunction with the indicator signal from comparing unit output, output not-carry indicator signal is to merchant's operation result output unit.
Merchant's operation result output unit is by to judging from the indicator signal of not-carry decision unit and comparing unit, and utilizes the merchant of the divider of input, and output is through the merchant of the final divider of the computing that rounds up.
The realization principle is as follows: whether the merchant who judges divider is the maximum number that its bit wide can be represented, if then the merchant of divider is not carried out carry operation, with the merchant of the divider merchant as final divider; Otherwise, remainder and divisor are compared: if remainder less than half of divisor, does not then carry out carry operation to the merchant of divider, with the merchant of divider merchant as final divider; If remainder is more than or equal to half of divisor, then the merchant to divider carries out carry, and the merchant who is about to divider adds 1 computing.
If everybody is 1 the divider merchant, then the merchant of divider is a maximum number.
A kind of method that remainder and divisor are compared is: fill a bit 0 (be equivalent to remainder be multiply by 2) at the lowest order of remainder, and this value and divisor compared, if this value is more than or equal to divisor, show that then remainder is more than or equal to half of divisor, otherwise, show that remainder is less than half of divisor.
Description of drawings
The device example structure synoptic diagram of Fig. 1 among the present invention the divider merchant that the symbol two's complement is arranged being handled.
Fig. 2 is the fundamental diagram of the device the divider merchant that the symbol two's complement is arranged handled among the present invention.
The device example structure synoptic diagram of Fig. 3 among the present invention no symbol divider merchant being handled
Fig. 4 is the fundamental diagram of the device no symbol divider merchant handled among the present invention.
Embodiment
Below in conjunction with accompanying drawing, specify the present invention.
The apparatus structure synoptic diagram of Fig. 1 among the present invention the divider merchant that the symbol two's complement is arranged being handled, as shown in Figure 1, wherein the absolute value comparing unit 101, not-carry decision unit 102, forward carry decision unit 103, negative sense carry decision unit 104, merchant's operation result output unit 105.Below in conjunction with specific embodiment, describe the calculating process of each unit in detail.
Suppose that dividend is a[5:0]=101110 (18), divisor is b[3:0]=0101 (5), then by the divider computing, obtain the merchant and be q[5:0]=111101 (3), remainder is rem[3:0]=1101 (3).The functional structure of each unit is described below:
Absolute value comparing unit 101: by judging the sign bit of remainder and divisor respectively, realize remainder absolute value and divisor signed magnitude arithmetic(al), and absolute value compared, result indicative signal is relatively outputed to not-carry decision unit 102 respectively, forward carry decision unit 103 and negative sense carry unit 104.
Described absolute value comparing unit 101 comprises first not gate, 1011, the second not gates 1012, first adder 1013, and second adder 1014, first selector 1015, second selector 1016 is more than or equal to comparer 1017.Be respectively described below:
First not gate 1011 carries out the operation of step-by-step negate to remainder, and the result is exported to first adder 1013, in this example, remainder step-by-step negate is obtained rem_rev[3:0]=0010 (2);
Second not gate 1012 carries out the operation of step-by-step negate to divisor, and the result is exported to second adder 1014, in this example, divisor step-by-step negate is obtained b_rev[3:0]=1010 (6);
More than or equal to comparer 1017, will be from the result of first selector 1015 with second selector 1016, compare, the gained comparative result is exported to not-carry decision unit 101, forward carry decision unit 102 and negative sense carry decision unit 103, in this example, promptly to rem_rev_add[3:0] and b[3:0] compare, at first with rem_rev_add[3:0] low level expands a bit 0, obtain rem_rev_add_ex[4:0]=00110 (6), then with this value and b[3:0] compare, obtain rem_rev_add_ex[4:0]＞b[3:0], thereby the result who obtains comparer is abs_comp=1.
Not-carry decision unit 102: by the merchant of divider is carried out the judgement of maximum positive and minimum negative, and in conjunction with the indicator signal from 101 outputs of absolute value comparing unit, output not-carry indicator signal is to merchant's operation result output unit 105.
Described not-carry decision unit 102 comprises first not gate, 1021, the second not gates 1022, with door 1023, rejection gate 1024, or door 1025.Be respectively described below:
First not gate 1021 carries out the negate computing to divider merchant's symbol, the result is exported to and door 1023 and rejection gate 1024, in this example, promptly to q[5]=1 carry out the negate computing, obtain q_rev[5]=0;
Second not gate 1022 carries out the negate computing to the output from the absolute value comparing unit, the result is exported to or door, in this example, is about to abs_comp and carries out the negate computing and obtain abs_comp_rev=0;
With door 1023, will be from the output result of first not gate 1021 and merchant's all except sign bit q[4:0 of divider] carry out one by one and operation, the gained result exports to or door 1024, in this example, be q_rev[5] and q[4:0] carry out one by one and operation, positive number maximal value indicator signal q_pos_max=0 obtained;
Or door 1025, to from second not gate 1022, result with door 1023 and rejection gate 1024, carry out or operation, the not-carry indicator signal that obtains is exported to merchant's operation result output unit, in this example, promptly utilize abs_comp_rev, three indicator signals of q_pos_max and q_neg_min are carried out or are operated, and finally obtain not-carry indicator signal no_carry=0.
Forward carry decision unit 103: the symbol of judging dividend and divisor, and the indicator signal of judging outputed to negative sense carry decision unit 104, and in conjunction with the output indicator signal of absolute value comparing unit 101, output forward carry indicator signal is to merchant's operation result output unit 105.
Described forward carry decision unit 103 comprises XOR gate 1031, and not gate 1032 is with door 1033.Be respectively described below:
Not gate 1032 carries out the operation of negate with the output result of XOR gate 1031, and the gained result exports to and door 1033, in this example, promptly ab_sign_diff is carried out inversion operation, obtains ab_sign_diff_rev=0;
With door 1033, the output of the output of absolute value comparing unit 101 and not gate 1032 is in the future carried out and operation, gained forward carry indicator signal is exported to merchant's operation result output unit 105, in this example, promptly abs_comp and ab_sign_diff_rev are carried out and operation, obtain forward carry indicator signal pos_carry=0.
Negative sense carry decision unit 104: according to the output signal from forward decision unit 103, with the output indicator signal of absolute value comparing unit 101, output negative sense carry indicator signal is to merchant's operation result output unit.
Described negative sense carry decision unit 104 is and door.Will be from the output of absolute value comparing unit, carry out with the output of XOR gate in the forward carry decision unit 103 or operate, gained negative sense carry indicator signal is exported to merchant's operation result output unit, in this example, promptly abs_comp and ab_sign_diff are carried out and computing, obtain negative sense carry indicator signal neg_carry=1.
Merchant's operation result output unit 105: by to from not-carry decision unit 102, forward carry decision unit 103 is judged with the indicator signal of negative sense carry decision unit 104, and utilizing the divider merchant who imports, output is through the merchant of the final divider of the computing that rounds up.
Described merchant's operation result output unit comprises first selector 1051, totalizer 1052, second selector 1053.Be respectively described below:
First selector 1051: with the output indicator signal of forward carry decision unit 103 and negative sense carry decision unit 104 as selecting signal, selectivity constant 1,-1 or 0 output to totalizer (if forward carry decision unit 103 output indicator signals be 1 and the output indicator signal of negative sense carry decision unit 104 be 0, then select 1, if the output indicator signal of negative sense carry decision unit 104 be 1 and forward carry decision unit 103 output indicator signals be 0, then select-1, other situations select 0), in this example, promptly utilize pos_carry, neg_carry can determine that as selecting signal selector switch is output as-1;
Totalizer 1052: sum operation is carried out in the output of first selector 1051 and the merchant of divider, and the gained result exports to second selector 1053, in this example, promptly to q[5:0]=111101 (3) add-1, obtain q_carry[5:0]=111100 (4);
Second selector 1053: to output result from totalizer 1052, merchant with divider, select by indicator signal from not-carry decision unit 102, the merchant who obtains final divider is (if the not-carry decision unit is output as 1, then select the merchant of the merchant of divider as final divider, otherwise, select the merchant of the result of totalizer) as final divider, in this example, promptly utilize the no_carry signal to q_carry[5:0] and q[5:0] select, because the no_carry signal is 0, so select q_carry[5:0] as the merchant of final divider, promptly final is q_round[5:0 through the divider merchant after the computing that rounds up]=q_carry[5:0];
Fig. 2 has provided the fundamental diagram of among the present invention the divider merchant that the symbol two's complement is arranged being handled, and as shown in Figure 2, may further comprise the steps:
Step 201 judges whether the merchant of divider is maximum positive or the minimum negative that its bit wide can be represented, if then execution in step 202, otherwise, execution in step 203.
In this step, if divider merchant's most significant digit is 0, and except most significant digit all the other everybody be 1, then the merchant of divider is the maximum positive that its bit wide can be represented; If divider merchant's most significant digit is 1, and except most significant digit all the other everybody be 0, then the merchant of divider is the maximum negative that its bit wide can be represented.For example, 1000 (8) are the 4 minimum negatives that can represent than peculiar symbol scale-of-two, and 0111 (7) is 4 maximum positive that can represent than peculiar symbol scale-of-two.
Step 202, the merchant to divider does not carry out carry operation, with the merchant of the divider merchant as final divider;
Step 203 compares remainder absolute value and divisor absolute value: if the remainder absolute value less than half of divisor absolute value, then execution in step 204, otherwise, execution in step 205.
In this step, the method that remainder absolute value and divisor absolute value are compared is: judge the symbol of remainder and divisor at first respectively, if corresponding sign bit is 0, then with the value of corresponding remainder or divisor as its absolute value; If corresponding sign bit is 1, then, adds 1, thereby obtain corresponding remainder absolute value or divisor absolute value each first negate of corresponding remainder or divisor.Fill a bit 0 (be equivalent to the remainder absolute value be multiply by 2) at the lowest order of remainder absolute value then, and this value and divisor absolute value compared, if this value is more than or equal to the divisor absolute value, show that then the remainder absolute value is more than or equal to half of divisor absolute value, otherwise, show that the remainder absolute value is less than half of divisor absolute value.For example, if divisor is 10101 (11), remainder is 00101 (5), then at first divisor and remainder are become its absolute value, be respectively 01011 (11) and 00101 (5), then the remainder lowest order is mended 0, obtain 001010 (10), with this number and divisor absolute value 01011 relatively, obtain this number, thereby show that the remainder absolute value is less than half of divisor absolute value less than the divisor absolute value.
Step 204, the merchant to divider does not carry out carry operation, with the merchant of the divider merchant as final divider;
Step 205, the symbol of dividend and divisor is judged: if dividend and inequality except that numerical symbol, then execution in step 206, otherwise execution in step 205.
In this step, judge whether dividend is identical with the symbol of divisor, the most significant digit that is about to dividend and divisor is judged, if the most significant digit of dividend be 1 and the most significant digit of divisor be 0, or the most significant digit of dividend be 0 and the most significant digit of divisor be 1, the symbol that then shows dividend and divisor is inequality, if the most significant digit of dividend and divisor is 0 or be 1, the symbol that then shows dividend and divisor is identical, and inferior judgement can realize by the most significant digit of dividend and divisor is carried out XOR.
Step 206 is carried out the negative sense carry to the merchant of divider, and the merchant who is about to divider subtracts 1 computing.For example the merchant of divider is 10110 (10), subtracts 1 computing and obtains the merchant of 10101 (11) as final divider later on.
Step 207 is carried out the forward carry to the merchant of divider, and the merchant who is about to divider adds 1 computing.For example the merchant of divider is 01010 (10), carries out add-one operation and obtains 01011 (11) merchant as final divider later on.
Fig. 3 as shown in Figure 3, comprises comparing unit 301 for the structural representation of the device no symbol divider merchant handled among the present invention, and not-carry decision unit 302 is discussed operation result output unit 303.Below in conjunction with an example, describe the calculating process of each unit in detail.
Suppose that dividend is a_uns[5:0]=101110 (46), divisor is b_uns[2:0]=110 (6), then by the computing of IP kernel divider, obtain the merchant and be q_uns[5:0]=000111 (7), remainder is rem_uns[2:0]=100 (4).The functional structure of each unit is described below:
Comparing unit 301: by remainder and divisor are compared, result indicative signal is relatively outputed to not-carry decision unit 302 respectively, merchant's operation result output unit 303.
Described comparing unit 301 is more than or equal to comparer.Remainder and divisor are compared, the gained comparative result is exported to not-carry decision unit and merchant's operation result output unit, in this example, promptly to rem_uns[2:0]=100 (4) and b_uns[2:0]=110 (6) compare, at first with rem_uns[2:0] low level expands a bit 0, obtain rem_uns_ex[3:0]=1000 (8), then with this value and b_uns[2:0] compare, obtain rem_uns_ex[3:0]＞b_uns[2:0], thereby the result who obtains comparer is comp_uns=1.
Not-carry decision unit 302: by the merchant of divider is carried out the judgement of maximum number, and in conjunction with the indicator signal of coming comparing unit 301 outputs, output not-carry indicator signal is to merchant's operation result output unit 303.
Described not-carry decision unit 302 comprises not gate 3021, with door 3022 and or door 3023.Be respectively described below:
Not gate 3021 carries out the negate computing to the output from comparing unit, the result is exported to or door 3023, in this example, promptly comp_uns is carried out the negate computing, and the result who obtains negate is comp_uns_rev=0;
With door 3022, all positions of the merchant of divider are carried out and operation one by one, the gained result exports to or door 3023, in this example, promptly to q_uns[5:0] institute is promising carries out and operation, obtains final and q_uns_max=0 as a result;
Or door 3023, to from not gate 3021 and with the result of door 3022, carry out or operation, the not-carry indicator signal that obtains is exported to merchant's operation result output unit 303, in this example, promptly comp_uns_rev and q_uns_max are carried out or operate, obtain not-carry indicator signal no_carry_uns=0.
Merchant's operation result output unit 303: by to judging from the indicator signal of not-carry decision unit 302 and comparing unit 301, and utilize the divider merchant of input, output is through the merchant of the final divider of the computing that rounds up.
Described merchant's operation result output unit 303 comprises totalizer 3031 and selector switch 3032.Be respectively described below:
Totalizer 3031: will carry out sum operation from the output of comparing unit 301 and the merchant of IP kernel divider, the gained result exports to selector switch 3032, in this example, promptly to q_uns[5:0] carry out the computing of addition with comp_uns, obtain the value q_add_uns[5:0 after the addition]=001000 (8);
Selector switch 3032: to output result from totalizer 3031, merchant with divider, select by indicator signal from not-carry decision unit 302, the merchant who obtains final divider is (if the indicator signal of not-carry decision unit 302 is 1, select the merchant of the merchant of divider as final divider, otherwise, select the merchant of the output result of totalizer 3031) as final divider, in this example, because the indicator signal no_carry_uns=0 of not-carry decision unit 302, so select the merchant of the output result of totalizer 3031 as final divider.
The fundamental diagram of Fig. 4 among the present invention no symbol divider merchant being handled as shown in Figure 4, may further comprise the steps:
Step 401 judges whether the merchant of divider is the maximum number that its bit wide can be represented, if then execution in step 402, otherwise execution in step 403.
In this step, if the divider merchant everybody be 1, then the merchant of divider is the maximum number that its bit wide can be represented.For example, 1111 (15) is that 4 bits do not have the maximum number that the symbol scale-of-two can be represented.
Step 403 compares half of remainder and divisor: if remainder less than half of divisor, then execution in step 403, otherwise execution in step 405.
In this step, with half method that compares of remainder and divisor be: head is minimum for filling a bit 0 remainder, be about to remainder and multiply by 2, and this value and divisor compared, if this value is more than or equal to divisor, then show remainder more than or equal to half of divisor, otherwise, show that remainder is less than half of divisor.For example, if divisor is 1011 (11), remainder is 110 (6), at first the remainder lowest order is mended 0, obtains 1100 (12), with this number and divisor comparison, obtains this number greater than divisor, shows that the remainder absolute value is greater than half of divisor absolute value.
Step 404, the merchant to divider does not carry out carry operation, with the merchant of the divider merchant as final divider;
Step 405 is carried out carry to the merchant of divider, and the merchant who is about to divider adds 1 computing.For example the merchant of divider is 1010 (10), carries out add-one operation and obtains 1011 (11) merchants as final divider later on.
What more than provide is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. the device of in the integrated circuit merchant of divider that the symbol two's complement is arranged being handled is characterized in that, comprises the absolute value comparing unit, the not-carry decision unit, forward carry decision unit, negative sense carry decision unit, merchant's operation result output unit; Wherein:
The absolute value comparing unit is by judging the sign bit of remainder and divisor respectively, realize remainder absolute value and divisor signed magnitude arithmetic(al), and the absolute value of remainder and divisor compared, result indicative signal is relatively outputed to the not-carry decision unit respectively, forward carry decision unit and negative sense carry decision unit;
The not-carry decision unit is by to carrying out the judgement of maximum positive and minimum negative from the merchant of IP kernel divider, and in conjunction with the indicator signal from the output of absolute value comparing unit, output not-carry indicator signal is to merchant's operation result output unit;
Forward carry decision unit is judged the difference of the symbol of dividend and divisor, and the indicator signal of judging outputed to negative sense carry decision unit, and in conjunction with the output indicator signal of absolute value comparing unit, output forward carry indicator signal is to merchant's operation result output unit;
The function of negative sense carry decision unit is: according to judgement dividend and the indicator signal of divisor symbol difference and the output indicator signal of absolute value comparing unit from the forward decision unit, output negative sense carry indicator signal is to merchant's operation result output unit;
Merchant's operation result output unit is by to from the not-carry decision unit, and the indicator signal of forward carry decision unit and negative sense carry decision unit judges, and utilizes the merchant of the divider of input, the round up merchant of final divider of computing of output process.
2. the device of in the integrated circuit merchant of no symbol divider being handled is characterized in that, comprises comparing unit, not-carry decision unit, merchant's operation result output unit.
Comparing unit outputs to the not-carry decision unit respectively, the carry decision unit by remainder and divisor are compared with result indicative signal relatively;
The not-carry decision unit is by to carrying out the judgement of maximum number from the merchant of IP kernel divider, and in conjunction with the indicator signal from comparing unit output, output not-carry indicator signal is to merchant's operation result output unit.
Merchant's operation result output unit is by to judging from the indicator signal of not-carry decision unit and comparing unit, and utilizes the merchant of the divider of input, and output is through the merchant of the final divider of the computing that rounds up.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105302769A (en) * | 2015-10-28 | 2016-02-03 | 天津大学 | Configuration method for realizing high-precision division in universal reconfigurable processor |
| CN108334306A (en) * | 2017-01-19 | 2018-07-27 | 想象技术有限公司 | Formal verification to the IC Hardware design for realizing division of integer |
| CN112578843A (en) * | 2019-09-29 | 2021-03-30 | 圣邦微电子（北京）股份有限公司 | Voltage trimming method and system based on integrated circuit |
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| KR0158647B1 (en) * | 1995-05-22 | 1998-12-15 | 윤종용 | Multiplier using both signed number and unsigned number |
| CN100543666C (en) * | 2006-09-18 | 2009-09-23 | 华为技术有限公司 | The method of a kind of fixed-point divider and realization computing thereof |
| CN101295237B (en) * | 2007-04-25 | 2012-03-21 | 四川虹微技术有限公司 | High-speed divider for quotient and balance |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105302769A (en) * | 2015-10-28 | 2016-02-03 | 天津大学 | Configuration method for realizing high-precision division in universal reconfigurable processor |
| CN108334306A (en) * | 2017-01-19 | 2018-07-27 | 想象技术有限公司 | Formal verification to the IC Hardware design for realizing division of integer |
| CN108334306B (en) * | 2017-01-19 | 2023-07-14 | 想象技术有限公司 | Method, system and medium for verifying hardware design for realizing integer divider |
| CN112578843A (en) * | 2019-09-29 | 2021-03-30 | 圣邦微电子（北京）股份有限公司 | Voltage trimming method and system based on integrated circuit |
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