CN108235352A - A kind of data monitoring method and device - Google Patents
A kind of data monitoring method and device Download PDFInfo
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- CN108235352A CN108235352A CN201810005520.XA CN201810005520A CN108235352A CN 108235352 A CN108235352 A CN 108235352A CN 201810005520 A CN201810005520 A CN 201810005520A CN 108235352 A CN108235352 A CN 108235352A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/04—Arrangements for maintaining operational condition
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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Abstract
The present invention provides a kind of data monitoring method and device,In the case where detecting that CCU systems need to load configuration data,By the CPLD of CCU systems by the configuration data that need to be loaded with the corresponding sequential export of the external universal asynchronous receiving-transmitting transmitter of CCU systems to its external universal asynchronous receiving-transmitting transmitter,And detecting the completion configuration data loading of CCU systems,And after the CPU of CCU systems initializes the external universal asynchronous receiving-transmitting transmitters of CPU,The startup running log for recording the startup operational process for having CPU is exported to universal asynchronous receiving-transmitting transmitter external CCU,Realize the time division multiplexing of the universal asynchronous receiving-transmitting transmitter external to CCU,And pass through output to universal asynchronous receiving-transmitting transmitter data external CCU,It is monitored such as configuration data and startup running log can start operational process to data loading and CPU,Realize the positioning to problem in start-up loading flow,So as to reduce research and development and debugging difficulty.
Description
Technical field
The invention belongs to data communication technology field, more specifically more particularly to a kind of data monitoring method and device.
Background technology
The base station (abbreviation LTE base station) under LTE (Long Term Evolution, long term evolution) network is at least wrapped at present
BBU (Base band Unit, Base Band Unit) and RRU (Radio Remote Unit, Remote Radio Unit) are included, wherein BBU is born
The processing of uplink baseband signal and downgoing baseband signal is blamed, and provides physical interface with by physical interface and RRU and other nets
Network completes information exchange, and RRU is communicated by physical interface with BBU, completes the conversion of baseband signal and radiofrequency signal.
For BBU, system clock and same can be provided for LTE base station by CCU (master clock plate) systems in BBU
Walk signal and be responsible for OAM (Operation Administration and Maintenance, Operations,Administration And Maintenance) and
RRC (Radio Resource Control, wireless heterogeneous networks), wherein CCU systems include：CPU(Central
Processing Unit, central processing unit), FPGA (Field Programmable Gate Array, field-programmable gate array
Row) and CPLD (ComplexProgrammable Logic Device, Complex Programmable Logic Devices) etc., by CPU and CPLD
It is responsible for OAM and RRC controls, is responsible for providing system clock and synchronizing signal by FPGA.
A storage unit can also be integrated in CCU systems, BOOT files is read from the storage unit and FPGA matches
Put data, but the prior art lacks certain flows in CCU system start-up loading flows is easily monitored, such as above-mentioned hardware is matched
The monitoring of word loading procedure is put, is difficult that rapidly the problem is determined in this way if hardware configuration word loading procedure goes wrong
Position, increases research and development and debugging difficulty.
Invention content
In view of this, the purpose of the present invention is to provide a kind of data monitoring method and device, for matching to CCU systems
The startup operational process for putting data loading and the CPU in CCU systems is monitored, and is realized to the problems in start-up loading flow
Positioning so as to reduce research and development and debugging difficulty, while realizes that the time-division of the universal asynchronous receiving-transmitting transmitter external to CCU systems answers
With.Technical solution is as follows：
The present invention provides a kind of data monitoring method, applied in master clock plate system, the method includes：
In the case where detecting that master clock plate system need to load configuration data, pass through the master clock plate system
Complex Programmable Logic Devices passes the configuration data that need to be loaded with the external universal asynchronous receiving-transmitting of the master clock plate system
The corresponding sequential export of defeated device is to the external universal asynchronous receiving-transmitting transmitter of master clock plate system；
In the central processing for detecting the completion configuration data loading of master clock plate system and the master clock plate system
After device completes the external universal asynchronous receiving-transmitting transmitter initialization of central processing unit, being controlled by Complex Programmable Logic Devices will
The startup running log that record has the startup operational process of the central processing unit, which is exported to master clock plate system is external, to be led to
Use asynchronous receiving-transmitting transmitter.
Preferably, it is described in the case where detecting that master clock plate system need to load configuration data, pass through the master control
The Complex Programmable Logic Devices of clock board system leads to the configuration data that need to be loaded so that the master clock plate system is external
Included with the corresponding sequential export of asynchronous receiving-transmitting transmitter to the external universal asynchronous receiving-transmitting transmitter of master clock plate system：
In the case where the central processing unit for detecting the master clock plate system need to load hardware configuration word, pass through institute
Complex Programmable Logic Devices is stated to pass the hardware configuration word with the external universal asynchronous receiving-transmitting of the master clock plate system
The corresponding sequential export of defeated device is to the external universal asynchronous receiving-transmitting transmitter of master clock plate system；
Detecting that the driving communicated with the Complex Programmable Logic Devices needs loading field programmable gate array to match
In the case of putting data, by the Complex Programmable Logic Devices by the field programmable gate array configuration data with master control
The corresponding sequential export of the external universal asynchronous receiving-transmitting transmitter of clock board system is to external general different of master clock plate system
Walk receiving-transmitting transmitter.
Preferably, the situation that hardware configuration word need to be loaded in the central processing unit for detecting master clock plate system
Under, by the Complex Programmable Logic Devices by the hardware configuration word with external general different of the master clock plate system
The corresponding sequential export of step receiving-transmitting transmitter to the external universal asynchronous receiving-transmitting transmitter of master clock plate system includes：
In the case where detecting that the central processing unit need to load hardware configuration word, according to the master clock plate system
Form required by the corresponding sequential of external universal asynchronous receiving-transmitting transmitter, is often received by the Complex Programmable Logic Devices
When the hardware configuration word of the preset quantity then being encapsulated as universal asynchronous receiving-transmitting transmitter to the hardware configuration word of preset quantity
Ordinal number evidence, and the universal asynchronous receiving-transmitting transmitter time series data is exported to the external universal asynchronous receiving-transmitting of master clock plate system
Transmitter.
Preferably, it is described to detect that the driving communicated with the Complex Programmable Logic Devices needs loading field that compile
In the case of journey gate array configuration data, the field programmable gate array is configured by the Complex Programmable Logic Devices
Data with the external corresponding sequential export of universal asynchronous receiving-transmitting transmitter to master clock plate system of master clock plate system outside
The universal asynchronous receiving-transmitting transmitter connect includes：
It, can by the complexity in the case where detecting that the driving needs loading field programmable gate array configuration data
Programmed logic device obtains the field programmable gate array configuration data of parallel transmission in the bus being connected with the driving, and root
According to form required by the external corresponding sequential of universal asynchronous receiving-transmitting transmitter of the master clock plate system, present count is often obtained
After the field programmable gate array configuration data of amount, the field programmable gate array configuration data of the preset quantity is encapsulated as
Universal asynchronous receiving-transmitting transmitter time series data exports the universal asynchronous receiving-transmitting transmitter time series data to master clock plate system
It unites external universal asynchronous receiving-transmitting transmitter.
Preferably, the method further includes：In the case where receiving preset data, determine that the driving needs loading field
Programmable gate array configuration data.
The present invention also provides a kind of data monitoring devices, and applied in master clock plate system, described device includes：
First control unit, in the case where detecting that master clock plate system need to load configuration data, passing through institute
State the Complex Programmable Logic Devices of master clock plate system by the configuration data that need to be loaded with the master clock plate system outside
The corresponding sequential export of universal asynchronous receiving-transmitting transmitter connect is to the external universal asynchronous receiving-transmitting transmitter of master clock plate system；
Second control unit, for when detecting that master clock plate system completes configuration data loading and the master control
It, can by complexity after the central processing unit of clock plate system completes the external universal asynchronous receiving-transmitting transmitter initialization of central processing unit
Programmed logic device control exports the startup running log for recording the startup operational process for having the central processing unit to master control
The external universal asynchronous receiving-transmitting transmitter of clock board system.
Preferably, first control unit, specifically in the central processing for detecting the master clock plate system
In the case that device need to load hardware configuration word, by the Complex Programmable Logic Devices by the hardware configuration word with the master
The external corresponding sequential export of universal asynchronous receiving-transmitting transmitter of clock board system is controlled to external general of master clock plate system
Asynchronous receiving-transmitting transmitter；
And specifically for detecting that the driving communicated with the Complex Programmable Logic Devices needs loading field can
In the case of programming gate array configuration data, the field programmable gate array is matched by the Complex Programmable Logic Devices
Data are put with the external corresponding sequential export of universal asynchronous receiving-transmitting transmitter of master clock plate system to master clock plate system
External universal asynchronous receiving-transmitting transmitter.
Preferably, first control unit, specifically for detecting that the central processing unit need to load hardware configuration
In the case of word, according to lattice required by the external corresponding sequential of universal asynchronous receiving-transmitting transmitter of the master clock plate system
Formula often receives the hardware configuration word of preset quantity then by the hard of the preset quantity by the Complex Programmable Logic Devices
Part configuration words are encapsulated as universal asynchronous receiving-transmitting transmitter time series data, and the universal asynchronous receiving-transmitting transmitter time series data is exported
The universal asynchronous receiving-transmitting transmitter external to master clock plate system.
Preferably, first control unit, specifically for detect it is described driving need loading field programmable gate array
In the case of row configuration data, obtained by the Complex Programmable Logic Devices and passed parallel in the bus being connected with described drive
Defeated field programmable gate array configuration data, and according to the external universal asynchronous receiving-transmitting transmitter of the master clock plate system
Form required by corresponding sequential, often after the field programmable gate array configuration data of acquisition preset quantity, by the present count
The field programmable gate array configuration data of amount is encapsulated as universal asynchronous receiving-transmitting transmitter time series data, by the universal asynchronous receipts
Hair transmitter time series data is exported to the external universal asynchronous receiving-transmitting transmitter of master clock plate system.
The present invention also provides a kind of storage medium, computer program stream, the computer are stored on the storage medium
Program flow, which is performed, realizes above-mentioned data monitoring method.
From above-mentioned technical proposal it is found that in the case where detecting that CCU systems need to load configuration data, pass through CCU systems
CPLD by the configuration data that need to be loaded (such as hardware configuration word and FPGA configuration data) with external universal asynchronous of CCU systems
The corresponding sequential export of receiving-transmitting transmitter is detecting that CCU systems are complete to the external universal asynchronous receiving-transmitting transmitter of CCU systems
After the universal asynchronous receiving-transmitting transmitter initialization external into the CPU completions CPU of configuration data loading and CCU systems, pass through CPLD
The startup running log for recording the startup operational process for having CPU is exported to the external universal asynchronous receiving-transmitting of CCU systems and passed by control
Defeated device realizes the time division multiplexing of the universal asynchronous receiving-transmitting transmitter external to CCU systems, and external to CCU systems by exporting
Universal asynchronous receiving-transmitting transmitter data, such as configuration data and start running log can to data load and CPU startup transport
Row process is monitored, and realizes the positioning to the problems in start-up loading flow, so as to reduce research and development and debugging difficulty.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments, for those of ordinary skill in the art, without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is the flow chart of data monitoring method provided in an embodiment of the present invention；
Fig. 2 is the structure diagram of data monitoring device provided in an embodiment of the present invention.
Specific embodiment
Existing CCU systems lack carries out convenient monitoring comprehensively to certain flows in CCU system start-up loading flows, so as to
Increase research and development and debugging difficulty.To solve this problem, the CCU corresponding to data monitoring method and device provided in this embodiment
System includes at least：CPLD and CPU, and an external UART (the Universal Asynchronous Receiver/ of CCU systems
Transmitter, universal asynchronous receiving-transmitting transmitter).
Wherein CPLD is included at least：Sequential conversion module and URAT alternative modules, sequential conversion module are used for basis
Form required by the corresponding sequential of UART is encapsulated data as UART time series datas, and UART alternatives module then needs for choosing
Output in this way exports the packaged data of sequential conversion module to UART still to the data in the external UART of CCU systems
The startup exported with UART external CPU is run into relevant data, is exported as started running log to CCU systems external
Which kind of data output UART, wherein UART alternatives module, which choose, is determined by CPLD, as can be flowed according to residing for CCU systems
Cheng Erding, is such as in configuration data loading flow in CCU systems, and control UART alternatives module chooses the encapsulation of sequential conversion module
Good data, after the UART initialization for being in that configuration data loading is completed and the CPU of CCU systems completions CPU is external in CCU systems
Flow in, the startup that control UART alternatives module chooses the UART output external with CPU runs relevant data, such as starts
Running log is realized the time division multiplexing of UART external to CCU systems with this, and the data in CCU systems can be loaded (as firmly
The loading of part configuration words and FPGA configuration data) and the startup operational process of CPU be monitored, be easy to implement to start-up loading
Thus the positioning of the problems in flow reduces research and development and debugging difficulty.
For above-mentioned CCU systems, the thought of data monitoring method provided in an embodiment of the present invention is：Detecting CCU systems
It is by the CPLD of CCU systems that the configuration data that need to be loaded is external with CCU systems in the case that system need to load configuration data
The corresponding sequential exports of UART are to the external UART of CCU systems；
The external UART initialization of CPU is completed in the CPU for detecting the completion configuration data loading of CCU systems and CCU systems
Afterwards, the startup running log for recording the startup operational process for having the CPU is exported by CPLD controls external to CCU systems
UART。
Hardware configuration word and FPGA configuration data are included with configuration data below, are with the start-up loading flow of CCU systems：
For loading hardware configuration word, CPU start-up operations system, loading FPGA configuration data and CPU operations, and combine the present invention and implement
Attached drawing in example, is clearly and completely described the technical solution in the embodiment of the present invention, it is clear that described embodiment
It is part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
Member's all other embodiments obtained without making creative work, shall fall within the protection scope of the present invention.
Referring to Fig. 1, it illustrates a kind of flow chart of data monitoring method provided in an embodiment of the present invention, for pair
The start-up loading flow of CCU systems is such as monitored the startup operational process of data loading and CPU, realizes to start-up loading
The positioning of the problems in flow, data monitoring method shown in specific Fig. 1 may comprise steps of：
101：In the case where the CPU for detecting CCU systems need to load hardware configuration word, hardware configuration word is loaded in CPU
During, it is by CPLD that hardware configuration word is external to CCU systems with the corresponding sequential exports of the external UART of CCU systems
UART。
In the present embodiment, by CPLD by hardware configuration word with the sequential export of the external UART of CCU systems to CCU systems
The feasible pattern of external UART of uniting is：It is external according to CCU systems in the case where detecting that CPU need to load hardware configuration word
The corresponding sequential of UART required by form, often receive the hardware configuration word of preset quantity then by the hardware configuration of preset quantity
Word is encapsulated as UART time series datas, and UART time series datas are exported to the external UART of CCU systems, realizes hard in CPU loadings
Simultaneously according to the sequential export hardware configuration word of UART to the external UART of CCU systems during part configuration words.
Wherein CPU is in the complete BOOT data of CCU system loads and loads hardware configuration word after the power is turned on again, and CPU needs to load
Hardware configuration word by CPU by CPLD from storage device, as read hardware configuration word in external norflash, CPLD is being read
When getting hardware configuration word, two step parallel processings are done respectively：The first step is to export hardware configuration word to CPU；Second step is：It will
Hardware configuration word caches and is encapsulated as UART time series datas and exports to UART the pins external CCU being connected with CPLD, second step
Process it is as follows：
The hardware configuration data that CPU is read out of storage device is cached the RAM (Random- to CPLD by CPLD
Access Memory, random access memory) in, such as CPU can by CPLD to storage device send chip selection signal and
Read signal, certain amount can be read from storage device by often sending a chip selection signal and a read signal, such as 16 data,
After CPU has sent defined chip selection signal and read signal by CPLD, show that CPU reads all hardware configuration datas, this
When all hardware configuration datas are cached in RAM to CPLD.By taking CPU is the CPU of T4240 types as an example, CPU needs
All hardware configuration datas can be read from storage device by sending 36 chip selection signals and 36 read signals by CPLD,
And often one chip selection signal of transmission and read signal can then read the hardware configuration word of 16, therefore sending 36 chip selection signals
With 36 read signals, then all hardware configuration words can be read from storage device, the hardware configuration word such as read includes 64
Bit flag position and 512 hardware configuration datas, wherein hardware configuration data are used to that Serdes PLL (Serializer- to be configured
Deserializer Phase Locked Loop), clock and pin multiplexing etc..
For CPLD, CPLD after the power is turned on, if CPLD monitor chip selection signal and read signal and meanwhile for 0 when, CPLD
In counter start counting up, be added in counter and show that CPU has sent the chip selection signal of specified quantity and the number of read signal
Value stops counting, will be write from storage device, such as data read in norflash external CPU when being added to 36 such as counter
Enter in the RAM opened up inside CPLD, determined by the digit of hardware configuration word when data being written in the RAM of CPLD, such as read
Hardware configuration word in the case of above-mentioned 64 bit flag position and 512 hardware configuration datas, to be write when entering data to RAM write
Data bit width is 16bits, and the address that the data of RAM are written is followed successively by 0,1 ..., 35, the hardware read when being written to address 35 is matched
It puts data to be all written in RAM, generates the indication signal for writing RAM completions at this time.
And the form of UART time series datas can be：One frame UART time series datas include：Start bit, data bit, check bit
And stop bits, for example the digit of the data bit of a frame UART time series datas is 8, and 8 data bit are followed successively by：Bit0、Bit1、
Bit2, Bit3, Bit4, Bit5, Bit6 and Bit7.Monitor generate write RAM complete in the case of, then CPLD can successively from
The hardware configuration word of preset quantity as defined in UART time series datas is read in the hardware configuration word of the RAM cachings of CPLD, and every time
The hardware configuration word non-overlapping copies of reading such as read 8 hardware configuration words, and the 8 hardware configuration words read every time are mutual every time
It is not overlapped, for the hardware configuration word arbitrarily once read, the hardware of the secondary reading is encapsulated according to the form of UART time series datas
Configuration words obtain UART time series datas, and UART time series datas are exported to UART the pins external CCU being connected with CPLD,
Thus it exports into the external UART of CCU systems, so as to record the hardware configuration word of CPU loadings, convenient for hardware configuration word
Loading procedure is monitored.
Still by it is above-mentioned including the hardware configuration word of 64 bit flag positions and 512 hardware configuration datas for, when monitoring to write
RAM (read operation bit wide is 1Bit, and the useful data deposited inside ram is 576Bits, that is, reads address from 0,1..., 576-1) is completed
Indication signal after, the form according to required by the sequential of UART, the 1st frame：Serially addition start bit is (real by CPLD programs successively
Now), it is 2 to read address in the data Bit 1 that address is 1 in the data Bit 0 that address is 0 in RAM, reading RAM, reading RAM
Data Bit 2, read RAM in address be 3 data Bit 3, read RAM in address be 4 data Bit 4, read RAM in
Data Bit 5 that address is 5, address is 6 in RAM data Bit 6 is read, address is 7 in RAM data Bit 7 is read, adds
Add check bit (being realized by CPLD programs), addition stop bits (being realized by CPLD programs), so far encapsulate first frame UART data
And it sends.According to this timing, until running through the data of the address 576-1 in RAM, and check bit and end are added
Position, i.e. 576/8=72 frames are simultaneously sent.
102：The external UART of CPU are completed in the CPU for detecting the completion hardware configuration word loading of CCU systems and CCU systems
After initialization, the startup running log for the startup operational process that record is had CPU is controlled to export by CPLD external to CCU systems
UART, so as to be monitored by the startup running log of output to the startup operational process of CPU.
103：In the case where detecting that the driving communicated with CPLD need to load FPGA configuration data, in drive load
During FPGA configuration data, by CPLD by FPGA configuration data with the corresponding sequential exports of the external UART of CCU systems
The UART external to CCU systems.
For FPGA configuration data, by CPLD by FPGA configuration data with the sequential export of UART to UART can
Line mode is：In the case where detecting that driving need to load FPGA configuration data, obtain and passed parallel in the bus being connected with driving
Defeated FPGA configuration data can be such as obtained with driving parallel transmission in the localbus buses being connected (or being cpu bus)
FPGA configuration data, wherein CPLD obtain FPGA configuration data process see the prior art, to this present embodiment no longer
It illustrates.
For the FPGA data of acquisition, handled in two steps in CPLD：One step outputs it FPGA configuration pins, to carry out
FPGA configuration data loads；Another step is encapsulated as UART time series datas, and is exported external to the CCU being connected with CPLD
UART pins.Wherein being encapsulated as the process of UART time series datas is：
The FPGA configuration data of preset quantity is often obtained according to form required by the corresponding sequential of the external UART of CCU systems
Afterwards, the FPGA configuration data of preset quantity is encapsulated as UART time series datas, UART time series datas is exported external to CCU
UART, realize during drive load FPGA configuration data simultaneously according to the sequential export FPGA configuration data of UART extremely
UART external CCU.
The form of UART time series datas can be in the present embodiment：One frame UART time series datas include：Start bit, data
The data bit digit of position, check bit sum stop bits, such as a frame UART time series datas is 8, and 8 data bit are followed successively by：Bit0、
Bit1, Bit2, Bit3, Bit4, Bit5, Bit6 and Bit7 are then got parallel in bus (such as localbus buses) in CPLD
After the FPGA configuration data (such as above-mentioned 8 configuration datas) of the preset quantity of transmission, the FPGA configuration data of preset quantity is turned
Serial data (data in a frame UART data can be encapsulated in) is changed to, it then will according to the form of above-mentioned UART time series datas
It seeks the serial data after encapsulation transition, and the serial data after encapsulation is exported by its pin external to coupled CCU
UART pins.
Feasible pattern for the serial data after the call format encapsulation transition according to above-mentioned UART time series datas is：For
Transformed serial data addition start bit, check bit sum stop bits, obtain a frame UART data, the UART data such as obtained
For：Start bit, transformed 8 Bits Serial data, check bit sum stop bits, and obtained UART data are exported by its pin
The UART pin external to coupled CCU, so as to record the FPGA configuration data of drive load, convenient for number is configured to FPGA
According to loading procedure be monitored.
Herein it should be noted is that：Detecting the feasible pattern for driving and need to loading FPGA configuration data is：It is receiving
In the case of preset data, determine that driving need to load FPGA configuration data, wherein preset data can be decided through consultation freely, such as can be with
It is 0xaa, 0x55,0xaa, 0x55,0xaa, 0x55,0xaa and the 0x55 being written successively, in the case where showing after receiving these data
The data of write-once are then FPGA configuration datas, then drive the FPGA configuration data that can be loaded and subsequently be written.
104：It is detecting the completion FPGA configuration data loading of CCU systems, the startup for having CPU will be recorded by CPLD controls
The startup running log of operational process is exported to the external UART of CCU systems, so as to pass through the startup running log of output
The startup operational process of CPU is monitored.
In the present embodiment, detection CCU systems, which complete configuration data loading feasible pattern, is：Detecting configuration data
Complement mark position is switched to default flag bit, is 1 as complement mark position is raised, then illustrates to have completed the loading of configuration data,
If drawing high than FPGA loading complement marks, illustrate to have completed the loading of FPGA configuration data.
From above-mentioned technical proposal it is found that in the case where detecting that CCU systems need to load configuration data, pass through CCU systems
CPLD by the configuration data that need to be loaded (such as hardware configuration word and FPGA configuration data) with external universal asynchronous of CCU systems
The corresponding sequential export of receiving-transmitting transmitter is detecting that CCU systems are complete to the external universal asynchronous receiving-transmitting transmitter of CCU systems
After the universal asynchronous receiving-transmitting transmitter initialization external into the CPU completions CPU of configuration data loading and CCU systems, pass through CPLD
The startup running log for recording the startup operational process for having CPU is exported to the external universal asynchronous receiving-transmitting transmitter of CCU systems,
Realize the time division multiplexing of the universal asynchronous receiving-transmitting transmitter external to CCU systems, and by exporting to external general of CCU systems
Asynchronous receiving-transmitting transmitter data, such as configuration data and startup running log can be to the startup operational process of data loading and CPU
It is monitored, realizes the positioning to the problems in start-up loading flow, so as to reduce research and development and debugging difficulty.
Corresponding with above method embodiment, the embodiment of the present invention also provides a kind of data monitoring device, applied to CCU systems
In system, structure is as shown in Fig. 2, can include：First control unit 11 and the second control unit 12.
First control unit 11, in the case where detecting that CCU systems need to load configuration data, passing through CCU systems
CPLD by the configuration data that need to be loaded with the corresponding sequential exports of the external UART of CCU systems to the external UART of CCU systems.
In the present embodiment, the CPU that the configuration data that CCU systems need to load includes but not limited to CCU systems need to be loaded firmly
Part configuration words and the driving communicated with CPLD need to load FPGA configuration data.Corresponding, the first control unit 11 is detecting
To CCU systems CPU need to load hardware configuration word in the case of, it is by CPLD that hardware configuration word is external with CCU systems
The corresponding sequential exports of UART need to be loaded to the external UART of CCU systems and in the driving for detecting CCU systems by CPLD
In the case of FPGA configuration data, by CPLD by FPGA configuration data with the corresponding sequential exports of the external UART of CCU systems
The UART external to CCU systems.
Specifically, the first control unit 11 is in the case where detecting that CPU need to load hardware configuration word, according to CCU systems
Form required by the corresponding sequential of external UART often receives the hardware configuration word of preset quantity by CPLD then by present count
The hardware configuration word of amount is encapsulated as UART time series datas, and the UART time series datas are exported to the external UART of CCU systems.
And in the case where detecting that driving need to load FPGA configuration data, the first control unit 11 by CPLD obtain with
The FPGA configuration data of parallel transmission in the connected bus of driving, and wanted according to the corresponding sequential of the external UART of CCU systems
Form is sought, after the FPGA configuration data for often obtaining preset quantity, the FPGA configuration data of preset quantity is encapsulated as UART sequential
Data export UART time series datas to the external UART of CCU systems.
Second control unit 12, for being completed in the CPU for detecting the completion configuration data loading of CCU systems and CCU systems
After UART initialization external CPU, exported by CPLD controls by the startup running log of startup operational process for having CPU is recorded
The UART external to CCU systems.
From above-mentioned technical proposal it is found that in the case where detecting that CCU systems need to load configuration data, pass through CCU systems
CPLD the configuration data that need to be loaded (such as hardware configuration word and FPGA configuration data) is corresponded to the external UART of CCU systems
Sequential export to the external UART of CCU systems, and detecting that CCU systems complete configuration data loading and CCU systems
After CPU completes the external UART initialization of CPU, run by CPLD controls by the startup of startup operational process for having CPU is recorded
Daily record exports the time division multiplexing for the external UART of CCU systems, realizing the UART external to CCU systems, and passes through output to CCU
The external UART data of system, such as configuration data and startup running log can be to the startup operational process of data loading and CPU
It is monitored, realizes the positioning to the problems in start-up loading flow, so as to reduce research and development and debugging difficulty.
The embodiment of the present invention also provides a kind of storage medium, and computer program stream, computer journey are stored on storage medium
Sequence stream, which is performed, realizes above-mentioned data monitoring method.
It should be noted that each embodiment in this specification is described by the way of progressive, each embodiment weight
Point explanation is all difference from other examples, and just to refer each other for identical similar part between each embodiment.
For device class embodiment, since it is basicly similar to embodiment of the method, so description is fairly simple, related part is joined
See the part explanation of embodiment of the method.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only include that
A little elements, but also including other elements that are not explicitly listed or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except also there are other identical elements in the process, method, article or apparatus that includes the element.
The foregoing description of the disclosed embodiments enables those skilled in the art to realize or use the present invention.To this
A variety of modifications of a little embodiments will be apparent for a person skilled in the art, and the general principles defined herein can
Without departing from the spirit or scope of the present invention, to realize in other embodiments.Therefore, the present invention will not be limited
The embodiments shown herein is formed on, and is to fit to consistent with the principles and novel features disclosed herein most wide
Range.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of data monitoring method, applied in master clock plate system, which is characterized in that the method includes：
In the case where detecting that master clock plate system need to load configuration data, pass through the complexity of the master clock plate system
Programmable logic device is by the configuration data that need to be loaded with the external universal asynchronous receiving-transmitting transmitter of the master clock plate system
Corresponding sequential export is to the external universal asynchronous receiving-transmitting transmitter of master clock plate system；
It is complete in the central processing unit for detecting the completion configuration data loading of master clock plate system and the master clock plate system
It, will record by Complex Programmable Logic Devices control after the universal asynchronous receiving-transmitting transmitter initialization external into central processing unit
The startup running log for having the startup operational process of the central processing unit is exported to external general different of master clock plate system
Walk receiving-transmitting transmitter.
2. according to the method described in claim 1, it is characterized in that, described detecting that master clock plate system need to load configuration
In the case of data, by the Complex Programmable Logic Devices of the master clock plate system by the configuration data that need to be loaded with institute
It is external to master clock plate system to state the external corresponding sequential export of universal asynchronous receiving-transmitting transmitter of master clock plate system
Universal asynchronous receiving-transmitting transmitter includes：
In the case where the central processing unit for detecting the master clock plate system need to load hardware configuration word, by described multiple
Miscellaneous programmable logic device is by the hardware configuration word with the external universal asynchronous receiving-transmitting transmitter of the master clock plate system
Corresponding sequential export is to the external universal asynchronous receiving-transmitting transmitter of master clock plate system；
Detect the driving communicated with the Complex Programmable Logic Devices need loading field programmable gate array be configured number
In the case of, by the Complex Programmable Logic Devices by the field programmable gate array configuration data with master clock
The corresponding sequential export of the external universal asynchronous receiving-transmitting transmitter of plate system is to the external universal asynchronous receipts of master clock plate system
Send out transmitter.
It is 3. according to the method described in claim 2, it is characterized in that, described in the central processing for detecting master clock plate system
In the case that device need to load hardware configuration word, by the Complex Programmable Logic Devices by the hardware configuration word with the master
The external corresponding sequential export of universal asynchronous receiving-transmitting transmitter of clock board system is controlled to external general of master clock plate system
Asynchronous receiving-transmitting transmitter includes：
It is external according to the master clock plate system in the case where detecting that the central processing unit need to load hardware configuration word
The corresponding sequential of universal asynchronous receiving-transmitting transmitter required by form, often received by the Complex Programmable Logic Devices pre-
Ordinal number when if the hardware configuration word of the preset quantity is then encapsulated as universal asynchronous receiving-transmitting transmitter by the hardware configuration word of quantity
According to, and the universal asynchronous receiving-transmitting transmitter time series data is exported to the external universal asynchronous receiving-transmitting of master clock plate system and is transmitted
Device.
4. according to the method described in claim 2, it is characterized in that, described detecting and the Complex Programmable Logic Devices
In the case that the driving communicated needs loading field programmable gate array configuration data, pass through the Complex Programmable Logic Devices
The field programmable gate array configuration data is corresponding with the external universal asynchronous receiving-transmitting transmitter of master clock plate system
Sequential export to the external universal asynchronous receiving-transmitting transmitter of master clock plate system includes：
In the case where detecting that the driving needs loading field programmable gate array configuration data, pass through the complex programmable
Logical device obtains the field programmable gate array configuration data of parallel transmission in the bus being connected with the driving, and according to institute
Form required by stating the external corresponding sequential of universal asynchronous receiving-transmitting transmitter of master clock plate system often obtains preset quantity
After field programmable gate array configuration data, the field programmable gate array configuration data of the preset quantity is encapsulated as general
Asynchronous receiving-transmitting transmitter time series data exports the universal asynchronous receiving-transmitting transmitter time series data to outside master clock plate system
The universal asynchronous receiving-transmitting transmitter connect.
5. according to the method described in claim 2, it is characterized in that, the method further includes：In the feelings for receiving preset data
Under condition, determine that the driving needs loading field programmable gate array configuration data.
6. a kind of data monitoring device, applied in master clock plate system, which is characterized in that described device includes：
First control unit, in the case where detecting that master clock plate system need to load configuration data, passing through the master
The Complex Programmable Logic Devices for controlling clock board system is external with the master clock plate system by the configuration data that need to be loaded
The corresponding sequential export of universal asynchronous receiving-transmitting transmitter is to the external universal asynchronous receiving-transmitting transmitter of master clock plate system；
Second control unit, for detecting the completion configuration data loading of master clock plate system and the master clock plate
After the central processing unit of system completes the external universal asynchronous receiving-transmitting transmitter initialization of central processing unit, pass through complex programmable
Logical device control exports the startup running log for recording the startup operational process for having the central processing unit to master clock
The external universal asynchronous receiving-transmitting transmitter of plate system.
7. device according to claim 6, which is characterized in that first control unit, specifically for detecting
In the case of stating the central processing unit of master clock plate system and need to loading hardware configuration word, pass through the complicated programmable logic device
Part is by the hardware configuration word with the external corresponding sequential export of universal asynchronous receiving-transmitting transmitter of the master clock plate system
The universal asynchronous receiving-transmitting transmitter external to master clock plate system；
And specifically for detecting that the driving communicated with the Complex Programmable Logic Devices needs loading field programmable
In the case of gate array configuration data, the field programmable gate array is configured by number by the Complex Programmable Logic Devices
The corresponding sequential export of the external universal asynchronous receiving-transmitting transmitter of master clock plate system is external to master clock plate system according to this
Universal asynchronous receiving-transmitting transmitter.
8. device according to claim 7, which is characterized in that first control unit, specifically for detecting
In the case of stating central processing unit and need to loading hardware configuration word, according to the external universal asynchronous receiving-transmitting of the master clock plate system
Form required by the corresponding sequential of transmitter, the hardware that preset quantity is often received by the Complex Programmable Logic Devices are matched
It puts word and the hardware configuration word of the preset quantity is then encapsulated as universal asynchronous receiving-transmitting transmitter time series data, and this is general different
Step receiving-transmitting transmitter time series data is exported to the external universal asynchronous receiving-transmitting transmitter of master clock plate system.
9. device according to claim 7, which is characterized in that first control unit, specifically for detecting
In the case of stating driving and needing loading field programmable gate array configuration data, by the Complex Programmable Logic Devices obtain with
The field programmable gate array configuration data of parallel transmission in the connected bus of the driving, and according to the master clock plate system
It unites form required by the corresponding sequential of external universal asynchronous receiving-transmitting transmitter, often obtains the field-programmable gate array of preset quantity
After row configuration data, the field programmable gate array configuration data of the preset quantity is encapsulated as universal asynchronous receiving-transmitting transmitter
Time series data exports the universal asynchronous receiving-transmitting transmitter time series data to the external universal asynchronous receipts of master clock plate system
Send out transmitter.
10. a kind of storage medium, which is characterized in that computer program stream, the computer journey are stored on the storage medium
Sequence stream is performed the data monitoring method realized as described in claim 1 to 5 any one.
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