CN108233929B

CN108233929B - Discrete magnitude sampling circuit

Info

Publication number: CN108233929B
Application number: CN201611156507.1A
Authority: CN
Inventors: 董凯; 高栋; 冯非; 田育新; 赵腊才; 程苏
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Priority date: 2016-12-14
Filing date: 2016-12-14
Publication date: 2021-06-01
Anticipated expiration: 2036-12-14
Also published as: CN108233929A

Abstract

The discrete magnitude sampling circuit realizes sampling of external input discrete magnitude and has anti-jamming capability and loop test of the discrete magnitude. The circuit can sample external input discrete quantity, when the discrete quantity shakes due to interference, the sampling circuit can filter the interference, and the sampling result cannot be changed due to the input shaking; this sampling circuit feeds back external input discrete magnitude to the host computer, and self has the loop test, can test whether sampling circuit normally works, the signal of test is sent by the host computer, the high low level of this test signal simulation external input discrete magnitude, input at sampling circuit's front end, the result that detects out when sampling circuit is the same with test signal then shows that sampling circuit normally works, different then show that sampling circuit works unusually, and test signal can also be for the low level for the high level, the omnidirectional has tested sampling circuit, sampling circuit work's accuracy and reliability have been guaranteed, the testability has been improved.

Description

Discrete magnitude sampling circuit

Technical Field

The invention belongs to the field of computer application. To a discrete magnitude sampling circuit.

Background

At present, discrete quantity sampling circuits are applied to discrete quantity input, because of various signal types of discrete quantities, the sampling circuits are different, but the accurate sampling of discrete quantities is not beyond the stability, reliability and accuracy of the sampling circuits.

Disclosure of Invention

The invention provides a high-reliability high-accuracy discrete quantity sampling circuit, which has the capacity of resisting disturbance, filters unstable jitter of discrete quantity, can perform loop test on the sampling circuit and ensures the accuracy of the sampling circuit.

The invention aims to ensure the accuracy, reliability and stability of the discrete quantity sampling circuit and improve the testability of the discrete quantity sampling circuit.

The detailed technical scheme of the invention is as follows:

1. a discrete magnitude sampling circuit is composed of a discrete magnitude sampling circuit, an anti-interference circuit and a loop test circuit; (1) the discrete quantity sampling circuit is composed of a voltage division resistor, an inverter and an optical coupler, divides the level of an input signal, adjusts the level through the inverter, and inputs the level to the optical coupler for isolation so as to be sampled by a processor at the rear end; (2) the anti-interference circuit is composed of a resistance-capacitance network, is positioned at the front end of the sampling circuit, and directly eliminates jitter and filters an input signal at the front end; the jitter generated on the input signal due to external interference is filtered, and the RC network formed by adopting the resistance capacitor is used for filtering and eliminating the jitter; (3) the loop test circuit is composed of an optical coupler, an inverter and a single-pole single-throw bus switch, a test signal sent by a processor at the rear end generates a discrete magnitude sampling circuit test signal through a test circuit composed of the optical coupler, the inverter and the single-pole single-throw bus switch, the test signal is input to the front end of the discrete magnitude sampling circuit, the processor compares the sampled signal with the preset test signal, and whether the sampling circuit is accurate or not is judged.

2. The discrete magnitude sampling circuit adopts an optical coupler to carry out level isolation at the front end and the rear end.

3. The discrete magnitude sampling circuit adopts an inverter to carry out level high-low conversion on discrete magnitude.

4. The anti-interference circuit adopts an RC network formed by a resistor and a capacitor to carry out filtering and jitter elimination processing, and parameters of the anti-interference circuit are adjusted according to the use environment.

5. The loop test circuit is composed of two paths of input test signals and generates one path of discrete magnitude sampling circuit test signals.

6. The level of one path of discrete magnitude sampling circuit test signals generated by the loop test circuit can be subjected to high-low conversion according to the levels of two paths of input signals.

Description of the drawings:

FIG. 1 is a detailed functional block diagram

FIG. 2 is a block diagram showing the detailed principle of the present invention

The specific implementation mode is as follows:

the discrete magnitude sampling circuit mainly realizes sampling of discrete magnitude and is composed of a divider resistor, a phase inverter and an optical coupler. The discrete quantity input is input, the ground open type discrete quantity is GND _1, when the input is an open signal, the diode V1 is not conducted, VCC _1 is input to the front end of the inverter N1 through R1, R2 and R3 voltage division, the input is high level, the VCC _1 is inverted to low level through N1, the optocoupler N2 is conducted, the output is low level, and meanwhile, the reference ground is switched to GND _2 for the acquisition of a rear-stage module; when the input signal is a ground signal, the diode V1 is conducted, the voltage at the positions of R1 and R2 is a conduction voltage drop of V1 and 0.7V, the voltage is divided by R2 and R3, the voltage is input to the front end of the inverter N1 to be a low level, the voltage is inverted to be a high level through N1, the optocoupler N2 is not conducted, the output is a high level, and meanwhile, the reference ground is switched to be GND _2 for the acquisition of a rear-stage module.

The anti-interference is formed by a resistance-capacitance network, namely, the RC charge-discharge circuit formed by R2 and C1 is realized, when abnormal jitter is generated by external input discrete quantity, due to the charge-discharge of R2 and C1, the jitter is effectively filtered, the output end level of N1 is ensured not to jump, the RC time constant iota is R2 multiplied by C1, a proper RC can be selected according to the possible jitter time of an input signal, the delay time of the post-stage sampling is prolonged due to the overlarge C, the signal instantaneity is reduced, the RC is reasonably selected to be combined, the jitter can be filtered, and the variation of the discrete quantity can be quickly fed back to a rear-end acquisition module.

The loop test circuit is composed of an optical coupler, an inverter and a single-pole/single-throw bus switch, BIT1 and BIT0 signals are sent by a rear-end acquisition module, BIT1 and BIT0 signals can be high or low, 4 conditions are provided in total, and each condition is explained in detail below.

(1) When BIT1 and BIT0 are 00, that is, BIT0 and BIT1 are all low level, BIT0 is low level, the output of N5 inverter is high level, the primary side of N7 optical coupler is not conducted, the enable input of N10 single-pole/single-throw bus switch is low level, and AB is not conducted; BIT1 is low level, the output of N4 inverter is high level, the primary side of N6 optocoupler is not conducted, the enable input of N9 single-pole/single-throw bus switch is low level, AB is not conducted; therefore, the Test signal is suspended, and is in a discrete quantity sampling mode in the mode, and the Test signal does not influence the sampling of the discrete quantity.

(2) When BIT1 and BIT1 are 01, BIT0 is high and BIT1 is low. BIT1 is low level, the output of N4 inverter is high level, the primary side of N6 optocoupler is not conducted, the enable input of N9 single-pole/single-throw bus switch is low level, AB is not conducted, the output of N8 inverter is high level; BIT0 is high level, and N5 inverter output is low level, and N7 opto-coupler primary side switches on, because N8 inverter output is high level, and the enabling input of N10 single-pole/single-throw bus switch is high level, AB switches on. Because N9 nonconducting, N10 switches on, and Test signal is the low level, no matter discrete magnitude input is high level or low level, and N1 inverter output is the high level, and N2 opto-coupler former limit nonconducting, output are the high level, are discrete magnitude sampling circuit Test mode under this mode, and discrete magnitude sampling circuit output is the high level.

(3) When BIT1 and BIT1 are 10, i.e., BIT0 is low, BIT1 is high. BIT1 is high level, the output of N4 inverter is low level, the primary side of N6 optocoupler is conducted, the enable input of N9 single-pole/single-throw bus switch is high level, AB is conducted, the output of N8 inverter is low level; BIT0 is low level, N5 inverter output is high level, N7 opto-coupler primary side is nonconducting, N10 single-pole/single-throw bus switch's enable input is low level, AB is nonconducting. Because N9 switches on, N10 does not switch on, and Test signal is the high level, no matter discrete magnitude input is high level or low level, and N1 inverter output is the low level, and N2 opto-coupler former limit switches on, and output is the low level, is discrete magnitude sampling circuit Test mode under this mode, and discrete magnitude sampling circuit output is the low level.

(4) When BIT1 and BIT1 are 11, BIT0 is high and BIT1 is high. BIT1 is high level, the output of N4 inverter is low level, the primary side of N6 optocoupler is conducted, the enable input of N9 single-pole/single-throw bus switch is high level, AB is conducted, the output of N8 inverter is low level; BIT0 is high level, and N5 inverter output is low level, and N7 opto-coupler primary side switches on, because N8 inverter output is low level, and the enabling input of N10 single-pole/single-throw bus switch is low level, AB is not switched on. Because N9 switches on, N10 does not switch on, and Test signal is the high level, no matter discrete magnitude input is high level or low level, and N1 inverter output is the low level, and N2 opto-coupler former limit switches on, and output is the low level, is discrete magnitude sampling circuit Test mode under this mode, and discrete magnitude sampling circuit output is the low level.

Combining the above 4 conditions, the specific operation mode is shown in the following table 1:

TABLE 1 discrete quantity sampling circuit mode of operation

The 4 cases are combined into 3 working modes, namely a discrete quantity sampling mode, a discrete quantity sampling circuit test mode (the discrete quantity test is high) and a discrete quantity sampling circuit test mode (the discrete quantity test is low). The 3 modes have different functions, namely the sampling of discrete quantities is realized, and the sampling circuit can be tested, so that the accuracy and the reliability of sampling are ensured.

The circuit realizes sampling of discrete magnitude, filters abnormal jitter of input discrete magnitude, tests the discrete magnitude sampling circuit and ensures accuracy of the sampling circuit. The circuit has high practicability, and greatly improves the accuracy, reliability, stability and testability of discrete quantity sampling.

Claims

1. A discrete magnitude sampling circuit, characterized by: the loop test circuit consists of a sampling circuit, an anti-interference circuit and a loop test circuit; (1) the sampling circuit is composed of a voltage division resistor, an inverter N1 and an optocoupler N2, divides the level of an input signal, adjusts the level through the inverter N1, inputs the level to the optocoupler N2 for isolation, and is used for reading by a processor at the rear end; (2) the anti-interference circuit is composed of a resistance-capacitance network, is positioned at the front end of the sampling circuit, and directly eliminates jitter and filters input signals at the front end; filtering jitter generated on an input signal due to external interference; (3) the loop test circuit is composed of an optical coupler N6, an optical coupler N7, an inverter N4, an inverter N5, an inverter N8 and a single-pole single-throw bus switch, a test signal sent by a processor at the rear end passes through the loop test circuit to generate a test signal of the sampling circuit, the test signal is input to the front end of the sampling circuit, and the processor compares the sampled signal with a preset test signal to judge whether the sampling circuit is accurate.

2. The discrete magnitude sampling circuit of claim 1, wherein: the sampling circuit adopts an optical coupler N2 to carry out level isolation.

3. A discrete quantity sampling circuit as claimed in claim 1 or 2, wherein: the sampling circuit performs level high-low conversion on the discrete quantity by using an inverter N1.

4. The discrete magnitude sampling circuit of claim 1, wherein: the anti-interference circuit is formed by adopting a resistance-capacitance network, and parameters of the anti-interference circuit are adjusted according to the using environment.

5. The discrete magnitude sampling circuit of claim 1, wherein: the loop test circuit is composed of two paths of input test signals and generates a path of sampling circuit test signal.

6. The discrete magnitude sampling circuit of claim 5, wherein: the level of one path of sampling circuit test signals generated by the loop test circuit can be subjected to high-low conversion according to the levels of two paths of input signals.