CN108232000A - A kind of method for manufacturing microminiature magnetic random store-memory unit - Google Patents

A kind of method for manufacturing microminiature magnetic random store-memory unit Download PDF

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Publication number
CN108232000A
CN108232000A CN201611191871.1A CN201611191871A CN108232000A CN 108232000 A CN108232000 A CN 108232000A CN 201611191871 A CN201611191871 A CN 201611191871A CN 108232000 A CN108232000 A CN 108232000A
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layer
etching
memory
memory unit
magnetic random
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肖荣福
张云森
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Shanghai Ciyu Information Technologies Co Ltd
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Shanghai Ciyu Information Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The present invention provides a kind of methods for manufacturing microminiature magnetic random store-memory unit, and memory layer is performed etching using lithographic technique first；When etching remembers layer, not fully etching memory layer is allowed to leave ultra-thin memory layer on barrier layer；Then using oxidation technology, the memory layer periphery being exposed after etching is aoxidized.As a result of etching and aoxidize and method, not only reduce the conductive cross-sectional area of memory layer, and the formation of magnetic RAM memory layer and reference layer short-channel is completely eliminated, be conducive to the promotion of MRAM circuits magnetic behavior, electric property and product yield.

Description

A kind of method for manufacturing microminiature magnetic random store-memory unit
Technical field
The present invention relates to a kind of magnetic random store-memory units, and in particular to a kind of manufacture microminiature magnetic random storage The method of mnemon belongs to magnetic RAM (MRAM, Magnetic Radom Access Memory) manufacturing technology Field.
Background technology
In recent years, using the MRAM of magnetic tunnel junction (MTJ, Magnetic Tunnel Junction) by it is believed that being Following solid state non-volatile memory body, it has the characteristics that high-speed read-write, large capacity and low energy consumption.Ferromagnetism MTJ is usual For sandwich structure, wherein the memory layer that is magnetic, it can change the direction of magnetization to record different data；Positioned at the exhausted of centre The tunnel barrier layer of edge；Magnetic reference layer, positioned at the opposite side of tunnel barrier layer, its direction of magnetization is constant.
For information can be recorded in this magnetoresistive element, it is proposed that using based on spin momentum transfer or spin-transfer torque The write method of (STT, Spin Transfer Torque) switch technology, such MRAM are known as STT-MRAM.According to magnetic polarization The difference in direction, STT-MRAM are divided into as STT-MRAM in face and vertical STT-MRAM (i.e. pSTT-MRAM), and the latter has preferably Performance.Method according to this, you can by providing spin polarized current to magnetoresistive element come the intensity of magnetization of inverting magnetization memory layer Direction.In addition, the reduction of the volume with Magnetic memory layer, write or spin polarized current that conversion operation need to be injected is also smaller. Therefore, this write method can be achieved at the same time device miniaturization and reduce electric current.
Meanwhile in view of switching electric current required when reducing MTJ element size can also reduce, so the pSTT- in terms of scale MRAM can be very good mutually to agree with state-of-the-art technology node.Therefore, it is desirable to it is that pSTT-MRAM elements are made into minimum ruler It is very little, and with extraordinary uniformity and the influence to MTJ magnetism is minimized, used preparation method can also be real Show high good and the bad rate, pinpoint accuracy, high reliability, low energy consumption and remain adapted to the temperature coefficient that data well preserve.Meanwhile Write operation is changed based on resistance state in nonvolatile memory, so as to need control thus caused to mtj memory device lifetime Destruction and shortening.However, the fluctuation of MTJ resistance may be increased by preparing a small-sized MTJ element so that pSTT-MRAM's Larger fluctuation can also be had therewith by writing voltage or electric current, can damage the performance of MRAM in this way.
In present MRAM manufacturing process, generally using a step etching technics to magnetic tunnel junction, i.e.,：To memory layer, Barrier layer and reference layer perform etching.Reactive ion etching (RIE, Reactive Ion may be used in specific scheme Etching) or the method for ion beam etching (IBE, Ion Beam Etching) is to realize, etches the physical damnification brought, changes Learn damage and since the short circuit again between reference layer caused by deposition and memory layer of etch by-products is all inevitable The problem of, this will influence the magnetism and electric property of MRAM device, be unfavorable for the raising of MRAM circuits yield.
Invention content
To solve the above-mentioned problems, the present invention provides a kind of sides for manufacturing microminiature magnetic random store-memory unit Method first performs etching memory layer using lithographic technique, and when etching remembers layer, not fully etching memory layer is allowed to Ultra-thin memory layer is left on barrier layer, then using oxidation technology, to the ultra-thin memory layer periphery that is exposed after etching into Row oxidation, reduces its conductive cross-sectional area.It is as follows：
Step 1：In the CMOS substrates of surface polishing, hearth electrode, magnetic tunnel junction and hard mask film layer are sequentially formed； Magnetic tunnel junction is the multi-layer film structure being sequentially overlapped by reference layer, barrier layer and memory layer；
Step 2：Graphic definition magnetic tunnel junction pattern, and pattern is shifted to the top of magnetic tunnel junction；
Step 3：Reactive ion etching remembers layer, and retains one layer of ultra-thin memory layer to prevent memory layer from being cut through；
Step 4：Ultra-thin memory layer, reference layer and the side wall of hard mask film layer and bottom-exposed part are aoxidized, forms electricity absolutely Edge layer；
Step 5：Ion is carried out to the ultra-thin memory layer bottom, barrier layer, the reference layer aoxidized and the hearth electrode that are aoxidized Beam etches；
Step 6：Dielectric filler etches gap, and is polished using chemically mechanical polishing until not oxidized hard mask The top of film layer.
Beneficial effects of the present invention：As a result of etching and aoxidize and method, not only reduce and to remember layer and lead Electric sectional area and the formation for completely eliminating magnetic RAM memory layer and reference layer short-channel are conducive to MRAM and return The promotion of road magnetic behavior, electric property and product yield.
Description of the drawings
Fig. 1 is the flow chart of the manufacturing process of the preferred embodiment of the present invention；
Fig. 2 is in the preferred embodiment of the present invention, and hearth electrode, magnetic are sequentially formed in the CMOS substrates of surface polishing Schematic diagram after property tunnel knot and hard mask film layer；
Fig. 3 is graphic definition magnetic tunnel junction pattern in the preferred embodiment of the present invention, and shifts pattern to magnetic Property tunnel knot at the top of after schematic diagram；
Fig. 4 is reactive ion etching memory layer in the preferred embodiment of the present invention, and retains one layer of ultra-thin memory layer With the schematic diagram for preventing memory layer from being cut through；
Fig. 5 is in the preferred embodiment of the present invention, by the use of the hard mask after etching as protective layer to ultra-thin memory layer And the side wall of the reference layer under it carries out depth lateral oxidation, reduces the schematic diagram of the cross section of memory layer perpendicular-to-plane；
Fig. 6 is in the preferred embodiment of the present invention, using the memory layer side wall after hard mask and oxidation as mask, to quilt Ultra-thin memory layer, barrier layer, the reference layer aoxidized and the hearth electrode of oxidation carry out the schematic diagram after ion beam etching；
Fig. 7 is the gap around hard mask that dielectric filler is not etched in the preferred embodiment of the present invention, and Schematic diagram until being polished at the top of not oxidized hard mask using chemically mechanical polishing；
Shown in figure：The CMOS substrate of 1- surfaces polishing, 2- hearth electrodes, 3- reference layers, 4- barrier layers, 5- memory layers, 50- Ultra-thin memory layer, 6- hard mask film layers, 7- electric insulation layers, 8- electrolyte.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.It should be noted that attached drawing of the present invention uses using the form of simplification and non-essence Accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The present invention a kind of manufacture microminiature magnetic random store-memory unit method, including but be not limited solely to prepare magnetic Property random access memory (MRAM), is also not necessarily limited to any process sequence or flow, if the product or device that are prepared with it is following Selection process sequence or flow are prepared same or similar.As shown in Figure 1, this method includes the following steps：
Step 1：As shown in Fig. 2, in the CMOS substrates 1 of surface polishing, it is sequentially depositing hearth electrode 2, reference layer 3, potential barrier Layer 4, memory layer 5 and hard mask film layer 6.Wherein hearth electrode 2 includes Seed Layer and conductive layer.Seed Layer is Ta, TaN, W, WN, Ti Or TiN, the thickness of Seed Layer is 0.5nm~5nm.Conductive layer is Cu, CuN, Mo, W or Ru, the thickness of conductive layer for 5nm~ 30nm。
Preferably, the overall thickness of magnetic tunnel junction (MTJ) multilayer film is 15nm~40nm, it is by reference layer 3, barrier layer The 4 Bottom Pinned structures being superimposed upwards successively with memory layer 5.
Further, reference layer 3 has magnetic polarization invariance, is face inner mold (iSTT-MRAM) or vertical-type according to it (pSTT-MRAM) structure is different.The reference layer of face inner mold (iSTT-MRAM) generally has (IrMn or PtMn)/CoFe/ Ru/CoFe structures, preferred overall thickness are 10nm~30nm.The reference layer of vertical-type (pSTT-MRAM) generally has TbCoFe Or [Co/Pt]nCo/Ru/[CoPt]mSuperlattice multilayer film structure, preferred overall thickness are 8nm~20nm.
Further, barrier layer 4 is nonmagnetic metal oxide, preferably MgO, MgZnO or Al2O3, thickness 0.5nm ~3nm.
Further, memory layer 5 polarizes with variable magnetic, is face inner mold (iSTT-MRAM) or vertical-type according to it (pSTT-MRAM) institute is different again for structure.The memory layer of face inner mold (iSTT-MRAM) is generally CoFe/CoFeB or CoFe/NiFe, Its preferred thickness is 2nm~6nm.Vertical-type (pSTT-MRAM) memory layer be generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB/ (Ta, W, Mo)/CoFeB, preferred thickness are 0.8nm~2nm.
Preferably, the thickness of hard mask film layer 6 is 40nm~100nm, deposition materials selected as Ta or W, in F members Better profile is obtained in plain plasma-based.
Step 2：Graphic definition magnetic tunnel junction pattern, and pattern is shifted to magnetic tunnel junction top as shown in Figure 3 Portion.In the process, (LE, lithography-etching) or Twi-lithography is once etched using a photoetching to carve twice Lose definition of the method completion of (LELE, lithography-etching-lithography-etching) to magnetic tunnel junction It is etched with the reactive ion (RIE) of hard mask film layer 6, and remaining polymer is removed using RIE techniques simultaneously, so that pattern turns Move on to the top of magnetic tunnel junction.
Step 3：Hard mask film layer 6 remembers layer 5 for mask reactive ion etching, and retains one layer of ultra-thin memory layer 50 To prevent memory layer from being cut through, as shown in Figure 4.
Preferably, the gas pressure intensity selected by reactive ion etching (RIE) is 1mTorr~100mTorr；Used master Etching gas is CH3OH or C2H5OH, CO/NH3It is 5sccm~100sccm Deng, flow, H can also be added2、N2、He、Ar、 Kr or Xe etc., flow are 10sccm~200sccm；The radio-frequency power supply power for generating and maintaining plasma is 200W~3000W； The radio-frequency power supply power for generating and maintaining bias is 0W~1500W；Wafer console temperature is 20 DEG C~200 DEG C.
Preferably, emission spectrometer (OES, Optical Emission Spectroscopy) is selected to be carved to monitor RIE The variation of erosion memory 5 component spectrum signal of layer.Stringent control RIE technological parameters and etch period, prevent barrier layer from being cut through, together When, it leaves one layer of ultra-thin memory layer 50 and comes as buffering.
Step 4：Hard mask side wall and bottom are retained after aoxidizing ultra-thin memory layer 50 and reference layer 3 below and etching Portion's expose portion is changed into electric insulation layer 7, to reduce the vertical conduction sectional area of memory layer 5, as shown in Figure 5.
Ion implanting (IIT, Ion Implantation Technology), ion beam etching may be used in oxidation technology (IBE, Ion Beam Etching), reactive ion etching (RIE, Reactive Ion Etching) or remote plasma etching Technology (RPE, Remote Plasma Etching) etc.；Wherein, one of which or several may be used in oxidation technology, to adjust Whole oxygen atom/oxonium ion, pure chemistry reaction/physical bombardment ratio remember layer to obtain to being exposed to outer side wall and bottom Maximum oxidation；Preferably, the reference layer 3 below ultra-thin memory layer 50 can be further aoxidized to obtain more preferable insulation performance.
Preferably, after oxidation technology, in vacuum environment, to the magnetic tunneling junction cell array of part processing into The high-temperature thermal annealing that 250 DEG C~500 DEG C of row, to repair the damage generated in oxidation process or defect, wherein, annealing time is 30 seconds to 30 minutes；
Step 5：Using the memory layer side wall after hard mask and oxidation as mask, to aoxidized ultra-thin memory layer 50, potential barrier Layer 4, the reference layer 3 aoxidized and hearth electrode 2 carry out ion beam etching, as shown in Figure 6；Meanwhile using emission spectrometer or The method detecting etching terminal of Secondary Ion Mass Spectrometry.
Preferably, using He, Ne, Ar, Kr or Xe etc. as ion source, flow is ion beam etching (IBE) 10sccm~200sccm, such as：10sccm, 30sccm, 50sccm, 100sccm or 200sccm etc.；Generate and maintain etc. from The power of the radio-frequency power supply of son is 100Watt~3000Watt, and ion beam accelerating voltage is 50V~1000V, the direction of ion beam Angle is 0 °~90 °, such as：0 ° or 5 ° etc., the speed of wafer console rotation is 0~60rpm, such as：0rpm, 30rpm or Person 60rpm etc..
Step 6：Dielectric 8 fills the gap around the hard mask not being etched, and is polished directly using chemically mechanical polishing To at the top of not oxidized hard mask, as shown in Figure 7.Wherein, dielectric 8 is SiO2、SiN、SiON、SiC、SiCN、Al2O3Or One kind in person MgO.
The preferred embodiment of the present invention described in detail above.It should be appreciated that those of ordinary skill in the art without Creative work is needed according to the present invention can to conceive and makes many modifications and variations.Therefore, all technologies in the art Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea Technical solution, all should be in the protection domain being defined in the patent claims.

Claims (10)

  1. A kind of 1. method for manufacturing magnetic random store-memory unit, which is characterized in that the endless full etching when etching remembers layer And ultra-thin memory layer is left, then the ultra-thin memory layer periphery is aoxidized.
  2. 2. a kind of method for manufacturing magnetic random store-memory unit according to claim 1, which is characterized in that including such as Lower step：
    Step 1：In the CMOS substrates of surface polishing, hearth electrode, magnetic tunnel junction and hard mask film layer are sequentially formed；It is described Magnetic tunnel junction is the multi-layer film structure being sequentially overlapped by reference layer, barrier layer and memory layer；
    Step 2：Graphic definition magnetic tunnel junction pattern, and the pattern is shifted to the top of the magnetic tunnel junction；
    Step 3：Layer is remembered described in reactive ion etching, and retains one layer of ultra-thin memory layer to prevent the memory layer quilt It cuts through；
    Step 4：The ultra-thin memory layer, the reference layer and the side wall of the hard mask film layer and bottom-exposed part are aoxidized, Form electric insulation layer；
    Step 5：To the ultra-thin memory layer bottom, the barrier layer, the reference layer aoxidized and the bottom aoxidized Electrode carries out ion beam etching；
    Step 6：Dielectric filler etches gap, and is polished using chemically mechanical polishing until the not oxidized hard mask The top of film layer.
  3. A kind of 3. method for manufacturing magnetic random store-memory unit according to claim 2, which is characterized in that the bottom Electrode includes Seed Layer and conductive layer, and the thickness of the Seed Layer is 0.5nm~5nm, the thickness of the conductive layer for 5nm~ 30nm。
  4. A kind of 4. method for manufacturing magnetic random store-memory unit according to claim 2, which is characterized in that the magnetic Property tunnel knot multi-layer film structure overall thickness be 15nm~40nm.
  5. 5. a kind of method for manufacturing magnetic random store-memory unit according to claim 2, which is characterized in that described hard The thickness of mask film layer is 40nm~100nm, and deposition materials are selected from Ta or W.
  6. 6. a kind of method for manufacturing magnetic random store-memory unit according to claim 2, which is characterized in that described anti- The main etching gas for answering ion etching is CH3OH、C2H5OH or CO/NH3, gas pressure intensity be 1mTorr~100mTorr, gas stream It measures as 5sccm~100sccm；H is added in the main etching gas2、N2, He, Ar, Kr or Xe, the gas flow of addition is 10sccm~200sccm.
  7. 7. a kind of method for manufacturing magnetic random store-memory unit according to claim 2, which is characterized in that select hair The variation for component spectrum signal of spectrometer being penetrated when etching the memory layer to monitor, controls etch process parameters and etch period, Leave the ultra-thin memory layer.
  8. A kind of 8. method for manufacturing magnetic random store-memory unit according to claim 2, which is characterized in that the oxygen Change using ion implanting, ion beam etching, reactive ion etching, remote plasma etching one or more of technique.
  9. A kind of 9. method for manufacturing magnetic random store-memory unit according to claim 2, which is characterized in that step 5 Described in ion beam etching gas select He, Ne, Ar, Kr or Xe one or several kinds.
  10. A kind of 10. method for manufacturing magnetic random store-memory unit according to claim 2, which is characterized in that step Dielectric described in six includes SiO2、SiN、SiON、SiC、SiCN、Al2O3Or one kind in MgO；And it is thrown using chemical machinery Tarry matter is straight to the top of the not oxidized hard mask film layer, to ensure the conducting of entire memory circuit.
CN201611191871.1A 2016-12-21 2016-12-21 A kind of method for manufacturing microminiature magnetic random store-memory unit Pending CN108232000A (en)

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Cited By (4)

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Publication number Priority date Publication date Assignee Title
WO2020093681A1 (en) * 2018-11-08 2020-05-14 江苏鲁汶仪器有限公司 Semiconductor device manufacturing method
CN111613719A (en) * 2019-02-22 2020-09-01 上海磁宇信息科技有限公司 Method for manufacturing magnetic random access memory unit array
CN111864058A (en) * 2020-07-29 2020-10-30 浙江驰拓科技有限公司 Preparation method of storage bit and preparation method of MRAM
CN112531106A (en) * 2019-09-18 2021-03-19 中电海康集团有限公司 Preparation method of magnetic tunnel junction

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CN104995685A (en) * 2013-01-11 2015-10-21 海德威科技公司 Mg discontinuous insertion layer for improving mt j shunt
WO2016126750A1 (en) * 2015-02-04 2016-08-11 Everspin Technologies, Inc. Magnetoresistive stack/structure and method of manufacturing same
CN107785485A (en) * 2016-08-31 2018-03-09 中电海康集团有限公司 A kind of preparation method of MTJ

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US20120244639A1 (en) * 2011-03-22 2012-09-27 Yuichi Ohsawa Method of manufacturing magnetic memory
CN104995685A (en) * 2013-01-11 2015-10-21 海德威科技公司 Mg discontinuous insertion layer for improving mt j shunt
US20140227801A1 (en) * 2013-02-08 2014-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of Forming a Magnetic Tunnel Junction Device
WO2015153107A1 (en) * 2014-04-02 2015-10-08 Qualcomm Incorporated Replacement conductive hard mask for multi-step magnetic tunnel junction (mtj) etch
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CN107785485A (en) * 2016-08-31 2018-03-09 中电海康集团有限公司 A kind of preparation method of MTJ

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020093681A1 (en) * 2018-11-08 2020-05-14 江苏鲁汶仪器有限公司 Semiconductor device manufacturing method
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CN111613719B (en) * 2019-02-22 2023-09-22 上海磁宇信息科技有限公司 Method for manufacturing magnetic random access memory cell array
CN112531106A (en) * 2019-09-18 2021-03-19 中电海康集团有限公司 Preparation method of magnetic tunnel junction
CN111864058A (en) * 2020-07-29 2020-10-30 浙江驰拓科技有限公司 Preparation method of storage bit and preparation method of MRAM

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Application publication date: 20180629