CN108231902A - More stacked layer power devices with series connection slot grid structure - Google Patents
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- CN108231902A CN108231902A CN201810010047.4A CN201810010047A CN108231902A CN 108231902 A CN108231902 A CN 108231902A CN 201810010047 A CN201810010047 A CN 201810010047A CN 108231902 A CN108231902 A CN 108231902A
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 7
- 230000009467 reduction Effects 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 238000009825 accumulation Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 7
- 230000009471 action Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101100207343 Antirrhinum majus 1e20 gene Proteins 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
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- 239000004576 sand Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
Abstract
The invention discloses one kind can improve device pressure resistance, reduce more stacked layer power devices with series connection slot grid structure than conducting resistance；The grid of the structure employs trench structure, and slot grid extend to oxygen buried layer, and longitudinal conducting channel is formd with p traps, simultaneously, slot grid form longitudinal electron accumulation layer with drift region, and current conducting areas is made significantly to be extended longitudinally, device is reduced and compares conducting resistance；Drift region includes the buried layer of multiple p-types that are connected with vertical grid, and device top uses surface polysilicon oxide layer structure, forms the cascade multiple device parallel-connection structures of grid；There are more stacked layer power devices of series connection slot grid structure using this, the breakdown voltage and reduction for effectively increasing device compare conducting resistance so that electric field distribution is more uniform, forms multiple cascade conducting electric currents.
Description
Technical field
The present invention relates to semiconductor power device technology field, especially a kind of more lamination work(with series connection slot grid structure
Rate device.
Background technology
It is well-known：Power integrated circuit (Power Integrated Circuit), collection signal processing, sensing are protected
Shield, power transmission techniques have been quickly grown, in weaponry, power electronics, boat in one since last century the eighties generate
Empty space flight, FPD driving and other new high-tech industries have extremely wide application.PIC is one in integrated circuit
Important branch compared with discrete device, not only has great advantage in terms of performance, power consumption and stability, and for reduce into
Originally, reducing volume and weight has very big meaning.Therefore, domestic and international expert and scholar this has been put into it is great concern and
In-depth study.
Power semiconductor mainly includes power diode, thyristor, power MOSFET, Power Insulated Gate Bipolar crystal
Manage (IGBT) and broad stopband power semiconductor etc..Wherein except thyristor is in the application of superpower field, power MOS and IGBT
It is two kinds of main power devices.Since wide-band gap material broad-band gap, high saturation drift velocity, high critical breakdown electric field etc. are prominent
Advantage, with silicon carbide monocrystal growth technology and the continuous maturation of gallium nitride heterojunction growth technology, broad stopband of new generation
Power semiconductor also obtains extensive concern and the further investigation of domestic and international semiconductor company and research institution.
The key of power semiconductor design is the key characteristics parameters such as optimization high voltage, on-state voltage drop, high-speed switch
Between compromise.It improves power density and reduces the developing direction that loss is all power semiconductor all the time, and the former
Pressure resistance with power device improves closely related.
Invention content
There is provided a kind of raisings that can solve power device to reduce pressure ratio for the technical problems to be solved by the invention
More stacked layer power devices with series connection slot grid structure of conducting resistance.
The technical solution adopted by the present invention to solve the technical problems is：More stacked layer power devices with series connection slot grid structure
Part, including from top to bottom set gradually drift region, buried layer, substrate；N is provided on the drift region+Drain region, drain electrode, grid
Electrode, source electrode, N+Contact zone and P+Source region；
Vertical grid are provided on the outer surface of the drift region side；The vertical grid form vertical for polysilicon and vertical oxide layer
To slot grid；The slot grid extend to buried layer；P traps are provided in the drift region；The slot grid form longitudinal conduction with p traps
Raceway groove；
The buried layer of lateral p-type being connected with vertical grid is provided in the drift region, the buried layer of the p-type at least has
Two；And the buried layer of p-type forms devices in parallel structure with vertical grid.
Further, there are three the buried layer tools for stating p-type is specially：The buried layer of first p-type, the buried layer of the second p-type and
The buried layer of three p-types；The buried layer of the buried layer of first p-type, the buried layer of the second p-type and third p-type forms parallel device with vertical grid
Part structure.
Further, buried layer two is provided with above the drift region, two top of buried layer is provided with surface texture.
Further, the spacing between the buried layer of two neighboring p-type is identical.
Further, it is equal with the lateral length of the buried layer for the p-type that vertical grid are connected.
Further, the even structure doping concentration for the buried layer of p-type being connected with vertical grid.
Further, the concentration of the buried layer of each p-type being connected with vertical grid is equal.
Further, the drift region between the buried layer of first p-type and the buried layer of the second p-type is the first drift region；Institute
It is the second drift region to state the drift region between the buried layer of the second p-type and the buried layer of third p-type；The buried layer of the third p-type is with burying
Drift region between layer is third drift region；First drift region, the second drift region, the concentration of third drift region are equal.
The beneficial effects of the invention are as follows：It is of the present invention have series connection slot grid structure more stacked layer power devices relative to
Existing power device has the following advantages：
1st, have in more stacked layer power device architectures of series connection slot grid structure, be conducive to obtain higher breakdown voltage.
2nd, have in more stacked layer power device architectures of series connection slot grid structure, in break-over of device, form series connection gate device
Parallel-connection structure forms multiple cascade conducting electric currents, this is conducive to the output current and power density that improve device.
3rd, have in more stacked layer power device architectures of series connection slot grid structure, surface polysilicon oxide layer structure increases
Device drift region exhausts, this is conducive to the concentration for increasing drift region, and conducting resistance is compared in reduction.
4th, have in more stacked layer power device architectures of series connection slot grid structure, using multiple P-buried and cannelure grid phase
Even, which increases the depletion actions of drift region.
5th, have in more stacked layer power device architectures of series connection slot grid structure, using multiple P-buried and cannelure grid phase
Even, multiple Diode series structures are formed, reduce the leakage current of device.
6th, have in more stacked layer power device architectures of series connection slot grid structure, realize multiple devices in parallel structures, so as to
It enough further reduces device size and improves integrated level.
Description of the drawings
Fig. 1 is the structure diagram of the power device of conventional N-type slot grid structure；
Fig. 2 is a kind of more stacked layer power device architecture schematic diagrames with series connection slot grid structure proposed by the present invention；
Fig. 3 is a kind of more stacked layer power devices and conventional type power device with series connection slot grid structure proposed by the present invention
Drain terminal longitudinal electric field compare figure；
Fig. 4 is a kind of conventional type slot grid structure power device equipotential lines distribution map proposed by the present invention；
Fig. 5 is a kind of more stacked layer power device equipotential lines distribution maps with series connection slot grid structure proposed by the present invention；
Fig. 6 is a kind of power device current line point with three layers of more laminated construction of p type buried layer slot grid proposed by the present invention
Butut；
Fig. 7 is a kind of hitting for more multiple p type buried layers of stacked layer power device with series connection slot grid structure proposed by the present invention
Wear voltage drift area concentration profile；
Fig. 8 is the structure diagram of cross section JFP-NFL LDMOS in the prior art；
It is indicated in figure：1- substrates, 2- buried layers, 3- drift regions, 4-N+Drain region, 5- drain electrodes, 6- gate electrodes, 7- source electrodes,
8-N+Contact zone, 9-P+Source region, 10-P traps, 11- polysilicons, 12- indulge oxide layer, the buried layer of the first p-types of 13-, and 14- first drifts about
Area, the buried layer of the second p-types of 15-, the second drift regions of 16-, the buried layer of 17- third p-types, 18 third drift regions, 19- surface textures,
20- buried layers two, 21- media slots one, 22- media slots two.
Specific embodiment
The present invention is further described with reference to the accompanying drawings and examples.
As shown in Figure 1, it is of the present invention have series connection slot grid structure more stacked layer power devices, including from top to bottom according to
The drift region 3 of secondary setting, buried layer 2, substrate 1；N is provided on the drift region 3+Drain region 4, drain electrode 5, gate electrode 6, source electrode
7、N+Contact zone 8 and P+Source region 9；
Vertical grid are provided on the outer surface of 3 side of drift region；The vertical grid are 12 shape of polysilicon 11 and vertical oxide layer
Into longitudinal direction slot grid；The slot grid extend to buried layer 2；P traps 10 are provided in the drift region 3；The slot grid and 10 shape of p traps
Into longitudinal conducting channel；
The buried layer of lateral p-type being connected with vertical grid is provided in the drift region 3, the buried layer of the p-type at least has
There are two；And the buried layer of p-type forms devices in parallel structure with vertical grid.
Further, there are three be specially for the buried layer tool of the p-type：The buried layer 13 of first p-type, the buried layer 15 of the second p-type
And the buried layer 17 of third p-type；The buried layer 17 of the buried layer 13 of first p-type, the buried layer 15 of the second p-type and third p-type with
Vertical grid form devices in parallel structure.
Further, by being provided with buried layer 2 20 in the top of the drift region 3,2 20 top of buried layer is provided with
Surface texture 19；The structure of isolation is both provided with from the surface of more stacked layer power devices is caused；Wherein substrate 1 and surface texture 19
The isolation of the similar oxide layer such as polysilicon oxide layer structure or polycrystalline silicon, the metal with similar structure may be used
Structure.Therefore, device depletion action is enhanced by surface texture, improves drift region concentration, reduced than conducting resistance, formed more
A device is in parallel.
Spacing between the buried layer of two neighboring p-type can be the same or different, it is preferred that two neighboring p-type is buried
Spacing between layer is identical, so as to improve drift region concentration, reduces than conducting resistance, reduces leakage current.
With the lateral length of the buried layer of p-type that vertical grid are connected can it is equal can not also be equal, it is preferred that be connected with vertical grid
P-type buried layer lateral length it is equal.Drift region concentration is improved, is reduced than conducting resistance, it is simple for process.
Further, the even structure doping concentration for the buried layer of p-type being connected with vertical grid.
Further, the concentration of the buried layer of each p-type being connected with vertical grid is equal.
Further, the drift region 3 between the buried layer 15 of 13 and second p-type of buried layer of first p-type is the first drift
Area 14；Drift region 3 between the buried layer 15 of second p-type and the buried layer 17 of third p-type is the second drift region 16；The third
Drift region 3 between the buried layer 17 of p-type and buried layer 2 is third drift region 18；First drift region 14, the second drift region 16,
The concentration of third drift region 18 is equal；Therefore 3 concentration of drift region can be improved, conducting resistance is compared in reduction.Form multiple devices simultaneously
Connection, the structure of grid series connection, forms multiple cascade conducting electric currents, reduces leakage current.
Further, the media slot 2 22 for extending to the longitudinal direction in drift region 3, the medium are provided on the buried layer 2
Slot 2 22 is transversely uniformly distributed.The media slot 1 extended in drift region 3, the medium are provided on the buried layer 2 20
Slot 1 is transversely uniformly distributed；Therefore the breakdown voltage of device can be improved.
In the prior art, cross section JFP-NFL LDMOS as shown in Figure 8, have LVD junction fields plate (JFP) on surface and
The P of one heavy doping NFL+.In drift region, there are one the length that P buried layers source and LBP are P buried layers further below.Nb, TJFPAnd LpIt is
The doping concentration in P areas, thickness and length in JFP.NdAnd NsubIt is the doping concentration of N-drift and P-sub.TsAnd TwIt is N-
The thickness of drift and the thickness of P-substrate.The JFP of the structure, electric field concentrate on drain electrode side.Secondly, one additional
Vertical diode D2Composition NFL and P-sub increases longitudinal breakdown voltage by reversely exhausting.Third, similar super junction, along
Drain-to-source gradually exhausts so that electric field approximately linear is distributed, and the distribution of LVD JFP smooth surfaces electric field increases breakdown potential
Pressure.Further, since JFP is to drift region N-drift depletion actions, RonReduce, increase drift region concentration.
More stacked layer power devices of the present invention with series connection slot grid structure are using surface texture, in surface texture
Electron inversion is formed, media slot collects hole, improves the electric field distribution of an oxygen layer, increases the depletion action to drift region,
Drift region concentration is increased, reduces conducting resistance.
In conclusion more stacked layer power devices with series connection slot grid structure of the present invention, in break-over of device, by
The buried layer 15 of buried layer 13, the second p-type in first p-type and the buried layer 17 of third p-type form devices in parallel knot with vertical grid
Structure.So as to be conducive to improve the output current and power density of device.
This has in more stacked layer power device architectures of series connection slot grid structure, due to surface polysilicon oxide layer structure, increases
Exhausting for device drift region is added, this is conducive to the concentration for increasing drift region, and conducting resistance is compared in reduction.
This has in more stacked layer power device architectures of series connection slot grid structure, using multiple P-buried and cannelure grid phase
Even, which increases the depletion actions of drift region.
This has in more stacked layer power device architectures of series connection slot grid structure, using multiple P-buried and cannelure grid phase
Even, multiple Diode series structures are formed, reduce the leakage current of device.
This has in more stacked layer power device architectures of series connection slot grid structure, realizes multiple devices in parallel structures, so as to
It enough further reduces device size and improves integrated level.
Embodiment 1：
As shown in Fig. 2, in figure, 1- substrates, 2- buried layers, 3- drift regions, 4-N+Drain region, 5- drain electrodes, 6- gate electrodes, 7- sources
Electrode, 8-N+Contact zone, 9-P+Source region, 10-P traps, 11- polysilicons, 12- indulge oxide layer, the buried layer of the first p-types of 13-, 14- first
Drift region, the buried layer of the second p-types of 15-, the second drift regions of 16-, the buried layer of 17- third p-types, 18 third drift regions, 19- surfaces knot
Structure, 20- buried layers two, 21- media slots one, 22- media slots two.
Source electrode 7, gate electrode 6 and drain electrode 5 are arranged on the intersection of drift region 3 and buried layer 2 20, wherein 7 He of source electrode
Gate electrode 6 is located at 3 left side of drift region, and drain electrode 5 is located at the right side of drift region 3.P+ source regions 9, p-well 10, polysilicon 11 and buried layer
2 20 lower surface contact.
In the present embodiment, it is silica dioxide medium to indulge field oxygen layer 12.The concentration of drift region 3 is set as 5.4e15.P-well 10
Concentration be set as 1e17.N+Drain region 4, N+Contact zone 8, P+The concentration of source region 9 is disposed as 1e20, and the concentration of the buried layer of p-type is equal
For 3e16 and it is equidistant.The height of media slot 1 and media slot 2 22 is that 0.5um width is 0.5um, is equidistantly
0.5um.When 5 additional high voltages of drain electrode, and gate electrode 6, source electrode 7 and Substrate ground, i.e. device are in reverse blocking
State.
A kind of power device and Fig. 1 with three layers of more laminated construction of p type buried layer slot grid proposed by the present invention shown in Fig. 2
The breakdown voltage of shown conventional type power device is compared.Structure proposed by the present invention has reached 398V, traditional slot grid knot
Structure breakdown voltage is 278V, improves 43.2%, the voltage endurance capability of device is significantly improved.It is 22.59m than conducting resistance
Ω·cm2, the ratio conducting resistance 23.86m Ω cm of traditional slot grid structure2, decrease.
Claims (8)
1. with series connection slot grid structure more stacked layer power devices, including from top to bottom set gradually drift region (3), buried layer
(2), substrate (1)；N is provided on the drift region (3)+Drain region (4), drain electrode (5), gate electrode (6), source electrode (7), N+It connects
Touch area (8) and P+Source region (9)；
It is characterized in that：Vertical grid are provided on the outer surface of drift region (3) side；The vertical grid is polysilicons (11) and indulge
The slot grid of longitudinal direction that oxide layer (12) is formed；The slot grid extend to buried layer (2)；P traps are provided in the drift region (3)
(10)；The slot grid form longitudinal conducting channel with p traps (10)；
The buried layer of lateral p-type being connected with vertical grid is provided in the drift region (3), the buried layer of the p-type at least has
Two；And the buried layer of p-type forms devices in parallel structure with vertical grid.
2. more stacked layer power devices with series connection slot grid structure according to claim 1, it is characterised in that：The p-type
Buried layer tool there are three be specially：Buried layer (13), the buried layer (15) of the second p-type and the buried layer of third p-type of first p-type
(17)；The buried layer (17) of the buried layer (13) of first p-type, the buried layer (15) of the second p-type and third p-type is formed simultaneously with vertical grid
Join device architecture.
3. more stacked layer power devices with series connection slot grid structure according to claim 2, it is characterised in that：The drift
Buried layer two (20) is provided with above area (3), surface texture (19) is provided with above the buried layer two (20).
4. more stacked layer power devices with series connection slot grid structure according to claim 3, it is characterised in that：It is two neighboring
Spacing between the buried layer of p-type is identical.
5. more stacked layer power devices with series connection slot grid structure according to claim 4, it is characterised in that：With vertical grid phase
The lateral length of the buried layer of p-type even is equal.
6. more stacked layer power devices with series connection slot grid structure according to claim 4, it is characterised in that：With vertical grid phase
The even structure doping concentration of the buried layer of p-type even.
7. more stacked layer power devices with series connection slot grid structure according to claim 4, it is characterised in that：With vertical grid phase
The concentration of the buried layer of each p-type even is equal.
8. more stacked layer power devices with series connection slot grid structure according to claim 4, it is characterised in that：Described first
Drift region (3) between the buried layer (13) of p-type and the buried layer (15) of the second p-type is the first drift region (14)；Second p-type
Drift region (3) between buried layer (15) and the buried layer (17) of third p-type is the second drift region (16)；The buried layer of the third p-type
(17) drift region (3) between buried layer (2) is third drift region (18)；First drift region (14), the second drift region
(16), the concentration of third drift region (18) is equal.
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|---|---|---|---|---|
| US20020132406A1 (en) * | 2000-11-27 | 2002-09-19 | Power Integrations, Inc. | High-voltage transistor with JFET conduction channels |
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| CN103579351A (en) * | 2013-11-22 | 2014-02-12 | 电子科技大学 | LDMOS (laterally diffused metal oxide semiconductor) device provided with super-junction buried layer |
| CN104218088A (en) * | 2014-07-14 | 2014-12-17 | 桂林电子科技大学 | SOI pressure-resistant structure based on folded drift region and power component |
| CN104992977A (en) * | 2015-05-25 | 2015-10-21 | 上海华虹宏力半导体制造有限公司 | Nldmos device and manufacturing method thereof |
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| US20020132406A1 (en) * | 2000-11-27 | 2002-09-19 | Power Integrations, Inc. | High-voltage transistor with JFET conduction channels |
| CN102148251A (en) * | 2011-01-10 | 2011-08-10 | 电子科技大学 | Semiconductor on insulator (SOI) lateral metal-oxide-semiconductor field-effect-transistor (MOSFET) device and integrated circuit |
| CN103579351A (en) * | 2013-11-22 | 2014-02-12 | 电子科技大学 | LDMOS (laterally diffused metal oxide semiconductor) device provided with super-junction buried layer |
| CN104218088A (en) * | 2014-07-14 | 2014-12-17 | 桂林电子科技大学 | SOI pressure-resistant structure based on folded drift region and power component |
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