CN108230975B - Display panel and detection method thereof - Google Patents

Display panel and detection method thereof Download PDF

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Publication number
CN108230975B
CN108230975B CN201810163706.8A CN201810163706A CN108230975B CN 108230975 B CN108230975 B CN 108230975B CN 201810163706 A CN201810163706 A CN 201810163706A CN 108230975 B CN108230975 B CN 108230975B
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pixel detection
reset
detection circuit
line
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CN108230975A (en
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郑智仁
刘伟
王鹏鹏
丁小梁
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a display panel and a detection method of the display panel, the display panel comprises a plurality of switch time sequence units and a plurality of reset time sequence units, in the working process of the display panel, the control unit can control the switch time sequence units to work one by one, and controlling the reset of each time sequence unit to work one by one, outputting the electric signals generated by the pixel detection circuits of each row connected with the reset unit in the reset stage and the sampling stage when corresponding to the components of each pixel detection circuit, moreover, the length of time for each pixel detection circuit group to output the electric signals generated by the pixel detection units in each row in the reset phase is short, therefore, the electrical signals generated by the pixel detection units scanned in the first stage in the integration stage and the electrical signals generated by the pixel detection units scanned in the second stage in each pixel detection circuit group can be prevented from being output simultaneously, and the accuracy of the electrical signals generated by the pixel detection units can be improved.

Description

Display panel and detection method thereof
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a detection method of the display panel.
Background
As shown in fig. 1, there is provided a display panel capable of displaying an image according to an optical signal in the related art. The display panel includes: the pixel detection units are arranged at the positions where the plurality of selection switch lines gate line, the plurality of reading lines read line, the plurality of reset lines reset line and the plurality of reading lines read line cross, the pixel detection units on the same row are connected with the same selection switch line gate line and the same reset line, the pixel detection units on the same column are connected with the same reading line read line, and the pixel detection units can accumulate optical signals and generate electric signals according to the accumulated optical signals. In order to reduce noise of an electrical signal output by each pixel detection unit, a Correlated Double Sampling (CDS) technology is generally adopted in the conventional pixel detection unit, that is, each pixel detection unit sequentially includes a reset stage, an integration stage and a sampling stage, in the reset stage, a reset line inputs a reset signal to the pixel detection unit to reset the electrical signal generated by the pixel detection unit, and a gate line is selected to input a start signal to the pixel detection unit, so that the pixel detection unit outputs the reset electrical signal through a corresponding read line; in the sampling phase, the selection switch line gate line inputs a turn-on signal to the pixel detection unit, so that the pixel detection unit outputs an electric signal generated in the integration period through the corresponding read line. Because the noise level of the electric signal output by the pixel detection unit in the reset stage is equivalent to that of the electric signal output by the pixel detection unit in the sampling stage, the noise problem of the electric signal output by the pixel detection unit can be solved by subtracting the electric signal output by the pixel detection unit in the reset stage and the electric signal output by the pixel detection unit in the sampling stage.
In order to improve the detection speed of each row of pixel detection units, each row of pixel detection units adopt a rolling type time sequence control mode. Referring to fig. 1 and 2, a rolling type timing control method for each row of pixel detecting units will be described in detail by taking an example in which a display panel includes six rows of pixel detecting units. In particular, at T1In the period, reset line1 resets the electric signals on the pixel detection units in the first row, and gate line1 outputs the reset electric signals on the pixel detection units in the first row through the corresponding read line, and the reset line is used for reading the electric signals at T2In the period, rest line2 resets the electric signals on the pixel detection units in the second row, and gate line2 outputs the reset electric signals on the pixel detection units in the second row, at this time, the pixel detection units in the first row accumulate optical signals; in the same manner, the electric signals on the pixel detection units of the third, fourth, fifth and sixth rows are reset by rest line3, rest line4, rest line5 and rest line6, respectively, and the reset electric signals on the pixel detection units of the third, fourth, fifth and sixth rows are passed through the corresponding pixel detection units by gate line3, gate line4, gate line5 and gate line6Reading the line read line output and causing the pixel detection units of the second, third, fourth, fifth, and sixth rows to start accumulating optical signals from after the reset phase; while the pixel detection units of the first row accumulate light signals for a duration of Tint (i.e., at T)5Time period), the gate line1 outputs the electrical signal generated by the pixel detection units of the first row during the integration phase through the corresponding read line, while the pixel detection units of the second row accumulate the light signal for a time duration of Tint (i.e., at T)6Period), the gate line2 outputs the electric signals generated by the pixel detection units of the second row in the integration period through the corresponding read lines; in the same manner, the electric signals generated by the pixel detection units in the third, fourth, fifth and sixth rows in the integration phase are output through the corresponding read lines by the gate lines 3, 4, 5 and 6, respectively.
However, when all the pixel detection units in each row do not output the electrical signal generated in the reset phase through the corresponding read line, the pixel detection unit that has completed the optical signal reset starts to output the electrical signal generated in the integration period through the corresponding read line, and the electrical signal generated in the integration period by the pixel detection unit of the corresponding previous scan and the electrical signal generated in the reset phase by the pixel detection unit of the subsequent scan are simultaneously output to the same read line, which affects the accuracy of the display panel to acquire the electrical signal generated by the pixel detection unit of the subsequent scan in the integration period, and accordingly causes an abnormality in the display image displayed by the display panel. Although the above technical problem can be solved by increasing the duration Tint of the pixel detection unit in the integration phase, since the light signal that can be accumulated by the pixel detection unit has a certain saturation value, that is, the duration Tint of the pixel detection unit in the integration phase has a maximum value, when the number of rows of the pixel detection unit is large, the above technical problem cannot be solved by increasing the duration Tint of the pixel detection unit in the integration phase.
Disclosure of Invention
The present invention provides a display panel and a method for detecting the display panel, which at least partially solve the problem of the conventional display panel that the accuracy of acquiring the electrical signal output by the detection pixel unit in the integration stage is poor.
In order to achieve the above object, the present invention provides a display panel including a plurality of selection switch lines, a plurality of readout lines, and a plurality of reset lines, the plurality of selection switch lines and the plurality of reset lines being arranged to cross the plurality of readout lines, and defining pixel detection units at the crossing positions, wherein each of the pixel detection units includes: the display panel is divided into M pixel detection circuit groups, and each pixel detection circuit group comprises a plurality of rows of pixel detection circuits; the display panel further includes: the device comprises a control unit, M switch time sequence units and M reset time sequence units; m is more than or equal to 2; wherein,
each of the switch timing units is connected to the selection switch line to which each of the pixel detection circuits of one of the pixel detection circuit groups is connected; each reset time sequence unit is connected with the reset line connected with each pixel detection circuit of one pixel detection circuit group; m of the switch timing units and M of the reset timing units are connected to the control unit, wherein,
the control unit is used for controlling the M switch time sequence units to work one by one; controlling the M reset time sequence units to work one by one;
each reset time sequence unit is used for inputting reset signals to the reset lines connected with the reset time sequence unit row by row in a reset stage so that the corresponding reset unit resets the charges accumulated by the corresponding photosensitive unit through the reset signals;
each switch time sequence unit is used for inputting a starting signal to each selection switch line connected with the switch time sequence unit line by line in a resetting stage so as to open the corresponding selection switch unit, and outputting a generated electric signal through the corresponding reading line according to the electric charge of the reset photosensitive unit of the corresponding voltage generation unit; and in a sampling stage, inputting a starting signal to each selection switch line connected with the switch time sequence unit line by line to open the corresponding selection switch unit, and outputting a generated electric signal through the corresponding reading line according to the electric charge accumulated by the voltage generation unit in the integration stage.
Preferably, the sum of the duration of the reset phase of each of the pixel detection circuits in each of the pixel detection circuit groups is less than or equal to the duration of the integration phase of any one of the pixel detection circuits in the pixel detection circuit group.
Preferably, the (N + 1) th switch timing unit is connected with each selection switch line in the (N + 1) th pixel detection circuit group and is connected with part of the selection switch lines in the nth pixel detection circuit group;
the starting time from the completion time of the reset stage of the last row of the pixel detection circuits in the Nth pixel detection circuit group to the sampling stage of the first row of the pixel detection circuits in the Nth pixel detection circuit group is a first period of time;
the control unit is further configured to, in the first period, input, by the N +1 th switch timing unit, a turn-on signal to some of the selection switch lines in the nth pixel detection circuit group connected thereto, line by line, so as to turn on the corresponding selection switch unit, and output, by the corresponding voltage generation unit, an electrical signal generated by the photosensitive unit in the first period through the corresponding readout line; wherein N is more than or equal to 1; the sum of the duration of the reset phase of each pixel detection circuit in each pixel detection circuit group is less than the duration of the integration phase of any one pixel detection circuit in the pixel detection circuit group, and the scanning duration of part of the selection switch lines in the nth pixel detection circuit group connected with the N +1 th switch timing sequence unit is less than or equal to the duration of the first time period.
Preferably, the (N + 1) th switching timing unit is connected with each selection switch line in the (N + 1) th pixel detection circuit group and is connected with part of the selection switch lines in the (N + 1) th pixel detection circuit group;
the sampling phase completion time of the last row of the pixel detection circuits in the Nth pixel detection circuit group to the starting time of the reset phase of the first row of the pixel detection circuits in the (N + 1) th pixel detection circuit group is a second time period;
the control unit is further configured to, in the second time period, input, by the N +1 th switch timing unit, an on signal to some of the selection switch lines in the nth pixel detection circuit group connected thereto, line by line, so as to turn on the corresponding selection switch unit, and output, by the corresponding voltage generation unit, an electrical signal generated by the photosensitive unit in the second time period through the corresponding read line; wherein N is more than or equal to 1; the scanning duration of part of the selection switch lines in the nth pixel detection circuit group connected with the (N + 1) th switch timing unit is less than or equal to the duration of the second period.
Preferably, M switch timing units and M reset timing units are integrated in the same timing control chip.
Preferably, the display panel further includes a plurality of operational amplifiers, each of which is connected to one of the readout lines and amplifies an electrical signal output from each of the pixel detection circuits.
Preferably, the reset unit includes a first transistor, wherein a first electrode of the first transistor is connected to a reset voltage terminal, a second electrode of the first transistor is connected to the light sensing unit and the voltage generating unit, and a control electrode of the first transistor is connected to the reset line;
the photosensitive unit comprises a photodiode, wherein a first pole of the photodiode is connected with the voltage generation unit and the reset unit, and a second pole of the photodiode is connected with a reverse bias voltage end;
the voltage generating unit comprises a second transistor, wherein a first pole of the second transistor is connected with a voltage input end, a second pole of the second transistor is connected with the selection switch unit, and a control pole of the second transistor is connected with the photosensitive unit and the resetting unit;
the selection switch unit includes a third transistor, wherein a first pole of the third transistor is connected to the voltage generation unit, a second pole of the third transistor is connected to the read line, and a control pole of the third transistor is connected to the selection switch line.
The invention also provides a detection method of the display panel, which is applied to the display panel and comprises the following steps:
a step of controlling the M switching timing units and the M reset timing units by a control unit; and controlling the pixel detection circuit connected with the switch timing unit to work through the switch timing unit and the reset timing unit;
the step of controlling the pixel detection circuit connected with the switching timing unit and the reset timing unit to work through the switching timing unit and the reset timing unit comprises the following steps:
a reset stage, in which the reset time sequence unit inputs reset signals to the reset lines connected thereto line by line, so that the corresponding reset units reset the charges accumulated by the corresponding photosensitive units through the reset signals, and the switch time sequence unit inputs turn-on signals to the selection switch lines connected thereto line by line, so that the corresponding selection switch units are turned on, and the corresponding voltage generation units output the generated electrical signals through the corresponding read lines according to the charges reset by the photosensitive units;
and in the sampling stage, a switch time sequence unit inputs turn-on signals to each selection switch line connected with the switch time sequence unit line by line so as to turn on the corresponding selection switch unit, and the voltage generation unit outputs generated electric signals through the corresponding reading line according to the electric charges accumulated by the photosensitive unit in the integration stage.
Preferably, the step of controlling the pixel detection circuit connected to the switching timing unit and the reset timing unit to operate by the switching timing unit and the reset timing unit further includes:
in a first period, inputting a turn-on signal to some of the selection switch lines in the nth pixel detection circuit group connected thereto row by row through the (N + 1) th switch timing sequence unit to turn on the corresponding selection switch unit, and outputting an electric signal generated by the corresponding voltage generation unit in the first period according to the photosensitive unit through the corresponding reading line; wherein N is more than or equal to 1; the sum of the duration of the reset phase of each pixel detection circuit in each pixel detection circuit group is less than the duration of the integration phase of any one pixel detection circuit in the pixel detection circuit group, and the scanning duration of part of the selection switch lines in the nth pixel detection circuit group connected with the N +1 th switch timing sequence unit is less than or equal to the duration of the first time period.
Preferably, the step of controlling the pixel detection circuit connected to the switching timing unit and the reset timing unit to operate by the switching timing unit and the reset timing unit further includes:
in a second time period, inputting turn-on signals to part of the selection switch lines in the nth pixel detection circuit group connected with the selection switch line row by row through the (N + 1) th switch timing sequence unit so as to turn on the corresponding selection switch unit, and outputting the corresponding voltage generation unit through the corresponding reading line according to the electric signal generated by the photosensitive unit in the second time period; wherein N is more than or equal to 1; the scanning duration of part of the selection switch lines in the nth pixel detection circuit group connected with the (N + 1) th switch timing unit is less than or equal to the duration of the second period.
The invention has the following beneficial effects:
the invention provides a display panel and a detection method of the display panel, wherein the display panel comprises a plurality of switch time sequence units and a plurality of reset time sequence units, and each switch time sequence unit and each reset time sequence unit are connected with a pixel detection circuit group. In the working process of the display panel, the control unit can control the switch time sequence units to work one by one and control the reset time sequence units to work one by one, corresponding pixel detection circuit groups output electric signals generated by pixel detection circuits of all rows connected with the pixel detection circuit groups in the reset stage and the sampling stage in a time sharing manner, moreover, the number of rows of the pixel detection circuits connected with each pixel detection circuit group is small, and the corresponding pixel detection circuit groups have shorter duration sum of the pixel detection units in the reset stage, so that after all the electric signals generated by the pixel detection units in all rows of the pixel detection circuit groups in the reset stage are output, the electric signals generated by the pixel detection units in the pixel detection circuit groups in the integration period are output through the corresponding reading lines, and accordingly, the electric signals generated by the pixel detection units scanned in the first in the integration stage in each pixel detection circuit group in the later scanning stage and the electric signals generated by the later scanning in the integration stage can be avoided The electrical signals generated by the pixel scanning detection units in the reset stage are output simultaneously, so that the accuracy of the display panel for acquiring the electrical signals generated by the detection pixel units in the integration stage can be improved, and the accuracy of the display image generated by the display panel can be correspondingly improved.
Drawings
FIG. 1 is a schematic structural diagram of a conventional display panel;
FIG. 2 is a schematic diagram of a working timing sequence of a conventional display panel;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the pixel detection circuit shown in FIG. 3;
fig. 5 is a schematic diagram of a working timing sequence of the display panel according to the embodiment of the invention.
Illustration of the drawings:
1. reset unit 2, voltage generation unit 3, selection switch unit 4, photosensitive unit
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, a display panel and a detection method of the display panel provided by the present invention are described in detail below with reference to the accompanying drawings.
Example 1
Embodiment 1 of the present invention provides a display panel, as shown in fig. 3 and 4, including: a plurality of selection switch lines gate line, a plurality of readout lines, and a plurality of reset lines, the plurality of selection switch lines gate line and the plurality of readout lines being arranged to intersect, and defining pixel detection units at the intersection positions, wherein each pixel detection unit includes: the reset unit 1, the voltage generation unit 2, the selection switch unit 3 and the photosensitive unit 4, the selection switch unit 3 in the pixel detection units on the same row is connected with the same selection switch line gate line, the reset unit 1 in the pixel detection units on the same row is connected with the same reset line rest line, and the selection switch unit 3 in the pixel detection units on the same column is connected with the same reading line read line.
The display panel provided by the embodiment of the invention is divided into M pixel detection circuit groups, and each pixel detection circuit group comprises a plurality of rows of pixel detection circuits; the display panel further includes: the device comprises a control unit, M switch time sequence units and M reset time sequence units; m is more than or equal to 2. Each switch time sequence unit is connected with a selection switch line connected with each pixel detection circuit of one pixel detection circuit group; each reset timing unit is connected to a reset line connected to each pixel detection circuit of one pixel detection circuit group.
The M switch time sequence units and the M reset time sequence units are connected with the control unit, and the control unit is used for controlling the M switch time sequence units to work one by one; and controlling the M reset time sequence units to work one by one.
Each reset timing sequence unit is used for inputting a reset signal to a reset line connected with the reset timing sequence unit row by row in a reset stage, so that the corresponding reset unit 1 resets the charges accumulated by the corresponding photosensitive unit 4 through the reset signal.
Each switch time sequence unit is used for inputting a starting signal to each selection switch line connected with the switch time sequence unit line by line in a resetting stage so as to open the corresponding selection switch unit 3, and outputting a generated electric signal through a corresponding reading line according to the electric charge reset by the voltage generating unit 2 according to the photosensitive unit 4; and in the sampling phase, inputting a starting signal to each selection switch line connected with the switch timing sequence unit line by line to open the corresponding selection switch unit 3, and outputting the generated electric signal through the corresponding reading line according to the electric charge accumulated by the voltage generating unit 2 in the integration phase according to the photosensitive unit 4.
In the embodiment of the present invention, the display panel includes six selection switch lines, six read lines, and four reset lines, and the corresponding pixel detection units are arranged in a matrix of six rows by four columns.
In order to more clearly describe the structure of the display panel in the present embodiment, M is 2; the display panel will be specifically described.
As shown in fig. 3, the display panel is divided into two pixel detection circuit group groups, the group1 includes pixel detection circuits of a first row, a second row and a third row, and the group2 includes pixel detection circuits of a fourth row, a fifth row and a sixth row. The display panel comprises two switch time sequence units and two reset time sequence units, wherein the first switch time sequence unit is connected with a selection switch line gate line connected with each row of pixel detection circuits in group1, the second switch time sequence unit is connected with a selection switch line gate line connected with each row of pixel detection circuits in group2, namely the first switch time sequence unit is connected with gate line1, gate line2 and gate line3, and the second switch time sequence unit is connected with gate line4, gate line5 and gate line 6. The first reset timing unit is connected to a reset line rest line to which each row of pixel detection circuits in group1 is connected, the second reset timing unit is connected to a reset line rest line to which each row of pixel detection circuits in group2 is connected, that is, the first reset timing unit is connected to reset line1, reset line2 and reset line3, and the second reset timing unit is connected to reset line4, reset line5 and reset line 6.
It should be noted that, the present invention is described by taking an example in which each pixel detection circuit group includes pixel detection circuits with the same number of rows. It is of course also possible that different groups of pixel detection circuits comprise pixel detection circuits with different numbers of rows, respectively.
In the working process of the display panel, the control unit can control the first switch time sequence unit and the second switch time sequence unit to work one by one and control the first reset time sequence unit and the second reset time sequence unit to work one by one. That is, after one of the first switch timing unit and the second switch timing unit finishes working, the other one does work; after one of the first reset timing unit and the second reset timing unit is completed, the other one is operated. The following description will take the first switch timing unit and the first reset timing unit as an example.
As shown in fig. 5, in the process of the operation of the first switching timing unit and the first reset timing unit, in the reset stage, the first reset timing unit performs a progressive scan on reset line1, reset line2 and reset line3, and the first switching timing unit performs a progressive scan on gate line1, gate line2 and gate line 3. Specifically, when the first reset timing unit inputs a reset signal to the reset line1, the reset unit 1 in the pixel detection circuit connected to the reset line1 can reset the charges accumulated in the light sensing unit 4 connected thereto, at this time, the first switch timing unit inputs an on signal to the gate line1, and the selection switch unit 3 in the pixel detection circuit connected to the gate line1 can output the generated electric signal through the corresponding read line according to the charges reset on the light sensing unit 4 by the voltage generation unit 2 connected thereto; in the same manner, the electric charges accumulated in the light sensing units 4 in the pixel detection circuits connected to the rest line2 and the rest line3 are sequentially reset, and the electric signals generated by the voltage generation units 2 in the pixel detection circuits connected to the gate line2 and the gate line3 are sequentially output through the corresponding read lines according to the electric charges reset on the light sensing units 4.
Thereafter, in the sampling phase, the first switch timing unit performs progressive scanning on the gate line1, the gate line2, and the gate line 3. It should be noted that each row of pixel detection circuits accumulates light signals from the reset phase to the sampling phase (i.e., the integration phase) in the light sensing units 4 in the row of pixel detection circuits, and generates corresponding electrical signals. Specifically, when the first switching timing unit inputs an on signal to the gate line1, the selection switch unit 3 in the first row of pixel detection circuits can output the generated electric signal through the corresponding read line from the electric charge accumulated by the voltage generation unit 2 connected thereto in the integration phase of the light sensing unit 4; in the same manner, the voltage generation units 2 in the pixel detection circuits of the second and third rows sequentially output the generated electric signals through the corresponding read lines, based on the electric charges accumulated by the light sensing units 4 in the integration period.
The scanning of the gate line1, gate line2 and gate line3 is completed by the first switch timing unit, and the scanning of the rest line1, rest line2 and rest line3 is completed by the first reset timing unit, so that the acquisition of the electric signals output by the pixel detection circuits of the first row, the second row and the third row in the reset phase and in the sampling phase is completed. After that, the scanning of the gate line4, gate line5 and gate line6 by the second switch timing unit and the scanning of the rest line4, rest line5 and rest line6 by the second reset timing unit can be completed according to the same method as described above, so as to complete the acquisition of the electric signals output by the pixel detection circuits of the fourth, fifth and sixth rows in the reset phase and in the sampling phase.
It can be seen that the group1 and the group2 output one by one, that is, after the electrical signals generated by the pixel detection circuits in the group1 in the reset phase and the sampling phase are output, the electrical signals generated by the pixel detection circuits in the group2 in the reset phase and the sampling phase are output. The number of rows of the pixel detection circuits connected to each pixel detection circuit group is small, and the sum Tp of the time lengths of the pixel detection units in the reset stage in each pixel detection circuit group is short, so that after all the electric signals generated by the pixel detection units in the reset stage in each pixel detection circuit group are completely output, the electric signals generated by the pixel detection units in the pixel detection circuit group in the integration period are output through the corresponding read lines, and further the electric signals generated by the pixel detection units scanned in advance in the integration stage in each pixel detection circuit group and the electric signals generated by the pixel detection units scanned in the following stage in the reset stage can be prevented from being output simultaneously.
The display panel provided in embodiment 1 of the present invention includes a plurality of switch timing units and a plurality of reset timing units, and each switch timing unit and each reset timing unit are connected to one pixel detection circuit group. In the working process of the display panel, the control unit can control each switch time sequence unit to work one by one and control each reset time sequence unit to work one by one, corresponding each pixel detection circuit group outputs electric signals generated by each row of pixel detection circuits connected with the corresponding pixel detection circuit group in a resetting stage and a sampling stage in a time-sharing manner, the number of rows of the pixel detection circuits connected with each pixel detection circuit group is small, and the sum Tp of the duration of each row of the pixel detection units in the resetting stage is short by corresponding each pixel detection circuit group, so that after all the electric signals generated by each row of the pixel detection units in the resetting stage in the pixel detection circuit group are output, the electric signals generated by each pixel detection unit in the pixel detection circuit group in an integration period are output through a corresponding read line, and accordingly, the situation that the electric signals generated by the pixel detection units scanned in advance in each pixel detection circuit group in the integration stage are generated in the integration stage can be avoided The electrical signal generated by the post-scanning pixel detection unit in the reset stage and the electrical signal generated by the post-scanning pixel detection unit are output simultaneously, so that the accuracy of the display panel for acquiring the electrical signals generated by the detection pixel units in the integration stage can be improved, and the accuracy of the display image generated by the display panel can be correspondingly improved.
Preferably, the sum Tp of the duration of the reset phase of each pixel detection circuit in each pixel detection circuit group is less than or equal to the duration Tint of the integration phase of any one pixel detection circuit in the pixel detection circuit group, so that after all the electric signals generated by the pixel detection units in each row of the pixel detection circuit group in the reset phase are output, the electric signals generated by the pixel detection units in the pixel detection circuit group in the integration period start to be output through the corresponding read lines, and accordingly, the electric signals generated by the pixel detection units scanned in advance in each pixel detection circuit group in the integration phase and the electric signals generated by the pixel detection units scanned in the following scanning phase in the reset phase can be prevented from being output simultaneously.
In order to determine the variation trend of the accumulated charges of some pixel detection circuits in the pixel detection circuit group during the integration phase, as shown in fig. 3 and 5, the (N + 1) th switch timing unit is connected to each selection switch line in the (N + 1) th pixel detection circuit group and is connected to some selection switch lines in the nth pixel detection circuit group.
The starting time from the completion time of the reset stage of the last row of pixel detection circuits in the nth pixel detection circuit group to the sampling stage of the first row of pixel detection circuits in the nth pixel detection circuit group is a first period Ta.
The control unit is further configured to, in a first period Ta, control the (N + 1) th switching timing sequence unit to input an on signal to a part of selection switch lines in an nth pixel detection circuit group connected thereto line by line, so that the corresponding selection switch unit 3 is turned on, and output an electric signal generated by the corresponding voltage generation unit 2 in the first period according to the photosensitive unit 4 through the corresponding read line; wherein N is more than or equal to 1; the sum Tp of the time lengths of the reset phases of the pixel detection circuits of each pixel detection circuit group is less than the time length Tint of the integration phase of any one pixel detection circuit in the pixel detection circuit group, and the scanning time length of part of the selection switch lines in the Nth pixel detection circuit group connected with the (N + 1) th switch timing sequence unit is less than or equal to the time length of the first time period Ta.
Specifically, the second switch timing unit is connected to both gate line4, gate line5 and gate line6 in group2 and gate line1 and gate line2 in group 1. In the working process of the display panel, in a first time period Ta, namely from the time when the reset phase of the pixel detection circuit in the third row is completed to the starting time of the sampling phase of the pixel detection circuit in the first row, the control unit can control the second switch timing unit to input starting signals to the gate line1 and the gate line2 row by row, and when the second switch timing unit inputs the starting signals to the gate line1, the first row of pixel detection circuits can output electric signals generated by the charges accumulated in the first time period through the corresponding reading lines; when the second switching timing unit inputs an on signal to the gate line2, the second row pixel detection circuit can output an electric signal generated by the electric charges accumulated in the first period through the corresponding read line.
Since the first period Ta is within the integration period of the first row of pixel detection circuits and the integration period of the second row of pixel detection circuits, the rate at which the first row of pixel detection circuits accumulate electric charges from the reset phase to the first period can be determined accordingly from the electric signals output by the first row of pixel detection circuits in the reset phase and the electric signals output in the first period, and according to the electric signals output by the first row of pixel detection circuits in the first period and the electric signals output by the first row of pixel detection circuits in the sampling phase, determining the rate of the electric charges accumulated by the first row of pixel detection circuits from the first period to the acquisition phase, and correspondingly comparing the rate of the electric charges accumulated by the first row of pixel detection circuits from the reset phase to the first period with the rate of the electric charges accumulated by the first row of pixel detection circuits from the first period to the sampling phase to determine the change trend of the electric charges accumulated by the first row of pixel detection circuits in the integration phase; similarly, the variation trend of the electric charge accumulated by the second row of pixel detection circuits in the integration phase is determined according to the electric signal output by the second row of pixel detection circuits in the reset phase, the electric signal output in the first period and the electric signal output in the sampling phase.
Further, the sum Tp1 of the time lengths of the reset phases of the first row, second row, and third row pixel detection circuits is smaller than the time length of the integration phase of any one of the first row, second row, and third row pixel detection circuits, and the scan time length of the gate line1 and gate line2 to which the second switch timing unit is connected is smaller than or equal to the time length of the first period Ta. Therefore, after the pixel detection units in the first and second rows complete outputting of the electric signals generated in the first stage, the pixel detection units in the first row start outputting the electric signals generated in the integration stage, so that the electric signals generated by the pixel detection units in the pixel detection circuit group in the first time period Ta and the electric signals generated by the pixel detection units in the pixel detection circuit group in the sampling stage can be prevented from being output simultaneously, and the accuracy of the display panel for acquiring the electric signals generated by the detection pixel units in the integration stage is improved.
In order to improve the intensity of the electrical signals in the integration stage of some pixel detection circuits in the pixel detection circuit group, as shown in fig. 3 and 5, the (N + 1) th switch timing unit is connected to each select switch line in the (N + 1) th pixel detection circuit group and to some select switch lines in the nth pixel detection circuit group.
The starting time from the sampling phase completion time of the last row of pixel detection circuits in the nth pixel detection circuit group to the resetting phase of the first row of pixel detection circuits in the (N + 1) th pixel detection circuit group is a second time period Tb.
The control unit is further configured to, in a second time period Tb, control the (N + 1) th switching timing sequence unit to input an on signal to some select switch lines in the nth pixel detection circuit group connected thereto line by line, so that the corresponding select switch unit 3 is turned on, and output the corresponding voltage generation unit 2 through a corresponding read line according to the electrical signal generated by the photosensitive unit 4 in the second time period; wherein N is more than or equal to 1; the scanning time length of a part of selection switch lines in the nth pixel detection circuit group connected with the (N + 1) th switch timing sequence unit is less than or equal to the time length of the second time period Tb.
Specifically, the second switch timing unit is connected to both gate line4, gate line5 and gate line6 in group2 and gate line1 and gate line2 in group 1. During the operation of the display panel, in a second time period Tb, that is, from the sampling phase completion time of the pixel detection circuit in the third row to the start time of the reset phase of the pixel detection circuit in the fourth row, the control unit can control the second switch timing unit to input the start signal to the gate line1 and the gate line2 row by row, and when the second switch timing unit inputs the start signal to the gate line1, the first row of pixel detection circuits can output the electric signal generated by the electric charge accumulated in the second time period through the corresponding read line; when the second switch timing unit inputs an on signal to the gate line2, the second row pixel detection circuit can output an electric signal generated by the electric charges accumulated in the second period through the corresponding read line.
Since the pixel detection circuits of the first row and the second row still continuously accumulate charges after the sampling period, the electric signals generated by the pixel detection circuits of the corresponding first row in the second phase are the charges accumulated by the pixel detection circuits of the first row from the end time of the reset phase to the end time of the second phase turning on signal (i.e. the duration Tint1 of the integration phase), the electric signals generated by the pixel detection circuits of the second row in the second phase are the charges accumulated by the pixel detection circuits of the second row from the end time of the reset phase to the end time of the second phase turning on signal (i.e. the duration Tint2 of the integration phase), and therefore, the intensities of the electric signals generated by the pixel detection circuits of the first row and the second row in the integration phase can be improved.
In addition, the scanning duration of the second switch timing unit connecting the gate line1 and the gate line2 is less than or equal to the duration of the second period Tb. Therefore, after the pixel detection units in the first row and the second row completely output the electric signals generated in the second stage, the fourth row of pixel detection units starts to output the electric signals generated in the reset stage, so that the electric signals generated by the pixel detection units in the pixel detection circuit group in the first period Tb and the electric signals generated by the pixel detection units in the pixel detection circuit group in the reset stage can be prevented from being output simultaneously, and the accuracy of the display panel for acquiring the electric signals generated by the detection pixel units in the integration stage is better improved.
Preferably, the M switch timing units and the M reset timing units in the display panel of this embodiment may be integrated in the same timing control chip, so that the structure of the display panel may be simple.
Further, as shown in fig. 3, the display panel of the present embodiment may further include a plurality of operational amplifiers OP. Specifically, the input end of each operational amplifier OP is connected to a read line, and the output end of each operational amplifier OP is connected to the control unit, and is configured to amplify the electrical signals output by each row of the pixel detection circuits, so that the control unit can identify the electrical signals output by each pixel detection circuit.
The specific structure of the pixel detection circuit is described in detail below with reference to fig. 4.
As shown in fig. 4, the reset unit 1 includes a first transistor M1, wherein a first pole of the first transistor M1 is connected to a reset voltage terminal Vrst, a second pole is connected to the light sensing unit 4 and the voltage generating unit 2, and a control pole is connected to a reset line. The light sensing unit 4 includes a photodiode PD, wherein a first pole of the photodiode PD is connected to the voltage generating unit 2 and the reset unit 1, and a second pole is connected to the reverse bias voltage terminal Vr. The voltage generating unit 2 includes a second transistor M2, in which a first pole of the second transistor M2 is connected to the voltage input Vdd terminal, a second pole is connected to the selection switch unit 3, and a control pole is connected to the light sensing unit 4 and the reset unit 1. The selection switch unit 3 includes a third transistor M3, wherein a first pole of the third transistor M3 is connected to the voltage generation unit 2, a second pole thereof is connected to the read line, and a control pole thereof is connected to the selection switch line gate line.
Specifically, the second pole of the first transistor M1, the control pole of the second transistor M2, and the first pole of the photodiode PD are all connected to the node a, and the photodiode PD is configured to control the potential of the node a according to the intensity of the optical signal and the voltage signal input from the reverse bias voltage terminal Vr; the first transistor M1 is used for resetting the potential of the node a according to the reset signal input by the reset line and the voltage signal input by the reset voltage terminal Vrst; the second transistor M2 is used for generating a corresponding electric signal according to the potential of the node a and the voltage signal input by the voltage input Vdd terminal; the third transistor M3 is configured to input an electrical signal generated by the second transistor M2 to a corresponding read line according to an on signal input to the select switch line gate line.
The first transistor M1 and the second transistor M2 may be switching transistors, and the embodiment of the invention is described by taking the first transistor M1 and the second transistor M2 as N-type transistors, and accordingly, when the control voltage is high, the first pole and the second pole are turned on, and when the control voltage is low, the first pole and the second pole are turned off. Of course, it is also possible that the first transistor M1 and the second transistor M2 are P-type triacs. The second transistor M2 may be an amplifying transistor, such as a source follower.
Example 2
Embodiment 2 of the present invention provides a method for detecting a display panel, where the method is applied to the display panel described in embodiment 1, and the method includes:
controlling the M switch time sequence units and the M reset time sequence units by the control unit; and controlling the pixel detection circuit connected with the switching time sequence unit to work through the switching time sequence unit and the resetting time sequence unit.
The step of controlling the pixel detection circuit connected with the switching time sequence unit and the reset time sequence unit to work comprises the following steps:
in the reset stage, a reset signal is input to a reset line connected to the reset line row by row through a reset timing unit, so that the corresponding reset unit 1 resets the charges accumulated in the corresponding photosensitive unit through the reset signal, and a turn-on signal is input to each selection switch line connected to the reset line row by row through a switch timing unit, so that the corresponding selection switch unit 3 is turned on, and the corresponding voltage generation unit 2 outputs the generated electric signal through a read line corresponding to the charges reset by the photosensitive unit.
In the sampling stage, the switch timing unit inputs turn-on signals to the select switch lines connected to the switch timing unit line by line to turn on the corresponding select switch unit 3, and the voltage generation unit 2 outputs the generated electric signals through the corresponding read lines according to the charges accumulated by the photosensitive units in the integration stage.
The display panel includes 2 switch timing units and 2 reset timing units. The display panel is divided into two pixel detection circuit group, the group1 includes pixel detection circuits of a first row, a second row and a third row, and the group2 includes pixel detection circuits of a fourth row, a fifth row and a sixth row. The display panel comprises two switch time sequence units and two reset time sequence units, wherein the first switch time sequence unit is connected with a selection switch line gate line connected with each row of pixel detection circuits in group1, the second switch time sequence unit is connected with a selection switch line gate line connected with each row of pixel detection circuits in group2, namely the first switch time sequence unit is connected with gate line1, gate line2 and gate line3, and the second switch time sequence unit is connected with gate line4, gate line5 and gate line 6. The first reset timing unit is connected to a reset line rest line to which each row of pixel detection circuits in group1 is connected, the second reset timing unit is connected to a reset line rest line to which each row of pixel detection circuits in group2 is connected, that is, the first reset timing unit is connected to reset line1, reset line2 and reset line3, and the second reset timing unit is connected to reset line4, reset line5 and reset line 6.
The control unit can control the first switch time sequence unit and the second switch time sequence unit to work one by one, and control the first reset time sequence unit and the second reset time sequence unit to work one by one. That is, after one of the first switch timing unit and the second switch timing unit finishes working, the other one does work; after one of the first reset timing unit and the second reset timing unit is completed, the other one is operated. The following description will take the first switch timing unit and the first reset timing unit as an example.
In the reset phase, the first reset timing unit performs a progressive scan on the rest line1, the rest line2, and the rest line3, and the first switching timing unit performs a progressive scan on the gate line1, the gate line2, and the gate line 3. Specifically, when the first reset timing unit inputs a reset signal to the reset line1, the reset unit 1 in the pixel detection circuit connected to the reset line1 can reset the charges accumulated in the light sensing unit 4 connected thereto, at this time, the first switch timing unit inputs an on signal to the gate line1, and the selection switch unit 3 in the pixel detection circuit connected to the gate line1 can output the generated electric signal through the corresponding read line according to the charges reset on the light sensing unit 4 by the voltage generation unit 2 connected thereto; in the same manner, the electric charges accumulated in the light sensing units 4 in the pixel detection circuits connected to the rest line2 and the rest line3 are sequentially reset, and the electric signals generated by the voltage generation units 2 in the pixel detection circuits connected to the gate line2 and the gate line3 are sequentially output through the corresponding read lines according to the electric charges reset on the light sensing units 4.
Thereafter, in the sampling phase, the first switch timing unit performs progressive scanning on the gate line1, the gate line2, and the gate line 3. It should be noted that each row of pixel detection circuits accumulates light signals from the reset phase to the sampling phase (i.e., the integration phase) and generates corresponding electrical signals. Specifically, when the first switching timing unit inputs an on signal to the gate line1, the selection switch unit 3 in the first row of pixel detection circuits can output the generated electric signal through the corresponding read line from the electric charge accumulated by the voltage generation unit 2 connected thereto in the integration phase of the light sensing unit 4; in the same manner, the voltage generation units 2 in the pixel detection circuits of the second and third rows sequentially output the generated electric signals through the corresponding read lines, based on the electric charges accumulated by the light sensing units 4 in the integration period.
The scanning of the gate line1, gate line2 and gate line3 is completed by the first switch timing unit, and the scanning of the rest line1, rest line2 and rest line3 is completed by the first reset timing unit, so that the acquisition of the electric signals output by the pixel detection circuits of the first row, the second row and the third row in the reset phase and in the sampling phase is completed. After that, the scanning of the gate line4, gate line5 and gate line6 by the second switch timing unit and the scanning of the rest line4, rest line5 and rest line6 by the second reset timing unit can be completed according to the same method as described above, so as to complete the acquisition of the electric signals output by the pixel detection circuits of the fourth, fifth and sixth rows in the reset phase and in the sampling phase.
It can be seen that the group1 and the group2 output one by one, that is, after the electrical signals generated by the pixel detection circuits in the group1 in the reset phase and the sampling phase are output, the electrical signals generated by the pixel detection circuits in the group2 in the reset phase and the sampling phase are output. The number of rows of the pixel detection circuits connected to each pixel detection circuit group is small, and the sum Tp of the time lengths of the pixel detection units in the reset stage in each pixel detection circuit group is short, so that after all the electric signals generated by the pixel detection units in the reset stage in each pixel detection circuit group are completely output, the electric signals generated by the pixel detection units in the pixel detection circuit group in the integration period are output through the corresponding read lines, and further the electric signals generated by the pixel detection units scanned in advance in the integration stage in each pixel detection circuit group and the electric signals generated by the pixel detection units scanned in the following stage in the reset stage can be prevented from being output simultaneously.
The detection method of the display panel provided by the embodiment 2 of the invention comprises the steps that the control unit can control the switch time sequence units to work one by one and control the reset time sequence units to work one by one; and the switching time sequence unit and the resetting time sequence unit control the pixel detection circuits connected with the switching time sequence unit and the resetting time sequence unit to work, because each pixel detection circuit group outputs electric signals generated by each row of pixel detection circuits connected with the switching time sequence unit in a resetting stage and a sampling stage in a time-sharing manner, the number of rows of the pixel detection circuits connected with each pixel detection circuit group is small, and the sum Tp of the time lengths of each row of pixel detection units in the resetting stage is short for each pixel detection circuit group, so that after all the electric signals generated by each row of pixel detection units in the resetting stage in the pixel detection circuit group are output, the electric signals generated by each pixel detection unit in the integration period in the pixel detection circuit group are output through the corresponding read line, and accordingly, the electric signals generated by the pixel detection units scanned in the integration stage in advance in each pixel detection circuit group and the electric signals generated by the pixel detection units scanned in the later scanning stage in the later scanning pixel detection circuit group can be prevented from being output in the later scanning stage The electric signals generated in the setting stage are output simultaneously, so that the accuracy of the display panel for acquiring the electric signals generated by the detection pixel units in the integration stage can be improved, and the accuracy of the display image generated by the display panel can be correspondingly improved.
In order to determine the variation trend of the charges accumulated by some pixel detection circuits in the group of pixel detection circuits in the integration phase, the step of controlling the pixel detection circuits connected with the switching timing unit and the reset timing unit to operate further includes:
in a first time period, inputting a starting signal to a part of selection switch lines in an nth pixel detection circuit group connected with the nth pixel detection circuit group line by line through an (N + 1) th switch time sequence unit so as to open a corresponding selection switch unit 3, and outputting an electric signal generated by a corresponding voltage generation unit 2 in the first time period according to a photosensitive unit through a corresponding reading line; wherein N is more than or equal to 1; the sum of the duration of the reset phase of each pixel detection circuit in each pixel detection circuit group is less than the duration of the integration phase of any one pixel detection circuit in the pixel detection circuit group, and the scanning duration of part of the selection switch lines in the nth pixel detection circuit group connected with the (N + 1) th switch timing sequence unit is less than or equal to the duration of the first time period.
Specifically, the second switch timing unit is connected to both gate line4, gate line5 and gate line6 in group2 and gate line1 and gate line2 in group 1. In a first period Ta, which is from the time when the reset phase of the pixel detection circuit in the third row is completed to the time when the sampling phase of the pixel detection circuit in the first row is turned on, the control unit can control the second switching timing unit to input the turn-on signal to the gate line1 and the gate line2 row by row, and when the second switching timing unit inputs the turn-on signal to the gate line1, the pixel detection circuit in the first row can output the electric signal generated by the electric charge accumulated in the first period through the corresponding read line; when the second switching timing unit inputs an on signal to the gate line2, the second row pixel detection circuit can output an electric signal generated by the electric charges accumulated in the first period through the corresponding read line.
Since the first period Ta is within the integration period of the first row of pixel detection circuits and the integration period of the second row of pixel detection circuits, the rate at which the first row of pixel detection circuits accumulate electric charges from the reset phase to the first period can be determined accordingly from the electric signals output by the first row of pixel detection circuits in the reset phase and the electric signals output in the first period, and determining the rate of the electric charges accumulated by the first row of pixel detection circuits from the first period to the acquisition stage according to the electric signals output by the first row of pixel detection circuits in the first period and the electric signals output by the first row of pixel detection circuits in the sampling stage, and correspondingly comparing the rate of the electric charges accumulated by the first row of pixel detection circuits from the reset stage to the first period with the rate of the electric charges accumulated by the first row of pixel detection circuits from the first period to the sampling stage to determine the variation trend of the electric charges accumulated by the first row of pixel detection circuits in the integration stage; similarly, the variation trend of the electric charge accumulated by the second row of pixel detection circuits in the integration phase is determined according to the electric signal output by the second row of pixel detection circuits in the reset phase, the electric signal output in the first period and the electric signal output in the sampling phase.
Further, the sum Tp1 of the time lengths of the reset phases of the first row, second row, and third row pixel detection circuits is smaller than the time length of the integration phase of any one of the first row, second row, and third row pixel detection circuits, and the scan time length of the gate line1 and gate line2 to which the second switch timing unit is connected is smaller than or equal to the time length of the first period Ta. Therefore, after the pixel detection units in the first and second rows complete outputting of the electric signals generated in the first stage, the pixel detection units in the first row start outputting the electric signals generated in the integration stage, so that the electric signals generated by the pixel detection units in the pixel detection circuit group in the first time period Ta and the electric signals generated by the pixel detection units in the pixel detection circuit group in the sampling stage can be prevented from being output simultaneously, and the accuracy of the display panel for acquiring the electric signals generated by the detection pixel units in the integration stage is improved.
In order to improve the intensity of the electrical signal in the integration stage of some pixel detection circuits in the group of pixel detection circuits, the step of controlling the pixel detection circuits connected to the switching timing unit and the resetting timing unit to operate through the switching timing unit and the resetting timing unit further includes:
in a second time period, inputting turn-on signals to some of the select switch lines in the nth pixel detection circuit group connected to the nth pixel detection circuit group row by row through the (N + 1) th switch timing sequence unit so as to turn on the corresponding select switch unit 3, and outputting the corresponding voltage generation unit through the corresponding read line according to the electric signal generated by the photosensitive unit in the second time period; wherein N is more than or equal to 1; the scanning duration of part of the selection switch line in the nth pixel detection circuit group connected with the (N + 1) th switch timing sequence unit is less than or equal to the duration of the second time period.
Specifically, the second switch timing unit is connected to both gate line4, gate line5 and gate line6 in group2 and gate line1 and gate line2 in group 1. In a second period Tb, which is from the sampling phase completion time of the pixel detection circuit in the third row to the turn-on time of the reset phase of the pixel detection circuit in the fourth row, the control unit can control the second switch timing unit to input the turn-on signal to the gate line1 and the gate line2 row by row, and when the second switch timing unit inputs the turn-on signal to the gate line1, the first row of pixel detection circuits can output the electric signal generated by the electric charges accumulated in the second period through the corresponding read line; when the second switch timing unit inputs an on signal to the gate line2, the second row pixel detection circuit can output an electric signal generated by the electric charges accumulated in the second period through the corresponding read line.
Since the pixel detection circuits of the first row and the second row still continuously accumulate charges after the sampling period, the electric signals generated by the pixel detection circuits of the corresponding first row in the second stage are the charges accumulated by the pixel detection circuits of the first row from the end time of the reset stage to the end time of the turn-on signal of the second stage (i.e. the duration Tint1 of the integration stage), the electric signals generated by the pixel detection circuits of the second row in the second stage are the charges accumulated by the pixel detection circuits of the second row from the end time of the reset stage to the end time of the turn-on signal of the second stage (i.e. the duration Tint2 of the integration stage), and therefore, the intensities of the electric signals generated by the pixel detection circuits of the first row and the second row in the integration stage can be improved.
In addition, the scanning duration of the second switch timing unit connecting the gate line1 and the gate line2 is less than or equal to the duration of the second period Tb. Therefore, after the pixel detection units in the first row and the second row completely output the electric signals generated in the second stage, the fourth row of pixel detection units starts to output the electric signals generated in the reset stage, so that the electric signals generated by the pixel detection units in the pixel detection circuit group in the first period Tb and the electric signals generated by the pixel detection units in the pixel detection circuit group in the reset stage can be prevented from being output simultaneously, and the accuracy of the display panel for acquiring the electric signals generated by the detection pixel units in the integration stage is better improved.
Example 3:
this embodiment 3 provides a display device including the display panel described in embodiment 1. Therefore, the display device provided by the embodiment has better accuracy of the displayed image.
The display device may be a liquid crystal display device or an electroluminescent display device, such as any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (7)

1. A display panel comprising a plurality of selection switch lines, a plurality of readout lines, and a plurality of reset lines, the plurality of selection switch lines and the plurality of readout lines being arranged to intersect and defining pixel detection units at the intersections, wherein each of the pixel detection units comprises: the display panel is divided into M pixel detection circuit groups, and each pixel detection circuit group comprises a plurality of rows of pixel detection circuits; the display panel further includes: the device comprises a control unit, M switch time sequence units and M reset time sequence units; m is more than or equal to 2; wherein,
each of the switch timing units is connected to the selection switch line to which each of the pixel detection circuits of one of the pixel detection circuit groups is connected; each reset time sequence unit is connected with the reset line connected with each pixel detection circuit of one pixel detection circuit group; m of the switch timing units and M of the reset timing units are connected to the control unit, wherein,
the control unit is used for controlling the M switch time sequence units to work one by one; controlling the M reset time sequence units to work one by one;
each reset time sequence unit is used for inputting reset signals to the reset lines connected with the reset time sequence unit row by row in a reset stage so that the corresponding reset unit resets the charges accumulated by the corresponding photosensitive unit through the reset signals;
each switch time sequence unit is used for inputting a starting signal to each selection switch line connected with the switch time sequence unit line by line in a resetting stage so as to open the corresponding selection switch unit, and outputting a generated electric signal through the corresponding reading line according to the electric charge of the reset photosensitive unit of the corresponding voltage generation unit; in a sampling stage, inputting a starting signal to each selection switch line connected with the switch time sequence unit line by line to open the corresponding selection switch unit, and outputting a generated electric signal through the corresponding reading line according to the electric charge accumulated by the voltage generation unit in the integration stage;
the (N + 1) th switch timing sequence unit is connected with each selection switch line in the (N + 1) th pixel detection circuit group and is connected with part of the selection switch lines in the (N) th pixel detection circuit group;
the starting time from the completion time of the reset stage of the last row of the pixel detection circuits in the Nth pixel detection circuit group to the sampling stage of the first row of the pixel detection circuits in the Nth pixel detection circuit group is a first period of time;
the control unit is further configured to, in the first period, input, by the N +1 th switch timing unit, a turn-on signal to some of the selection switch lines in the nth pixel detection circuit group connected thereto, line by line, so as to turn on the corresponding selection switch unit, and output, by the corresponding voltage generation unit, an electrical signal generated by the photosensitive unit in the first period through the corresponding readout line; wherein N is more than or equal to 1; the sum of the duration of the reset phase of each pixel detection circuit in each pixel detection circuit group is less than the duration of the integration phase of any one pixel detection circuit in the pixel detection circuit group, and the scanning duration of part of the selection switch lines in the nth pixel detection circuit group connected with the N +1 th switch timing sequence unit is less than or equal to the duration of the first time period.
2. The display panel according to claim 1, wherein a sampling phase completion timing of the last row of the pixel detection circuits in the nth pixel detection circuit group to an on timing of the reset phase of the first row of the pixel detection circuits in the N +1 th pixel detection circuit group is a second period;
the control unit is further configured to, in the second time period, input, by the N +1 th switch timing unit, an on signal to some of the selection switch lines in the nth pixel detection circuit group connected thereto, line by line, so as to turn on the corresponding selection switch unit, and output, by the corresponding voltage generation unit, an electrical signal generated by the photosensitive unit in the second time period through the corresponding read line; wherein N is more than or equal to 1; the scanning duration of part of the selection switch lines in the nth pixel detection circuit group connected with the (N + 1) th switch timing unit is less than or equal to the duration of the second period.
3. The display panel of claim 1, wherein M of the switch timing units and M of the reset timing units are integrated in a same timing control chip.
4. The display panel according to claim 1, further comprising a plurality of operational amplifiers, each of which is connected to one of the read lines for amplifying the electric signal output from each of the pixel detection circuits.
5. The display panel according to claim 1, wherein the reset unit comprises a first transistor, wherein a first electrode of the first transistor is connected to a reset voltage terminal, a second electrode of the first transistor is connected to the light sensing unit and the voltage generating unit, and a control electrode of the first transistor is connected to the reset line;
the photosensitive unit comprises a photodiode, wherein a first pole of the photodiode is connected with the voltage generation unit and the reset unit, and a second pole of the photodiode is connected with a reverse bias voltage end;
the voltage generating unit comprises a second transistor, wherein a first pole of the second transistor is connected with a voltage input end, a second pole of the second transistor is connected with the selection switch unit, and a control pole of the second transistor is connected with the photosensitive unit and the resetting unit;
the selection switch unit includes a third transistor, wherein a first pole of the third transistor is connected to the voltage generation unit, a second pole of the third transistor is connected to the read line, and a control pole of the third transistor is connected to the selection switch line.
6. A method for inspecting a display panel, applied to the display panel according to any one of claims 1 to 5, the method comprising:
a step of controlling the M switching timing units and the M reset timing units by a control unit; and controlling the pixel detection circuit connected with the switch timing unit to work through the switch timing unit and the reset timing unit;
the step of controlling the pixel detection circuit connected with the switching timing unit and the reset timing unit to work through the switching timing unit and the reset timing unit comprises the following steps:
a reset stage, in which the reset time sequence unit inputs reset signals to the reset lines connected thereto line by line, so that the corresponding reset units reset the charges accumulated by the corresponding photosensitive units through the reset signals, and the switch time sequence unit inputs turn-on signals to the selection switch lines connected thereto line by line, so that the corresponding selection switch units are turned on, and the corresponding voltage generation units output the generated electrical signals through the corresponding read lines according to the charges reset by the photosensitive units;
a sampling stage, in which a switch timing unit inputs a start signal to each of the selection switch lines connected to the switch timing unit line by line to turn on the corresponding selection switch unit, and the voltage generation unit outputs a generated electric signal through the corresponding reading line according to the electric charge accumulated by the light sensing unit in the integration stage;
the step of controlling the pixel detection circuit connected with the switching timing unit and the reset timing unit to work through the switching timing unit and the reset timing unit further comprises:
in a first period, inputting a turn-on signal to some of the selection switch lines in the nth pixel detection circuit group connected thereto row by row through the (N + 1) th switch timing sequence unit to turn on the corresponding selection switch unit, and outputting an electric signal generated by the corresponding voltage generation unit in the first period according to the photosensitive unit through the corresponding reading line; wherein N is more than or equal to 1; the sum of the duration of the reset phase of each pixel detection circuit in each pixel detection circuit group is less than the duration of the integration phase of any one pixel detection circuit in the pixel detection circuit group, and the scanning duration of part of the selection switch lines in the nth pixel detection circuit group connected with the N +1 th switch timing sequence unit is less than or equal to the duration of the first time period.
7. The method for inspecting a display panel according to claim 6, wherein the method is applied to the display panel according to claim 3; the step of controlling the pixel detection circuit connected with the switching timing unit and the reset timing unit to work through the switching timing unit and the reset timing unit further comprises:
in a second time period, inputting turn-on signals to part of the selection switch lines in the nth pixel detection circuit group connected with the selection switch line row by row through the (N + 1) th switch timing sequence unit so as to turn on the corresponding selection switch unit, and outputting the corresponding voltage generation unit through the corresponding reading line according to the electric signal generated by the photosensitive unit in the second time period; wherein N is more than or equal to 1; the scanning duration of part of the selection switch lines in the nth pixel detection circuit group connected with the (N + 1) th switch timing unit is less than or equal to the duration of the second period.
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