CN108227800A - A kind of regulator circuit - Google Patents
A kind of regulator circuit Download PDFInfo
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- CN108227800A CN108227800A CN201611130365.1A CN201611130365A CN108227800A CN 108227800 A CN108227800 A CN 108227800A CN 201611130365 A CN201611130365 A CN 201611130365A CN 108227800 A CN108227800 A CN 108227800A
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- 230000000295 complement effect Effects 0.000 claims abstract description 12
- 230000005611 electricity Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 4
- 230000000087 stabilizing effect Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The embodiment of the invention discloses a kind of regulator circuit, the circuit includes：Voltage bias unit, first order operation amplifier unit, second level operation amplifier unit, Muller compensating unit, control unit and complementary switch unit, input terminal of the complementary switch unit respectively with the output voltage terminal of the regulator circuit and the first order operation amplifier unit is connected, for when the output voltage terminal of the regulator circuit is connected and is loaded, disconnect the access between the output voltage terminal of the regulator circuit and the input terminal of the first order operation amplifier unit, the access between reference voltage and the first order operation amplifier unit input terminal is connected, so that the input terminal voltage of the first order operation amplifier unit keeps equal with reference voltage, reduce the overshoot voltage that load-strap is come, influence of the load to the stability of circuit is reduced simultaneously.
Description
Technical field
The present embodiments relate to circuit engineering more particularly to a kind of regulator circuits.
Background technology
Increasing with the scale of integrated circuit, complexity is also higher and higher, while to the various performance requirements of circuit
Also it is higher and higher.
Such as commonly used low dropout voltage regulator in integrated circuit, traditional low voltage difference voltage stabilizing shown in Figure 1
The electrical block diagram of circuit, including：Voltage bias unit 110, with control unit 150 and first order operation amplifier unit
120 are connected, for being that first order operation amplifier unit 120 provides bias voltage under the control of control unit 150；The first order is transported
Amplifying unit 120 is calculated, is connected with control unit 150 and second level operation amplifier unit 130, in control unit 150 and partially
The voltage difference under the control of voltage between output voltage VO UT and reference voltage VBG is put to be amplified, and by result export to
Second level operation amplifier unit 130；Second level operation amplifier unit 130, is connected with control unit 150, in control unit
Ability amplification, and output and reference voltage are driven under 150 control to the output voltage of first order operation amplifier unit 120
Output voltage VO UT identical VBG；Muller compensating unit 140, respectively with first order operation amplifier unit 120 and second level operation
Amplifying unit 130 is connected, for slowing down the transient response of output voltage VO UT；Control unit 150, respectively with voltage bias unit
110th, first order operation amplifier unit 120 is connected with second level operation amplifier unit 130, in the control of control signal EN
Under, control the work of each unit.It should be noted that in Fig. 1 since the component part of control unit 150 is distributed in phase
Away from remote position, so inconvenient iris out signal with wire frame, control unit 150 includes the first PMOS tube MP1, the 4th PMOS tube
MP4, the 7th PMOS tube MP7 and the second NMOS tube MN2.
But in the prior art, traditional low dropout voltage regulator as shown in Figure 1 is when output terminal has load to add next
It carves, leading to output terminal, this overshoot voltage can cause to be stabilized output in regulator circuit there are one larger overshoot voltage
Voltage VOUT becomes unstable, and unstable output voltage VO UT is through feeding back to first order operation amplifier unit 120 so that described
Difference increase between unstable output voltage VO UT and reference voltage VBG, therefore the regulator circuit is added to come in load
When need to readjust output voltage VO UT again, be allowed to equal with reference voltage and be restored in stationary value, therefore
Cause the stabilization time needed for low dropout voltage regulator long, influence the voltage regulation performance of the circuit.
Invention content
The present invention provides a kind of regulator circuit, reduces the overshoot voltage that load-strap is come, while reduces load to circuit
Stability influence.
The embodiment of the present invention provides a kind of regulator circuit, and the circuit includes：
Voltage bias unit, first order operation amplifier unit, second level operation amplifier unit, Muller compensating unit, control
Unit further includes：
Complementary switch unit, respectively with the output voltage terminal of the regulator circuit and the first order operation amplifier unit
Input terminal is connected, for when the output voltage terminal of the regulator circuit is connected and loaded, disconnecting the defeated of the regulator circuit
Go out the access between the input terminal of voltage end and the first order operation amplifier unit, conducting reference voltage is transported with the first order
The access between amplifying unit input terminal is calculated, so that the input terminal voltage of the first order operation amplifier unit is kept and reference electricity
It presses equal.
Illustratively, the voltage bias unit includes：Second PMOS tube, third PMOS tube, the first NMOS tube and third
NMOS tube, wherein：
The source electrode of second PMOS tube is connected with power supply, grid and drain electrode and first NMOS tube drain electrode phase
Even；The source electrode of the third PMOS tube is connected with power supply, and grid is connected with the grid of second PMOS tube, drain electrode and described the
The drain electrode of three NMOS tubes is connected；The grid of first NMOS tube is connected with reference voltage, source electrode and the third NMOS tube
Source electrode is connected；The drain electrode of the third NMOS tube is connected with grid.
Preferably, the first order operation amplifier unit includes：5th PMOS tube, the 6th PMOS tube, the 4th NMOS tube,
Five NMOS tubes and the 6th NMOS tube, wherein：
The source electrode of 5th PMOS tube is connected with power supply, grid and drain electrode and the 5th NMOS tube drain electrode phase
Even；The source electrode of 6th PMOS tube is connected with power supply, and grid is connected with the grid of the 5th PMOS tube, drain electrode and described the
The drain electrode of six NMOS tubes is connected；The grid of 5th NMOS tube is connected with the output voltage terminal of the regulator circuit, source electrode with
The source electrode of 6th NMOS tube and the drain electrode of the 4th NMOS tube are connected；The grid of 6th NMOS tube and reference electricity
Pressure is connected；The grid of 4th NMOS tube is connected with the grid of the third NMOS tube, source electrode and the source electrode of third NMOS tube
It is connected.
Further, the second level operation amplifier unit includes：8th PMOS tube, second resistance and 3rd resistor,
In：
The source electrode of 8th PMOS tube is connected with power supply, and grid is connected with the drain electrode of the 6th PMOS tube, drain electrode with
The first end of the second resistance is connected, the second end of the second resistance and the first end of the 3rd resistor and output electricity
Pressure side is connected, and the second end of the 3rd resistor is connected to the ground.
Preferably, the Muller compensating unit includes, first resistor and the first capacitance, wherein：The of the first resistor
One end is connected with the drain electrode of the 6th PMOS tube, and second end is connected with the first end of first capacitance, first capacitance
Second end be connected with the drain electrode of the 8th PMOS tube.
Preferably, described control unit includes：First PMOS tube, the 4th PMOS tube, the 7th PMOS tube and the second NMOS tube,
Wherein：
The source electrode of first PMOS tube is connected with power supply, drain electrode be connected with the drain electrode of second PMOS tube, grid and
Control signal is connected；The grid of 4th PMOS tube is connected with control signal, and source electrode is connected with power supply, drain electrode and the described 5th
The drain electrode of PMOS tube is connected；The grid of 7th PMOS tube with control signal be connected, source electrode is connected with power supply, drain with it is described
The drain electrode of 6th PMOS tube is connected；The grid of second NMOS tube is connected with revertive control signal, drain electrode and the 3rd NMOS
The drain electrode of pipe is connected, and source electrode is connected to the ground.
Further, the complementary switch unit includes：7th NMOS tube, the 8th NMOS tube, the 9th PMOS tube and the tenth
PMOS tube, wherein, the grid of the 9th PMOS tube is connected with pulse signal, the source electrode drain electrode with the 7th NMOS tube respectively
It is connected with the output voltage terminal of the regulator circuit, source electrode and the first order operation amplifier of the drain electrode with the 7th NMOS tube
The input terminal of unit is connected；The grid of 7th NMOS tube is connected with inverted burst signal；The grid of tenth PMOS tube with
Inverted burst signal is connected, and drain electrode and reference voltage of the source electrode with the 8th NMOS tube are connected, drain electrode and the 8th NMOS tube
Source electrode and the input terminal of the first order operation amplifier unit be connected；The grid of 8th NMOS tube and pulse signal phase
Even.
A kind of regulator circuit provided in an embodiment of the present invention, including voltage bias unit, first order operation amplifier unit,
Two level operation amplifier unit, Muller compensating unit, control unit and complementary switch unit, the complementary switch unit respectively with institute
The output voltage terminal for stating regulator circuit is connected with the input terminal of the first order operation amplifier unit, for working as the regulator circuit
Output voltage terminal connection load when, disconnect the output voltage terminal of the regulator circuit and the first order operation amplifier list
The access between reference voltage and the first order operation amplifier unit input terminal is connected in access between the input terminal of member, with
The input terminal voltage of the first order operation amplifier unit is made to keep equal with reference voltage, reduces the overshoot electricity that load-strap is come
Pressure, while reduce influence of the load to the stability of circuit.
Description of the drawings
Fig. 1 is the electrical block diagram of traditional low dropout voltage regulator；
Fig. 2 is a kind of structure diagram for regulator circuit that the embodiment of the present invention one provides；
Fig. 3 is a kind of structure diagram of regulator circuit provided by Embodiment 2 of the present invention；
Fig. 4 is that traditional low dropout voltage regulator provided by Embodiment 2 of the present invention and low voltage difference provided in this embodiment are steady
The power supply rejection ratio simulation comparison figure of volt circuit.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limitation of the invention.It also should be noted that in order to just
Part related to the present invention rather than entire infrastructure are illustrated only in description, attached drawing.
Embodiment one
Fig. 2 is a kind of voltage regulator circuit structure schematic diagram that the embodiment of the present invention one provides, and the present embodiment is suitable for integrated
The situation of regulator circuit is used in circuit.Referring specifically to as shown in Fig. 2, a kind of regulator circuit provided in this embodiment specifically wraps
It includes：
Voltage bias unit 210, first order operation amplifier unit 220, second level operation amplifier unit 230, Muller compensation
Unit 240, control unit 250 and complementary switch unit 260；
Wherein, complementary switch unit 260, respectively with the output voltage terminal VOUT of regulator circuit and first order operation amplifier list
The input terminal of member 220 is connected, described steady for when the output voltage terminal VOUT connections of the regulator circuit load, disconnecting
Reference voltage is connected in access between the output voltage terminal VOUT of volt circuit and the input terminal of first order operation amplifier unit 220
Access between 220 input terminal of VBG and first order operation amplifier unit, so that the input terminal of first order operation amplifier unit 220
Voltage keeps equal with reference voltage VBG.
A kind of regulator circuit provided in an embodiment of the present invention on the basis of traditional low dropout voltage regulator, passes through increasing
Add complementary switch unit, realize when the output voltage terminal of the regulator circuit connects load, disconnect the voltage stabilizing electricity
Access between the input terminal of the output voltage terminal on road and the first order operation amplifier unit, conducting reference voltage and described the
Access between level-one operation amplifier unit input terminal so that the first order operation amplifier unit input terminal voltage keep with
Reference voltage is equal, and then reduces the overshoot voltage that load-strap is come, while reduces influence of the load to the stability of circuit.
Embodiment two
Fig. 3 is a kind of voltage regulator circuit structure schematic diagram provided by Embodiment 2 of the present invention, on the basis of above-described embodiment,
The each unit for forming the regulator circuit is optimized in the present embodiment, referring specifically to shown in Fig. 3：
Illustratively, voltage bias unit 210 includes：Second PMOS tube MP2, third PMOS tube MP3, the first NMOS tube
MN1 and third NMOS tube MN3, wherein：
The source electrode of second PMOS tube MP2 is connected with power supply VCC, grid and drain electrode and the first NMOS tube MN1 drain electrode phase
Even；The source electrode of third PMOS tube MP3 is connected with power supply VCC, and grid is connected with the grid of the second PMOS tube MP2, drain electrode and third
The drain electrode of NMOS tube MN3 is connected；The grid of first NMOS tube MN1 is connected with reference voltage VBG, source electrode and third NMOS tube MN3
Source electrode be connected；The drain electrode of third NMOS tube MN3 is connected with grid.
Illustratively, first order operation amplifier unit 220 includes：5th PMOS tube MP5, the 6th PMOS tube MP6, the 4th
NMOS tube MN4, the 5th NMOS tube MN5 and the 6th NMOS tube MN6, wherein：
The source electrode of 5th PMOS tube MP5 is connected with power supply VCC, grid and drain electrode and the 5th NMOS tube MN5 drain electrode phase
Even；The source electrode of 6th PMOS tube MP6 is connected with power supply VCC, and grid is connected with the grid of the 5th PMOS tube MP5, drain electrode and the 6th
The drain electrode of NMOS tube MN6 is connected；The grid of 5th NMOS tube MN5 is connected with output voltage VO UT, source electrode and the 6th NMOS tube MN6
Source electrode and the drain electrode of the 4th NMOS tube MN4 be connected；The grid of 6th NMOS tube MN6 is connected with reference voltage VBG；4th
The grid of NMOS tube MN4 is connected with the grid of third NMOS tube MN3, and source electrode is connected with the source electrode of third NMOS tube MN3.
Illustratively, second level operation amplifier unit 230 includes：8th PMOS tube MP8, second resistance R2 and 3rd resistor
R3, wherein：
The source electrode of 8th PMOS tube MP8 is connected with power supply VCC, and grid is connected with the drain electrode of the 6th PMOS tube MP6, drain electrode with
The first end of second resistance R2 is connected, the second end of second resistance R2 and the first end and output voltage terminal of 3rd resistor R3
VOUT is connected, and the second end of 3rd resistor R3 is connected with ground VSS.
Illustratively, Muller compensating unit 240 includes, first resistor R1 and the first capacitance C1, wherein：First resistor R1's
First end is connected with the drain electrode of the 6th PMOS tube MP6, and second end is connected with the first end of the first capacitance C1, and the of the first capacitance C1
Two ends are connected with the drain electrode of the 8th PMOS tube MP8.
Illustratively, control unit 250 includes：First PMOS tube MP1, the 4th PMOS tube MP4, the 7th PMOS tube MP7 and
Second NMOS tube MN2, wherein：
The source electrode of first PMOS tube MP1 is connected with power supply VCC, drain electrode be connected with the drain electrode of the second PMOS tube MP2, grid and
Control signal EN is connected；The grid of 4th PMOS tube MP4 is connected with control signal EN, and source electrode is connected with power supply VCC, drain electrode and the
The drain electrode of five PMOS tube MP5 is connected；The grid of 7th PMOS tube MP7 is connected with control signal EN, and source electrode is connected with power supply VCC,
Drain electrode is connected with the drain electrode of the 6th PMOS tube MP6；The grid of second NMOS tube MN2 is connected with revertive control signal ENB, drain electrode and the
The drain electrode of three NMOS tube MN3 is connected, and source electrode is connected with ground VSS.
Illustratively, complementary switch unit 260 includes：7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th PMOS tube
MP9 and the tenth PMOS tube MP10, wherein, the grid of the 9th PMOS tube MP9 is connected with pulse signal SW, and source electrode is respectively with the 7th
The drain electrode of NMOS tube MN7 is connected with the output voltage terminal VOUT of the regulator circuit, drain electrode and the source electrode of the 7th NMOS tube MN7 and
The input terminal of first order operation amplifier unit 220 is connected；The grid of 7th NMOS tube MN7 is connected with inverted burst signal SWB；Tenth
The grid of PMOS tube MP10 is connected with inverted burst signal SWB, source electrode and the drain electrode of the 8th NMOS tube MN8 and reference voltage VBG phases
Even, drain electrode is connected with the source electrode of the 8th NMOS tube MN8 and the input terminal of first order operation amplifier unit 220；8th NMOS tube
The grid of MN8 is connected with pulse signal SW.
The structure diagram of low dropout voltage regulator shown in Figure 3, the operation principle of the circuit are：Circuit is in not work
When work, pulse signal SW is low level (inverted burst signal SWB is high level), so MP9 and MN7 conductings, the voltage stabilizing
Access between the output voltage terminal VOUT of circuit and the input terminal of first order operation amplifier unit 220 is connected；Control signal EN
For low level 0, reference voltage VBG is also low level, and the first PMOS tube MP1 is connected at this time, and the first NMOS tube MN1 is closed, current potential
Point VP1 is connected with power supply VCC, therefore potential point VP1 is high level, and same principle, potential point VP2, VP3 are also in high electricity
It is flat, therefore the second PMOS tube MP2, third PMOS tube MP3, the 5th PMOS tube MP5, the 6th PMOS tube MP6 and the 8th PMOS tube
MP8 is turned off；And due to controlling signal ENB at this time as high level, the second NMOS tube MN2 conductings, so potential point VN1 with
Ground VSS is connected, so in low level, so the 4th NMOS tube MN4 is closed, so not having electric current stream in entire regulator circuit
It crosses；When control signal EN becomes high level when circuit is started to work, reference voltage VBG is also high level, MN1 conductings,
Therefore potential point VP1 and ground VSS is connected directly, so MP2 and MP3 conductings, the current potential of potential point VN1 gradually rises, MN3 with
MN4 is gradually turned on, and the conducting of MN4 causes potential point VN2 to be connected with ground VSS, so potential point VP3 is low level (reference voltage
VBG causes MN6 to be connected for high level), therefore MP8 is connected, output end voltage VOUT starts to increase, as output end voltage VOUT etc.
When reference voltage VBG, circuit start is completed, in steady-working state；But the once output of the regulator circuit
When voltage end VOUT access loads, load can bring overshoot voltage, cause to be stabilized output end voltage VOUT changes
It is unstable, corresponding counter-measure such as why not is taken, the regulator circuit will restart once, make output end voltage VOUT extensive
Stable state is arrived again, so extends the stabilization time of the regulator circuit, and causes the stability of the regulator circuit
It can not be high；In order to reduce the influence that access load brings the regulator circuit, reduce overshoot voltage, embodiment adds mutual
Fill switch unit 260 is that (inverted burst signal SWB overturnings are low electricity to high level by pulse signal SW overturnings when loading access
It is flat), control MP9 and MN7 shutdowns, the output voltage terminal VOUT of the regulator circuit is defeated with first order operation amplifier unit 220
Enter the path blockade between end, output voltage VO UT to be prevented to feed back to the input terminal of first order operation amplifier unit 220, simultaneously
MP10 and MN8 conductings, reference voltage VBG with the input terminal of first order operation amplifier unit 220 is connected, makes reference voltage VBG
The input terminal for being applied to first order operation amplifier unit 220 (loads the value of output voltage VO UT and reference voltage VBG before access
It is equal), it is achieved thereby that under the premise of the dc point of circuit is not influenced, circuit caused by eliminating the access of load is not
The problem of stablizing.
Specifically, it may refer to traditional low dropout voltage regulator shown in Fig. 4 and low voltage difference provided in this embodiment be steady
The power supply rejection ratio simulation comparison figure of volt circuit, wherein, horizontal axis represents the time (μ s), and the longitudinal axis represents voltage (V), and reference voltage is
3.8V, since overshoot voltage is that output voltage VO UT is caused to decline rapidly when access is loaded；It is imitative referring to first in Fig. 4
Output voltage linear decline when true 410,4 μ s of curve, traditional low dropout voltage regulator about make when 4.8 μ s
It obtains output voltage VO UT and is restored to 3.8V, about needing 0.8 μ s；And low dropout voltage regulator provided in this embodiment about exists
Output voltage VO UT is caused to be restored to 3.8V when 4.5 μ s, is about needing 0.5 μ s (referring to the second simulation curve in Fig. 4
420), it is seen that the time needed for circuit stability reduces by about one time, with obvious effects；Overshoot voltage is also reduced to from 3.92V simultaneously
3.82V.Wherein, third simulation curve 430 represents pulse signal SW in Fig. 4, and pulse signal SW is when access is loaded
High level.
The technical solution of the present embodiment on the basis of embodiment one, has each unit of the regulator circuit
Body reduces the overshoot voltage that load-strap is come, while reduces the time needed for circuit stability, and then reduces load to electricity
The influence of the stability on road improves the stability of circuit.
Note that it above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiment described here, can carry out for a person skilled in the art various apparent variations,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
It can include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (7)
1. a kind of regulator circuit, including：Voltage bias unit, first order operation amplifier unit, second level operation amplifier unit, more
Strangle compensating unit, control unit, which is characterized in that further include：
Complementary switch unit, respectively with the input of the output voltage terminal of the regulator circuit and the first order operation amplifier unit
End is connected, for when the output voltage terminal of the regulator circuit is connected and loaded, disconnecting the output electricity of the regulator circuit
Access between the input terminal of pressure side and the first order operation amplifier unit, conducting reference voltage are put with the first order operation
Access between big unit input terminal, so that the input terminal voltage of the first order operation amplifier unit is kept and reference voltage phase
Deng.
2. circuit according to claim 1, which is characterized in that the voltage bias unit includes：Second PMOS tube, third
PMOS tube, the first NMOS tube and third NMOS tube, wherein：
The source electrode of second PMOS tube is connected with power supply, and grid and drain electrode are connected with the drain electrode of first NMOS tube；Institute
The source electrode for stating third PMOS tube is connected with power supply, and grid is connected with the grid of second PMOS tube, drain electrode and the third
The drain electrode of NMOS tube is connected；The grid of first NMOS tube is connected with reference voltage, source electrode and the source of the third NMOS tube
Extremely it is connected；The drain electrode of the third NMOS tube is connected with grid.
3. circuit according to claim 2, which is characterized in that the first order operation amplifier unit includes：5th PMOS
Pipe, the 6th PMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube, wherein：
The source electrode of 5th PMOS tube is connected with power supply, and grid and drain electrode are connected with the drain electrode of the 5th NMOS tube；Institute
The source electrode for stating the 6th PMOS tube is connected with power supply, and grid is connected with the grid of the 5th PMOS tube, drain electrode and the described 6th
The drain electrode of NMOS tube is connected；The grid of 5th NMOS tube is connected with the output voltage terminal of the regulator circuit, source electrode and institute
It states the source electrode of the 6th NMOS tube and the drain electrode of the 4th NMOS tube is connected；The grid and reference voltage of 6th NMOS tube
It is connected；The grid of 4th NMOS tube is connected with the grid of the third NMOS tube, source electrode and the source electrode phase of third NMOS tube
Even.
4. circuit according to claim 3, which is characterized in that the second level operation amplifier unit includes：8th PMOS
Pipe, second resistance and 3rd resistor, wherein：
The source electrode of 8th PMOS tube is connected with power supply, and grid is connected with the drain electrode of the 6th PMOS tube, drain electrode with it is described
The first end of second resistance is connected, the first end and output voltage terminal of the second end of the second resistance and the 3rd resistor
It is connected, the second end of the 3rd resistor is connected to the ground.
5. circuit according to claim 4, which is characterized in that the Muller compensating unit includes, first resistor and first
Capacitance, wherein：The first end of the first resistor is connected with the drain electrode of the 6th PMOS tube, second end and first capacitance
First end be connected, the second end of first capacitance is connected with the drain electrode of the 8th PMOS tube.
6. circuit according to claim 5, which is characterized in that described control unit includes：First PMOS tube, the 4th PMOS
Pipe, the 7th PMOS tube and the second NMOS tube, wherein：
The source electrode of first PMOS tube is connected with power supply, and drain electrode is connected with the drain electrode of second PMOS tube, grid and control
Signal is connected；The grid of 4th PMOS tube is connected with control signal, and source electrode is connected with power supply, drain electrode and the 5th PMOS
The drain electrode of pipe is connected；The grid of 7th PMOS tube is connected with control signal, and source electrode is connected with power supply, drain electrode and the described 6th
The drain electrode of PMOS tube is connected；The grid of second NMOS tube is connected with revertive control signal, drain electrode and the third NMOS tube
Drain electrode is connected, and source electrode is connected to the ground.
7. circuit according to claim 6, which is characterized in that the complementary switch unit includes：7th NMOS tube, the 8th
NMOS tube, the 9th PMOS tube and the tenth PMOS tube, wherein, the grid of the 9th PMOS tube is connected with pulse signal, source electrode point
Output voltage terminal not with the drain electrode of the 7th NMOS tube and the regulator circuit is connected, drain electrode and the 7th NMOS tube
Source electrode is connected with the input terminal of the first order operation amplifier unit；The grid of 7th NMOS tube and inverted burst signal phase
Even；The grid of tenth PMOS tube is connected with inverted burst signal, drain electrode and reference voltage of the source electrode with the 8th NMOS tube
It is connected, drain electrode is connected with the source electrode of the 8th NMOS tube and the input terminal of the first order operation amplifier unit；Described
The grid of eight NMOS tubes is connected with pulse signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611130365.1A CN108227800B (en) | 2016-12-09 | 2016-12-09 | Voltage stabilizing circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611130365.1A CN108227800B (en) | 2016-12-09 | 2016-12-09 | Voltage stabilizing circuit |
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| CN108227800A true CN108227800A (en) | 2018-06-29 |
| CN108227800B CN108227800B (en) | 2024-06-14 |
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| CN201611130365.1A Active CN108227800B (en) | 2016-12-09 | 2016-12-09 | Voltage stabilizing circuit |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02137008A (en) * | 1988-11-18 | 1990-05-25 | Nec Corp | Stabilized power supply circuit |
| CN1448818A (en) * | 2002-03-28 | 2003-10-15 | 华邦电子股份有限公司 | Voltage regulator having bidirectional current |
| TW200513821A (en) * | 2003-10-01 | 2005-04-16 | Mediatek Inc | Fast-disabled voltage regulator circuit with low-noise feedback loop |
| US20100014356A1 (en) * | 2008-07-17 | 2010-01-21 | Nan Wang | Sense amplifier used in electrically erasable programmable read-only memory and the implementing method thereof |
| US20130099770A1 (en) * | 2010-12-15 | 2013-04-25 | Liang Cheng | Reference power supply circuit |
| TW201351085A (en) * | 2012-06-13 | 2013-12-16 | Elite Semiconductor Esmt | Low dropout regulator with improved transient response |
| CN204858519U (en) * | 2015-08-15 | 2015-12-09 | 重庆宁来科贸有限公司 | Sound and common bi -polar protective power supply of warning of light |
| CN105475215A (en) * | 2015-11-30 | 2016-04-13 | 成都聚汇才科技有限公司 | Intelligent fish tank aerator control system based on bridge rectifier and voltage regulator circuit |
| CN106100321A (en) * | 2016-07-18 | 2016-11-09 | 东南大学 | A kind of complementary feedback formula gate switch charge pump circuit |
-
2016
- 2016-12-09 CN CN201611130365.1A patent/CN108227800B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02137008A (en) * | 1988-11-18 | 1990-05-25 | Nec Corp | Stabilized power supply circuit |
| CN1448818A (en) * | 2002-03-28 | 2003-10-15 | 华邦电子股份有限公司 | Voltage regulator having bidirectional current |
| TW200513821A (en) * | 2003-10-01 | 2005-04-16 | Mediatek Inc | Fast-disabled voltage regulator circuit with low-noise feedback loop |
| US20100014356A1 (en) * | 2008-07-17 | 2010-01-21 | Nan Wang | Sense amplifier used in electrically erasable programmable read-only memory and the implementing method thereof |
| US20130099770A1 (en) * | 2010-12-15 | 2013-04-25 | Liang Cheng | Reference power supply circuit |
| TW201351085A (en) * | 2012-06-13 | 2013-12-16 | Elite Semiconductor Esmt | Low dropout regulator with improved transient response |
| CN204858519U (en) * | 2015-08-15 | 2015-12-09 | 重庆宁来科贸有限公司 | Sound and common bi -polar protective power supply of warning of light |
| CN105475215A (en) * | 2015-11-30 | 2016-04-13 | 成都聚汇才科技有限公司 | Intelligent fish tank aerator control system based on bridge rectifier and voltage regulator circuit |
| CN106100321A (en) * | 2016-07-18 | 2016-11-09 | 东南大学 | A kind of complementary feedback formula gate switch charge pump circuit |
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