TW201351085A - Low dropout regulator with improved transient response - Google Patents

Abstract

The present disclosure relates to a low dropout regulator (LDO) with improved transient response. The low dropout regulator includes an input terminal, an output terminal, a power transistor, a feedback circuit, and an error amplifier. The power transistor has a source connected to the input terminal, a drain connected to the output terminal, and a gate connected to the error amplifier. The error amplifier includes an input differential pair, a gain stage, an output stage, and a transient enhanced circuit. In accordance with an increasing load current transient, the transient enhanced circuit generates an output voltage with logic high level so as to reduce the voltage level of an output voltage from the output stage.

Description

Low dropout regulator with improved transient response

The present invention is directed to a low dropout regulator having improved transient response.

In low dropout voltage regulator applications, the load current has a large effect on its transient response. When the low-dropout regulator needs to provide a small load current, the output transistor can easily supply the required current, so it does not have much effect on its transient response. However, when the low-dropout regulator needs to supply a large load current, the output transistor cannot provide the required current immediately, so in the transient response, the output voltage of the low-dropout regulator will drop until the output transistor can provide At high currents, it will gradually return to the original voltage level.

1 shows a circuit diagram of a low voltage drop regulator 10 of the prior art. Referring to FIG. 1, the low-dropout voltage regulator 10 includes a bandgap voltage generator 101, an error amplifier 102, an output transistor 103, a first resistor 104, a second resistor 105, and an output capacitor 106. .

The source and drain of the output transistor 103 are coupled to the input and output of the low dropout regulator 10, respectively. The first resistor 104 and the second resistor 105 form a voltage dividing circuit to provide a feedback voltage V _FB proportional to the output voltage V _OUT to the positive input terminal of the error amplifier 102. The error amplifier 102 is configured to amplify a difference between a reference voltage V _REF provided by the bandgap voltage generator 101 and a negative input terminal of the error amplifier 102 and the feedback voltage V _FB to generate an output voltage V _{C .} To the gate of the output transistor 103. When a load current I _LOAD changes, the error amplifier 102 appropriately adjusts the output voltage V _C to change the source of the power transistor 103 by detecting the difference between the feedback voltage V _FB and the reference voltage V _REF . The pole-gate voltage difference provides sufficient output current to the load to stabilize the output voltage V _OUT .

However, in the prior art, when the load current I _LOAD is rapidly converted from a small load current to a large load current (hereinafter referred to as a load current transient increase), the output voltage V _{OUT is} significantly and rapidly reduced. After a short period of time, the output transistor 103 reacts to the change in the output voltage V _OUT to provide the desired load current, returning the output voltage to the set voltage value. In other words, the low voltage drop regulator of the prior art is limited by the poor transient response of the error amplifier 102, which in turn affects the recovery time of the output voltage V _OUT .

Therefore, it is necessary to propose an improved error amplifier to improve the transient response of the low dropout regulator.

The present invention provides a low dropout regulator having improved transient response including an input, an output, a power transistor, a feedback network, and an error amplifier. The input is for receiving a DC voltage source. The output is used to generate a DC output voltage. The source of the power transistor is connected to the input and its drain is connected to the output. The feedback network is coupled to the output and configured to generate a feedback voltage according to the DC output voltage. The error amplifier is coupled to one of the gates of the power transistor and includes an input differential stage, a gain stage, an output stage, and a transient acceleration circuit. The input The differential stage is configured to receive the feedback voltage and a reference voltage to generate a first output voltage. The gain stage is configured to receive the first output voltage to generate a second output voltage. The output stage is configured to receive the second output voltage and a third output voltage to generate a fourth output voltage. The transient acceleration circuit is configured to receive the first output voltage to generate the third output voltage. The transient acceleration circuit generates the third output voltage having a high logic voltage level to reduce the voltage level of the fourth output voltage according to a load current transient increase condition.

2 shows a block diagram of a low dropout regulator 20 with improved transient response in accordance with an embodiment of the present invention. Referring to FIG. 2, the low dropout regulator 20 includes an input to receive a DC voltage source V _IN and an output to generate a DC output voltage V _OUT . The low-dropout regulator 20 includes a power transistor 205 connected in series to the input terminal and the output terminal, a source coupled to the input terminal, a gate coupled to an error amplifier 21, and a drain coupled Connect to the output. The low dropout regulator 20 further includes an output capacitor 208 coupled to the output and a feedback network 206. In the present embodiment, the feedback network 206 is composed of a series resistor R ₁ and a resistor R ₂ . The feedback network 206 is configured to generate a feedback voltage V _FB according to the DC output voltage V _OUT ratio.

Referring to FIG. 2, the error amplifier 21 includes an input differential stage 212, a gain stage 214, an output stage 216, and a transient acceleration circuit 218. The input differential stage 212 is configured to receive the feedback voltage V _FB and a reference voltage V _REF to generate an output voltage V ₁ . The gain stage 214 is configured to receive the output voltage V ₁ to generate an output voltage V ₂ . The output stage 216 is configured to receive the output voltage V ₂ and an output voltage V ₃ to generate an output voltage V _G . The transient acceleration circuit 218 is configured to receive the output voltage V ₁ to generate the output voltage V ₃ .

Fig. 3 is a detailed circuit diagram of the error amplifier 21 in accordance with an embodiment of the present invention. Referring to FIG. 3, the input differential stage 212 of the error amplifier 21 includes differential pair transistors M ₁ and M ₂ , diode transistors connected to load transistors M ₃ and M _{4 ,} and a bias current source I. _B1 . The bias current source I _B1 provides a bias current to the differential pair of transistors M ₁ and M ₂ . The drain and gate of the load transistor M ₃ are short-circuited to the transistor M ₁ , and the drain and gate of the load transistor M ₄ are short-circuited to the transistor M ₂ . After receiving the feedback voltage V _FB and the reference voltage V _REF , the input differential stage 212 is at the gate of the load transistor M ₄ according to the difference between the feedback voltage V _FB and the reference voltage V _REF This output voltage V _{1 is} generated.

Referring to FIG. 3, in the present embodiment, the gain stage 214 includes transistors M ₅ , M ₆ , M _{7 ,} and M ₈ . The gain stage 214 generates the output voltage V ₂ after receiving the output voltage V ₁ generated by the input differential stage 212. The output stage 216 includes transistors M ₉ and M ₁₀ connected in series, wherein the transistor M _{9 is configured} to receive the output voltage V ₂ generated by the gain stage 214, and the transistor M _{10 is configured} to receive the transient acceleration the output circuit 218 generates a voltage V _3. The output stage 216 generates the output voltage V _G according to the voltages V ₂ and V ₃ for driving the gate of the power transistor 205 as shown in FIG. Depending on the voltage level of the gate of the power transistor 205, the power transistor 205 will output an appropriate current to supply the load current I _LOAD .

Referring to FIG. 3, the transient acceleration circuit 218 includes a voltage to current circuit 32, a bias current source I _B2, and a current mirror circuit 34. The voltage-to-current circuit 32 is configured to receive the output voltage V ₁ generated by the input differential stage 212 to generate an output current I ₁ . The current mirror circuit 34 is configured to receive the output current I ₁ and the bias current source I _B2 to generate the output voltage V ₃ . In this embodiment, the voltage-to-current circuit 32 includes transistors M ₁₂ , M _{14 ,} and M ₁₆ , wherein the transistor M _{12 is configured} to receive the output voltage V ₁ , and the transistors M ₁₄ and M _{16 are} formed. a current mirror configuration which receives the output current to form the current I ₁ from the amplifying transistor M _12.

The current mirror circuit 34 includes transistors M ₁₈ , M ₁₉ and M ₂₀ . The drain and gate of the transistor M ₁₈ are shorted to the drain of the transistor M ₁₆ . The transistor M _{18 is configured} to receive the output current I ₁ to provide a bias voltage V _B . The transistors M ₁₉ and M ₂₀ form a stacked configuration in which the gate of the transistor M ₁₉ receives the bias voltage V _B and the drain receives the current of the bias current source I _B2 . The drain of the transistor M ₁₉ produces the output voltage V ₃ . The output voltage V ₃ to provide the transistor M ₁₀ of the output stage 216, to bias the transistor M ₁₀ generates an appropriate current, thereby controlling the power transistor.

The operation of the low dropout regulator 20 of the present invention will now be described with reference to Figs. 2 through 3. When the current value of the load current I _LOAD is the minimum value of the rated load current, the voltage level of the feedback voltage V _FB generated according to the DC output voltage V _OUT ratio is close to the voltage level of the reference voltage V _REF . Thus, the flow through the error amplifier 21 in the plurality of differential pair transistors M and M ₂ will be equal to the current _one. Based on the current flowing through the transistor M ₂ , the load transistor M ₄ generates an appropriate bias voltage value V ₁ (=V _{GS, M4} ) to bias the transistor M ₈ in the gain stage 214 and the transient state. The transistor M ₁₂ in the acceleration circuit 218. By the biasing method described above, a smaller source-gate voltage difference of the power transistor 205 is generated to supply the rated load current minimum.

When the load current transient increases, since the source-gate voltage difference of the power transistor 205 cannot be changed immediately, the voltage level of the DC output voltage V _OUT will first decrease due to the transient increase of the load current, so that the ratio The generated voltage level of the feedback voltage V _FB will be less than the voltage level of the reference voltage V _REF . In this case, the bias current of the bias current source I _B1 in the input differential stage 212 will all flow through the transistor M ₁ such that the current flowing through the transistor M ₂ approaches zero. Therefore, the input differential stage 212 produces the output voltage V ₁ that is close to zero. The output voltage V ₁ near zero operates via the gain stage 214 and outputs a high logic voltage level V ₂ proximate to the DC voltage source V _IN such that the transistor M ₉ in the output stage 216 is turned off.

At the same time, the output voltage V ₁ near 0 will generate an output current I ₁ close to 0 after passing through the voltage-to-current circuit 32 in the transient acceleration circuit 218. According to the output current I ₁ , the transistor M ₁₈ in the current mirror circuit 34 generates a bias voltage V _B close to zero, causing the transistor M _{19 to be} turned off. When the transistor M ₁₉ is turned off, the transient acceleration circuit 218 will quickly output a high logic voltage level V ₃ close to the supply voltage source V _IN . Since the transistor M ₉ in the output stage 216 is in an off state at this time, and the transistor M _{10 is} fully turned on (V _{GS, M10} = V ₃ = V _IN ), the power transistor 205 generates a large source. - Gate differential (V _{GS, 205} = V _IN ) to supply the maximum rated load current.

According to the structure of the error amplifier 21 disclosed in the present invention, the transient response of the low-dropout regulator 20 can be improved by the operation of the transient acceleration circuit 218 and the output stage 216. When the output voltage V _OUT decreases as the load current I _LOAD rises abruptly, because the transistor M ₉ in the output stage 216 is turned off, the transient acceleration circuit 218 will quickly generate a push voltage V ₃ to speed up The transistor M ₁₀ in the output stage 216 is turned on. Accordingly, the power transistor 205 reacts quickly to supply more current to the output, thereby increasing the output voltage _VOUT and returning to the original voltage.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

10‧‧‧Low Dropout Regulator

101‧‧‧gap voltage generator

102‧‧‧Error amplifier

103‧‧‧Output transistor

104,105‧‧‧resistance

106‧‧‧Output capacitor

20‧‧‧Low Dropout Regulator

205‧‧‧Power transistor

206‧‧‧Return to the network

208‧‧‧output capacitor

21‧‧‧Error amplifier

212‧‧‧Input differential level

214‧‧‧ Gain level

216‧‧‧Output

218‧‧‧Transient acceleration circuit

32‧‧‧voltage to current circuit

34‧‧‧current mirror circuit

I _LOAD ‧‧‧Load current

I _B1 , I _B2 ‧‧‧ bias current source

R ₁ , R ₂ ‧‧‧ resistance

M ₁ ~M ₁₀ , M ₁₂ , M ₁₄ , M ₁₆ , M ₁₈ , M ₁₉ , M ₂₀ ‧‧‧O crystal

The technical features and advantages of the present invention are fully understood by reference to the foregoing description and the accompanying drawings.

1 shows a circuit diagram of a low voltage drop regulator of the prior art; FIG. 2 shows a block diagram of a low dropout regulator with improved transient response in accordance with an embodiment of the present invention; and FIG. 3 shows an embodiment of the present invention. Detailed circuit diagram of the error amplifier.

20‧‧‧Low Dropout Regulator

205‧‧‧Power transistor

206‧‧‧Return to the network

208‧‧‧output capacitor

21‧‧‧Error amplifier

212‧‧‧Input differential level

214‧‧‧ Gain level

216‧‧‧Output

218‧‧‧Transient acceleration circuit

I _LOAD ‧‧‧Load current

R ₁ , R ₂ ‧‧‧ resistance

Claims (6)

A low-dropout voltage regulator with improved transient response, comprising: an input terminal for receiving a DC voltage source; an output terminal for generating a DC output voltage; and a power transistor having a source connected to the source An input terminal and a drain connected to the output terminal; a feedback network coupled to the output terminal for generating a feedback voltage according to the DC output voltage; and an error amplifier coupled to the power transistor a gate comprising: an input differential stage for receiving the feedback voltage and a reference voltage to generate a first output voltage; and a gain stage for receiving the first output voltage to generate a second output a voltage output; an output stage for receiving the second output voltage and a third output voltage to generate a fourth output voltage; and a transient acceleration circuit for receiving the first output voltage to generate the third output voltage The transient acceleration circuit generates the third output voltage having a high logic voltage level to lower the voltage level of the fourth output voltage according to a load current transient increase condition. The low dropout regulator of claim 1, wherein the output stage comprises: a first transistor for receiving the second output voltage to generate the fourth output voltage; a second transistor for receiving the third output voltage to generate the fourth output voltage; wherein, when the feedback voltage transiently increases, the gain stage generates the second output voltage having a high logic voltage level The first transistor is turned off, and the transient acceleration circuit generates the third output voltage having a high logic voltage level to turn on the second transistor. The low-dropout voltage regulator according to claim 1, wherein the transient acceleration circuit comprises: a voltage-to-current circuit for receiving the first output voltage to generate an output current; a bias current source; and a first a current mirror circuit for receiving the output current and the current of the bias current source to generate the third output voltage. The low-dropout voltage regulator according to claim 1, wherein the input differential stage comprises: a first transistor for receiving the feedback voltage; and a second transistor for receiving the reference voltage; a three-electrode having a drain and a gate short-circuited to the first transistor; a fourth transistor having a drain and a gate short-circuited to the second transistor, and a gate thereof generating the first output voltage And a bias current source for providing current to the first transistor and the second transistor. The low-dropout voltage regulator according to claim 3, wherein the voltage-to-current circuit comprises: a first transistor for receiving the first output voltage; and a second current mirror circuit connected to the first battery A crystal for generating the output current. The low-dropout voltage regulator according to claim 3, wherein the first current mirror circuit comprises: a first transistor having a drain and a gate short-circuited to the voltage-to-current circuit for generating a bias voltage And a second transistor having a gate for receiving the bias voltage and a drain connected to the bias current source to generate the third output voltage.