CN108205517A - A kind of FFT multiplexing methods - Google Patents

A kind of FFT multiplexing methods Download PDF

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CN108205517A
CN108205517A CN201611187723.2A CN201611187723A CN108205517A CN 108205517 A CN108205517 A CN 108205517A CN 201611187723 A CN201611187723 A CN 201611187723A CN 108205517 A CN108205517 A CN 108205517A
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fft
data
period
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clock cycle
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CN108205517B (en
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陈望杰
鲍成浩
李仙法
张健伟
杨健
吴鸿海
靳东
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8511 Research Institute of CASIC
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    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms

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Abstract

The present invention provides a kind of FFT multiplexing methods, includes the following steps：Step 1, it carries out D times according to externally input high-speed sample data to extract, and data is extracted to each single item and carry out digital filtering；Step 2, within the continuous K/D clock cycle, e is carried out to filtering output data respectively‑2πk/KFrequency displacement is handled；Step 3, within the continuous K/D clock cycle, obtained data are subjected to transformation from serial to parallel conversion, K/D clock cycle updates a data；Step 4, the processing of D points parallel FFT is carried out respectively to D point datas, and each clock cycle within K/D period carries out multiplexing process respectively to FFT result；Step 5, to obtaining D point FFT results by each period the result of K points FFT is collectively constituted into rearrangement, and according to engineering demand Sequential output.

Description

A kind of FFT multiplexing methods
Technical field
The present invention relates to a kind of signal processing technology, particularly a kind of FFT multiplexing methods.
Background technology
Fast Fourier Transform (FFT) (FFT) is a kind of fast algorithm of discrete Fourier transform (DFT), is description discrete signal The important mathematical tool of time domain and frequency domain relationship, is used widely in terms of Digital Signal Processing.Traditional fft algorithm can be with It is realized using software, DSP, special FFT processing chips or FPGA etc..Wherein, the speed that software and DSP are realized is slower, no The requirement that high speed signal is handled in real time in Digital Receiver can be met；Although special FFT processing chips speed, valency Lattice are expensive, are not easy to be widely popularized.FPGA has that resourceful, speed is fast, flexible design, is widely used in recent years.
The fft processor designing scheme that FPGA is realized at present can be divided into serial process and parallel processing according to data flow.String Row processing be each butterfly computation only with a butterfly unit, processing mode is fairly simple, and arithmetic speed is relatively slow.Parallel place Reason arithmetic speed is very fast, and the resource of occupancy is also relatively more, this carrys out all more nervous system in certain spaces and hardware resource It says particularly difficult.Therefore a kind of FFT multiplexing methods are proposed, are multiplexed by butterfly processing element, operated using half parallel pipelining process, Contradiction between active balance FPGA inter-process speed and resource consumption effectively reduces the demand to logical resource, meets The demand of engineer application.
Invention content
The purpose of the present invention is to provide a kind of FFT multiplexing methods, include the following steps：
Step 1, it carries out D times according to externally input high-speed sample data to extract, and data is extracted into line number to each single item Word filters；
Step 2, within the continuous K/D clock cycle, e is carried out to filtering output data respectively-j2πk/KFrequency displacement is handled, In, k=0~K/D-1；
Step 3, within the continuous K/D clock cycle, obtained data are subjected to transformation from serial to parallel conversion, at K/D The clock period updates a data；
Step 4, the processing of D points parallel FFT, and each clock cycle pair within K/D period are carried out respectively to D point datas FFT result carries out multiplexing process respectively；
Step 5, to obtaining D point FFT results by each period the result of K points FFT is collectively constituted into rearrangement, and according to work Journey demand Sequential output.
Compared with prior art, the present invention its remarkable advantage is：(1) it is multiplexed by butterfly processing element, optimizes FFT module Logical resource occupies；(2) it is operated using half parallel pipelining process, improves high-speed data processing capacity；(3) inside active balance FPGA Manage the contradiction between speed and resource consumption；(4) output data is ranked up, reduces system processing complexity.
The present invention is described further with reference to the accompanying drawings of the specification.
Description of the drawings
Fig. 1 is flow chart of the method for the present invention.
Fig. 2 is the data flow diagram of 32 Parallel FFTs.
Specific embodiment
With reference to Fig. 1, Fig. 2, a kind of FFT multiplexing methods, which is characterized in that include the following steps：
Step 1, it carries out D times according to externally input high-speed sample data to extract, and data is extracted into line number to each single item Word filters；
Step 2, within the continuous K/D clock cycle, e is carried out to filtering output data respectively-j2πk/KFrequency displacement is handled, In, k=0~K/D-1；
Step 3, within the continuous K/D clock cycle, obtained data are subjected to transformation from serial to parallel conversion, at K/D The clock period updates a data；
Step 4, the processing of D points parallel FFT, and each clock cycle pair within K/D period are carried out respectively to D point datas FFT result carries out multiplexing process respectively；
Step 5, to obtaining D point FFT results by each period the result of K points FFT is collectively constituted into rearrangement, and according to work Journey demand Sequential output.
Step 1, which is divided, extracts and filtering following steps high-speed sample data progress for D times：
Step 11, the high-speed sample data split-phase of input is acquired first and latched；
Step 12, each phase data is extracted according to D times；
Step 13, it extracts sampled data according to D times and equivalent extraction preparation is carried out to FIR low pass filter coefficient；
Step 14, it extracts sampled data according to D times and matches D times and extract FIR low pass filter coefficient and be filtered.
Step 2 specifically includes following steps：
Step 21, according to the e in each K/D period-j2πk/KFrequency displacement is handled, wherein, k=0~K/D-1 prepares frequency displacement Coefficient；
Step 22, it exports filtering data according to each K/D period with frequency displacement coefficient again to be multiplied, realizes removing for frequency It moves.
Each clock cycle of the step 4 within K/D period carries out multiplexing process, tool to the FFT result of D point parallel datas Body includes the following steps：
Step 41, input frequency-shift data prepares, and the data inputted in K/D period are x (m), x (m+D), x (m+D*2), x (m++D*3) ..., x (m+ (K/D-1) * D) data；
Step 42, using the frequency shift property of FFT within K/D period K points FFT is realized with D points FFT.
Step 5 specifically includes following steps：
Step 51, according to D points FFT outputs each in K/D period as a result, being transformed into the result sequence of K points FFT；
Step 52, change the frequency displacement direction in each period D point FFT in K/D period, and then change each period output The result sequence of FFT；
Step 53, adjacency channel conversion is carried out to the FFT result at the odd even moment in result, realizes the result sequence of FFT Arrangement output.
Embodiment
If the wave filter group (K=64) of 64 channels, high speed signal sample rate f s is 2.6GHz, and external AD is divided into 8 phases (carry out 8 times extraction, D=8) into FPGA, per phase data rate 325MHz, i.e. FPGA operating rates 325MHz；Wave filter group exports Rate fo=fs/64=40.625MHz, multiplexing multiple=fpga operating rates/output speed=325/ of each phase data 40.625=8, i.e., 8 times multiplexings；It is as follows：
Step 1, it carries out D times according to externally input high-speed sample data to extract, and data is extracted into line number to each single item Word filters；
Step 11,2.6GHz 8 phases of high-speed sample data point of input are carried out FPGA acquisitions first to latch；
Step 12, each phase data is according to 8 times of extractions；
Step 13, it extracts sampled data according to 8 times and equivalent extraction preparation is carried out to FIR low pass filter coefficient；
Step 14,8 times of extraction FIR low pass filter coefficients of sampled data matching are extracted according to 8 times to be filtered.
Step 2, within continuous 8 clock cycle, e is carried out to filtering output data respectively-j2πk/8Frequency displacement is handled, wherein, k =0~7；
Step 21, according to the e in each K/D period-j2πk/KFrequency displacement is handled, wherein, k=0~K/D-1 prepares frequency displacement Coefficient；
Step 22, it exports filtering data according to each K/D period with frequency displacement coefficient again to be multiplied, realizes removing for frequency It moves.
Step 3, within continuous 8 clock cycle, obtained data are subjected to transformation from serial to parallel conversion, 8 clock weeks Phase updates a data；
Step 4, to the difference D points parallel FFT processing of D point datas, and each clock cycle within K/D period is to FFT As a result multiplexing process is carried out respectively；
Step 41, input frequency-shift data prepares, and the data inputted in 8 periods are x (m), x (m+8), x (m+16), x (m+ 24) ..., x (m+63) data；
Step 42,64 point FFT are realized with 8 point FFT within 8 periods using the frequency shift property of FFT；
8 FFT data b (m) within every 8 periods are：
8 point FFT operations are carried out to b (m), obtained FFT result sequence sorts as shown in table 1.
Table 1 realizes 64 point FFT output result sequence lists with 8 point FFT
En8 1 0 0 0 0 0 0 0
Q0 0 63 62 61 60 59 58 57
Q1 32 31 30 29 28 27 26 25
Q2 16 15 14 13 12 11 10 9
Q3 48 47 46 45 44 43 42 41
Q4 8 7 6 5 4 3 2 1
Q5 40 39 38 37 36 35 34 33
Q6 24 23 22 21 20 19 18 17
Q7 56 55 54 53 52 51 50 49
Wherein, the sequence in every 8 periods is distinguished according to En8, and obtains each branch output result.
Step 5, the result of 64 point FFT is collectively constituted into rearrangement to obtaining 8 FFT results by each period, and according to Engineering demand Sequential output.
Step 51, according to 8 point FFT outputs each in 8 periods as a result, the result sequence of 64 point FFT is transformed into, such as table 1 It is shown；
Step 52, change the frequency displacement direction in each 8 point FFT of period in 8 periods, and then change each period output The result sequence of FFT；
Conventional frequency displacement direction is according to 0~7 sequence frequency displacement, due to the symmetry of frequency displacement, using [01-12-23-34] sequentially into Line frequency shifting is handled, and the results are shown in Table 2.
Table 2 changes 64 point FFT output result sequence lists after frequency displacement
En8 1 0 0 0 0 0 0 0
Q0 0 63 1 62 2 61 3 60
Q1 32 31 33 30 34 29 35 28
Q2 16 15 17 14 18 13 19 12
Q3 48 47 49 46 50 45 51 44
Q4 8 7 9 6 10 5 11 4
Q5 40 39 41 38 42 37 43 36
Q6 24 23 25 22 26 21 27 20
Q7 56 55 57 54 58 53 59 52
Step 53, adjacency channel conversion is carried out to the FFT result at the odd even moment in result, realizes the result sequence of FFT Arrangement output.
First, for table 2, the adjacent rows at strange moment are subjected to data exchange, obtain that the results are shown in Table 3.
64 point FFT outputs result sequence list after the exchange of 3 strange moment of table
En8 1 0 0 0 0 0 0 0
Q0 63 62 61 60 59 58 57 56
Q1 0 1 2 3 4 5 6 7
Q2 31 33 29 35 27 37 25 39
Q3 32 30 34 28 36 26 38 24
Q4 47 49 45 51 43 53 41 55
Q5 16 14 18 12 20 10 22 8
Q6 15 17 13 19 11 21 9 23
Q7 48 46 50 44 52 42 54 40
Again, it will not go together and be ranked up by incremental order, as shown in table 4.
Table 4 changes 64 point FFT output result sequence lists after row sequence
Finally, six intermediate rows are remake with the exchange of primary simple adjacent rows at the odd number moment, you can obtain finally by It is exported according to the FFT result of sequence sequence, as shown in table 5.
64 point FFT outputs result sequence list after table 5 sorts
En8 1 0 0 0 0 0 0 0
Q1 0 1 2 3 4 5 6 7
Q6 15 14 13 12 11 10 9 8
Q5 16 17 18 19 20 21 22 23
Q2 31 30 29 28 27 26 25 24
Q3 32 33 34 35 36 37 38 39
Q4 47 46 45 44 43 42 41 40
Q7 48 49 50 51 52 53 54 55
Q0 63 62 61 60 59 58 57 56

Claims (5)

1. a kind of FFT multiplexing methods, which is characterized in that include the following steps：
Step 1, it carries out D times according to externally input high-speed sample data to extract, and data is extracted to each single item and carry out digital filter Wave；
Step 2, within the continuous K/D clock cycle, e is carried out to filtering output data respectively-j2πk/KFrequency displacement is handled, wherein, k=0 ~K/D-1；
Step 3, within the continuous K/D clock cycle, obtained data are subjected to transformation from serial to parallel conversion, K/D clock week Phase updates a data；
Step 4, the processing of D points parallel FFT is carried out respectively to D point datas, and each clock cycle within K/D period is to FFT As a result multiplexing process is carried out respectively；
Step 5, to obtaining D point FFT results by each period the result of K points FFT is collectively constituted into rearrangement, and need according to engineering Seek Sequential output.
2. according to the method described in claim 1, it is characterized in that, step 1 divide to high-speed sample data carry out D times extract and filter Wave following steps：
Step 11, the high-speed sample data split-phase of input is acquired first and latched；
Step 12, each phase data is extracted according to D times；
Step 13, it extracts sampled data according to D times and equivalent extraction preparation is carried out to FIR low pass filter coefficient；
Step 14, it extracts sampled data according to D times and matches D times and extract FIR low pass filter coefficient and be filtered.
3. according to the method described in claim 1, it is characterized in that, step 2 specifically includes following steps：
Step 21, according to the e in each K/D period-j2πk/KFrequency displacement is handled, wherein, k=0~K/D-1 prepares frequency displacement coefficient；
Step 22, it exports filtering data according to each K/D period with frequency displacement coefficient again to be multiplied, realizes moving for frequency.
4. according to the method described in claim 1, it is characterized in that, each clock cycle of the step 4 within K/D period to D The FFT result of point parallel data carries out multiplexing process, specifically includes following steps：
Step 41, input frequency-shift data prepares, and the data inputted in K/D period are x (m), x (m+D), x (m+D*2), x (m++ D*3) ..., x (m+ (K/D-1) * D) data；
Step 42, using the frequency shift property of FFT within K/D period K points FFT is realized with D points FFT.
5. according to the method described in claim 1, it is characterized in that, step 5 specifically includes following steps：
Step 51, according to D points FFT outputs each in K/D period as a result, being transformed into the result sequence of K points FFT；
Step 52, change the frequency displacement direction in each period D point FFT in K/D period, and then change the FFT of each period output Result sequence；
Step 53, adjacency channel conversion is carried out to the FFT result at the odd even moment in result, realizes that the result of FFT is ranked sequentially Output.
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CN112732339A (en) * 2021-01-20 2021-04-30 上海微波设备研究所（中国电子科技集团公司第五十一研究所） Time division multiplexing time extraction FFT implementation method, system and medium

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Publication number Priority date Publication date Assignee Title
CN111339484A (en) * 2020-02-20 2020-06-26 中国科学院自动化研究所 Method and device for realizing large radio interference array correlator based on FPGA
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