CN108182164A - The SoC interface circuit and access method that a kind of data address is adaptively converted - Google Patents
The SoC interface circuit and access method that a kind of data address is adaptively converted Download PDFInfo
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- CN108182164A CN108182164A CN201711232993.5A CN201711232993A CN108182164A CN 108182164 A CN108182164 A CN 108182164A CN 201711232993 A CN201711232993 A CN 201711232993A CN 108182164 A CN108182164 A CN 108182164A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
Abstract
The SoC interface circuit and access method that a kind of data address is adaptively converted, SoC interface circuit include：The generation module of direction controlling direction signals, the generation module of data and the selection of address sel signals, address latch allow the generation module of ale signal and bidirectional buffering generation module.The present invention is realized processor and the data address of CAN controller is adaptively converted by address to processor independence, data to 8 bit address of CAN controller, the interface circuit design of data-reusing channel.The present invention realizes address, data time-sharing multiplex using bidirectional buffering generation module, simplifies design, improves work efficiency.
Description
Technical field
The SoC interface circuit and access method adaptively converted the present invention relates to a kind of data address belong to interface access
Field.
Background technology
Previous designs the address for being directed to CAN controller, the situation of data/address bus time-sharing multiplex using processing
Device sends operational order twice and completes the once read/write operation to CAN controller register.First time operational order will
CAN controller address and data multiplex bus, second of operation are sent into the address of the CAN controller register of access
Data in CAN controller register if carrying out the read operation to CAN controller, are read in processor by instruction,
If carrying out the write operation of CAN controller, data are written to the register of CAN controller from processor.By turning
It changes into and meets CAN controller read/write cycles sequential, most CAN controller is hung on a processor at last.This access side
Formula, which needs processor to send operational order twice, could complete once to the access of CAN controller, and access cycle is long, accesses
Efficiency is low.
How to improve processor is the technical issues of this field is urgently to be resolved hurrily to the access speed of CAN controller.
The design passes through the processing to address data selecting module and set direction module, it is only necessary to which processor sends primary
Operational order can just complete the read/write operation to CAN controller register, substantially reduce the operating time, improve behaviour
Make efficiency, improve properties of product.
Invention content
The technology of the present invention solves the problems, such as：The present invention provides the SoC interface circuit that a kind of data address is adaptively converted
And access method, the processing that this method passes through address date selecting module and set direction module, it is only necessary to which processor sends one
Secondary operational order can just complete the read/write operation to CAN controller register, need transmission two so as to overcome processor
Secondary operational order could be completed once to access the shortcomings that access efficiency brought is low to CAN controller.
The present invention technical solution be：
The SoC interface circuit that a kind of data address is adaptively converted is provided, realizes visit of the processor to CAN controller
It asks, including ALE generation modules, direction generation modules, sel generation modules and bidirectional buffering generation module；
The ALE generation modules receive the clock signal of processor output, input/output space chip selection signal, generate address latch
Allow the address latch of signal ALE to CAN controller to allow to hold, address latch allows signal in input/output space chip selection signal
Falling edge exports the high level signal for continuing half of clock cycle；
Direction generation modules receive the clock signal of processor output, input/output space chip selection signal and input/output space
Enable signal is read, generates direction control signal direction, direction control signal becomes in input/output space chip selection signal falling edge
For low level, read to become high level when the arrival of enable signal failing edge or the arrival of input/output space chip selection signal rising edge in space；
Sel generation modules receive the clock signal and input/output space chip selection signal of processor output, generate selection signal sel,
Selection signal sel generates the low level signal for continuing a clock cycle in input/output space chip selection signal failing edge, other
Moment is high level signal；
The most-significant byte data of bidirectional buffering generation module reception processor output, least-significant byte address, the two-way control of processor data
End signal processed, selection signal sel and direction control signal direction；By processor most-significant byte data, least-significant byte address is chosen
The data address multiplexed signals formed after sel signal behaviors is input to the input terminal I of bidirectional buffering generation module；Direction controlling is believed
After number direction carries out logical AND with processor data double-direction control end signal, it is input to making for bidirectional buffering generation module
It can end OEN；The data address multiplexed signals interface of CAN controller is connected to the bidirectional end PAD of bidirectional buffering generation module；
The most-significant byte data input pin of the output terminal C connection processing devices of bidirectional buffering generation module.
Preferably, the ALE generation modules include NOT gate D1, trigger D2, NOT gate D3 and door D4；NOT gate D1 is received
The clock signal clkout of processor output, the clkoutn clock signals after output reversely, when trigger D2 receives clkoutn
Clock signal receives iosn signals as input signal, output iosn_reg1 is inputted to one of door D4 as clock signal
End；NOT gate D3 receives iosn signals, and output is connected to another input terminal with door D4；With door D4 output signals ALE to CAN
The address latch of bus control unit allows to hold ALE.
Preferably, direction generation modules include trigger D11, trigger D12, NOT gate D13, trigger D14 or
Door D15, NAND gate D16 and door D17, NOT gate D18 or door D19 or door D110, NAND gate D111；Trigger D11 receptions are handled
The clock signal clkout of device output as clock signal, the space reading enable signal oen of processor output as input signal,
Output terminal is connected to or an input terminal of door D15；Trigger D12 using the clock signal clkout as clock signal, with
For the direction signals of NOT gate D111 outputs as input signal, output terminal is connected to an input terminal of NAND gate D16；It is non-
Door D13 receive processor output input/output space chip selection signal iosn, output terminal be connected to an input terminal of door D17 and/or
An input terminal of door D110；Trigger D14 is using the clock signal clkout as clock signal, the input/output space piece choosing
Signal iosn is connected to another input terminal with another input terminal of door D17 and/or door D110 as input signal, output；
Or door D15 another input terminal receives the space and reads enable signal oen, output terminal be connected to NAND gate D16 another is defeated
Enter end；NAND gate D16 output terminals are connected to the input terminal of NOT gate D18；It is connected to door D17 output terminals or one of door D19 defeated
Enter end；NOT gate D18 output terminals are connected to or another input terminal of door D19；Or door D19 output terminals are connected to NAND gate D111's
One input terminal；Or door D110 output terminals are connected to another input terminal of NAND gate D111；NAND gate D111 outbound course controls
Signal direction processed.
Preferably, sel generation modules are to include trigger D21, NOT gate D22 and NAND gate D23；Trigger D21 receiving areas
The clock signal clkout of device output is managed as clock signal, the input/output space chip selection signal iosn of processor output is as input
Signal, an input terminal of output terminal connection NAND gate D23；NOT gate D22 receives the input/output space chip selection signal iosn, output
Another input terminal of end connection NAND gate D23；NAND gate D23 output selection signals sel.
Preferably, bidirectional buffering generation module includes buffer D31 and buffer D32；The Enable Pin of buffer D31 is double
To the Enable Pin OEN of buffering generation module, input terminal is the input terminal I of bidirectional buffering generation module, and output terminal is bidirectional buffering
The two-way PAD ends of generation module；Buffer D32 input terminals are connected with the output of buffer D31, and output terminal is generated for bidirectional buffering
The output terminal C of module.
There is provided what a kind of SoC interface circuit adaptively converted using the data address accessed CAN controller
Method, step are as follows：
(1) interface circuit generation address latch allows signal ALE, is connected to the address latch of CAN controller and allows
End；The input/output space chip select terminal of processor is connected to the CS# chip select terminal mouths of CAN controller；The reset terminal of processor is connected to
The reset terminal of CAN controller；The 15th middle broken ends of fractured bone for being connected to CAN controller of general purpose I/O port of processor；Place
Reason device write that enabled interface is connected to CAN controller write enabled interface；The reading of processor enables interface, and to be connected to CAN total
The reading of lane controller enables interface；
(2) the data address multiplexed signals of interface circuit generation processor, is input to the input of bidirectional buffering generation module
Hold I；Direction control signal direction is generated with after processor data double-direction control end signal progress logical AND, being input to double
To the Enable Pin OEN of buffering generation module；Two-way PAD ends are connected to the number of CAN controller by bidirectional buffering generation module
According to address multiplex signaling interface；When the OEN signals of bidirectional buffering generation module are low level, the data of processor output or address
Signal exports to the address date of CAN controller and is multiplexed end；CAN controller outputting data signals to processor number
According to input terminal.
Compared with the prior art, the invention has the advantages that：
(1) present invention by processor due to that using address, data selection and set direction, can send once-through operation
The access to CAN controller is completed in instruction, and sending operational order twice relative to previous processor could carry out once
Read/write access improves access efficiency, and strictly observes read and write access sequential, realizes from the address of processor independence, data
Channel is to the conversion of address date multiplex channel.
(2) present invention realizes address, data time-sharing multiplex using bidirectional buffering generation module, simplifies design, improves
Working efficiency.
(3) ALE generation modules of the invention obtain the signal of half of clock cycle, ingenious generation by using reversed clock
Address latch allows signal, and circuit logic is simple.
(4) interface circuit of the invention is applicable not only to SPARC V8 processors, additionally it is possible to suitable for other with external memory
The processor of controller.
Description of the drawings
Fig. 1 is the structure diagram of SoC interface circuit that data address of the present invention is adaptively converted；
Fig. 2 is the circuit diagram of ALE generation modules of the present invention；
Fig. 3 is the sequence diagram of ALE generation modules of the present invention；
Fig. 4 is the circuit diagram of direction generation modules of the present invention；
Fig. 5 a be direction generation modules of the present invention the first in the case of sequence diagram；Fig. 5 b are the present invention
Sequence diagram under the second situation of direction generation modules；
Fig. 6 is the circuit diagram of sel generation modules of the present invention；
Fig. 7 is the sequence diagram of sel generation modules of the present invention；
Fig. 8 is the circuit diagram of bidirectional buffering generation module of the present invention.
Specific embodiment
As shown in Figure 1, the SoC interface circuit adaptively converted of the data address that uses of the present invention by ALE generation modules,
Direction generation modules, sel generation modules and bidirectional buffering generation module composition.
ALE generation modules receive the clkout clock signals of SPARC V8 processors output, input/output space chip selection signal
Iosn, generation address latch allow signal ALE, continue half of clock week in the output of input/output space chip selection signal iosn falling edges
The address latch of the ale signal of phase to CAN controller allows to hold ALE, referring to Fig. 3.
Referring to Fig. 2, ALE generation modules include NOT gate D1, trigger D2, NOT gate D3 and door D4.NOT gate D1 receives clkout
Clock signal, after reversed, output clkoutn clock signals to trigger D2.Trigger D2 receives clkoutn clock signal conducts
Clock signal receives iosn signals as input signal, output iosn_reg1 a to input terminal with door D4.NOT gate D3 connects
Iosn signals are received, output is connected to another input terminal with door D4.With door D4 output signals ALE to CAN controller
Address latch allows to hold ALE.
Direction generation modules receive the clkout clock signals of SPARC V8 processors output, input/output space piece choosing letter
Number iosn and input/output space read enable signal oen, generate direction controlling direction signals.Direction controlling direction believes
It number is lower in iosn falling edges, direction signals are just drawn high when oen failing edges or iosn rising edges, two kinds of situations
Sequential respectively referring to Fig. 5 a, Fig. 5 b.
Referring to Fig. 4, direction generation modules include trigger D11, trigger D12, NOT gate D13, trigger D14 or
Door D15, NAND gate D16 and door D17, NOT gate D18 or door D19 or door D110, NAND gate D111；Trigger D11 receptions are handled
The clock signal clkout of device output as clock signal, the space reading enable signal oen of processor output as input signal,
Output terminal is connected to or an input terminal of door D15；Trigger D12 using the clock signal clkout as clock signal, with
For the direction signals of NOT gate D111 outputs as input signal, output terminal is connected to an input terminal of NAND gate D16；It is non-
Door D13 receive processor output input/output space chip selection signal iosn, output terminal be connected to an input terminal of door D17 and/or
An input terminal of door D110；Trigger D14 is using the clock signal clkout as clock signal, the input/output space piece choosing
Signal iosn is connected to another input terminal with another input terminal of door D17 and/or door D110 as input signal, output；
Or door D15 another input terminal receives the space and reads enable signal oen, output terminal be connected to NAND gate D16 another is defeated
Enter end；NAND gate D16 output terminals are connected to the input terminal of NOT gate D18；It is connected to door D17 output terminals or one of door D19 defeated
Enter end；NOT gate D18 output terminals are connected to or another input terminal of door D19；Or door D19 output terminals are connected to NAND gate D111's
One input terminal；Or door D110 output terminals are connected to another input terminal of NAND gate D111；NAND gate D111 outbound course controls
Signal direction processed.
Sel generation modules receive the clkout clock signals and input/output space chip selection signal of SPARC V8 processors output
Iosn, generation selection signal sel.Selection signal sel is generated in iosn failing edges and is continued the low level of clock cycle
Signal, other moment are high level signal, referring to Fig. 7.When sel for it is low when address strobe, sel for it is high when data strobe.
Referring to Fig. 6, sel generation modules are to include trigger D21, NOT gate D22 and NAND gate D23；Trigger D21 receiving areas
The clock signal clkout of device output is managed as clock signal, the input/output space chip selection signal iosn of processor output is as input
Signal, an input terminal of output terminal connection NAND gate D23；NOT gate D22 receives the input/output space chip selection signal iosn, output
Another input terminal of end connection NAND gate D23；NAND gate D23 output selection signals sel.
Bidirectional buffering generation module receives the most-significant byte data and least-significant byte address, CAN bus of SPARC V8 processors output
The data address multiplexed signals of controller, selection signal sel, the direction generation module of sel generation modules output export
The data double-way control end signal bdrive_oen_io of direction control signal direction, SPARC V8 processors；It will processing
After the chosen signal sel selections of the most-significant byte data of device and least-significant byte address, data address multiplexed signals addr_data [7 is formed:
0], into row address strobe when sel is low, sel carries out data strobe when being high, by data address multiplexed signals addr_data [7:
0] it is input to the input terminal I of bidirectional buffering generation module；Direction control signal direction and processor data double-direction control end
After signal bdrive_oen_io carries out logical AND, it is input to the Enable Pin OEN of bidirectional buffering generation module；CAN bus is controlled
The data address multiplex interface AD [7 of device:0] it is connected to the bidirectional end PAD of bidirectional buffering generation module；Bidirectional buffering generation module
Output terminal C be connected to the most-significant byte data input pin datain [31 of processor:24].
Referring to Fig. 8, bidirectional buffering generation module includes buffer D31 and buffer D32；The Enable Pin of buffer D31 is
The Enable Pin OEN of bidirectional buffering generation module, input terminal are the input terminal I of bidirectional buffering generation module, and output terminal is two-way slow
Rush the two-way PAD ends of generation module；Buffer D32 input terminals are connected with the output of buffer D31, and output terminal is given birth to for bidirectional buffering
Into the output terminal C of module.
The present invention realizes the access method of SoC interface circuit that data address is adaptively converted, and includes the following steps：
(1) interface circuit generation address latch allows signal ALE, is connected to the address latch of CAN controller and allows
Hold ALE；The input/output space chip selection signal iosn of SPARC V8 processors output is connected to the CS# ports of CAN controller；
The reset terminal rst of SPARC V8 processors output is connected to the reset terminal RESET# of CAN controller；SPARC V8 processors
The 15th pio [15] of general purpose I/O Interface be connected to the middle broken ends of fractured bone INT# of CAN controller；SPARC V8 processors are write
What enabled interface writen was connected to CAN controller writes enabled interface WR#；The reading of SPARC V8 processors enables interface
The reading that oen is connected to CAN controller enables interface RD#；
(2) generation data address multiplexed signals addr_data [7:0], it is input to the input terminal of bidirectional buffering generation module
I；Generate direction control signal direction and SPARC V8 processor datas double-direction control end signal bdrive_oen_io into
After row logical AND, it is input to the Enable Pin OEN of bidirectional buffering generation module；Bidirectional buffering generation module inputs input terminal I
The data address multiplexed signals that data address multiplexed signals addr_data is connected to CAN controller through two-way PAD ends connects
Mouth AD [7:0], the signal and controlled by OEN signals, when OEN signals are low level, data flow is by input terminal I to two-way PAD
End, SPARC V8 processors output dataout [31:24] and address [7:0] to CAN controller；Data flow is by two-way
It is not controlled when PAD ends are to input terminal I by OEN, the datain of CAN controller outputting data signals to SPARC V8 processors
[31:24]。
For the processor with outer memory controller, be generally capable of providing signal iosn, oen, writen, clkout,
Pio is applicable in the interface circuit of the present invention.
Sel generation modules are controlled by 10M~60MHz clocks clkout, and in iosn failing edges, generation continues a clock
Period low level signal sel.Address strobe when sel is low, data strobe when sel is high.
(3) clock signal clkout is sent into ALE generation modules.Ale signal is generated and is held in iosn signals falling edge
Continue half of clkout clock cycle.
(4) there are four ports for bidirectional buffering generation module：I, enabled OEN, two-way PAD, output C are inputted, is corresponded to respectively
dataout[31:24] and adress [7:0] the data address signal addr_data [7 after sel is selected:0]、
Logical AND, the can_ad [7 of direction and processor data double-direction control end signal bdrive_oen_io:0]、datain
[31:24].The channel realized from SPARC V8 processor addresses, Dynamic data exchange is answered to 8 CAN controller address dates
It is adaptively converted with the data address of channel.
The above, best specific embodiment only of the invention, but protection scope of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (6)
1. the SoC interface circuit that a kind of data address is adaptively converted realizes access of the processor to CAN controller,
It is characterized in that, including ALE generation modules, direction generation modules, sel generation modules and bidirectional buffering generation module；
The ALE generation modules receive the clock signal of processor output, input/output space chip selection signal, and generation address latch allows
The address latch of signal ALE to CAN controller allows to hold, and address latch allows signal to decline in input/output space chip selection signal
Output continues the high level signal of half of clock cycle at；
Direction generation modules receive the clock signal of processor output, and input/output space chip selection signal and input/output space reading make
Energy signal, generates direction control signal direction, and direction control signal becomes low in input/output space chip selection signal falling edge
Level is read to become high level when the arrival of enable signal failing edge or the arrival of input/output space chip selection signal rising edge in space；
Sel generation modules receive the clock signal and input/output space chip selection signal of processor output, generate selection signal sel, selection
Signal sel generates the low level signal for continuing a clock cycle, other moment in input/output space chip selection signal failing edge
For high level signal；
The most-significant byte data of bidirectional buffering generation module reception processor output, least-significant byte address, processor data double-direction control end
Signal, selection signal sel and direction control signal direction；By processor most-significant byte data, the chosen sel in least-significant byte address
The data address multiplexed signals formed after signal behavior is input to the input terminal I of bidirectional buffering generation module；Direction control signal
After direction carries out logical AND with processor data double-direction control end signal, it is input to the enabled of bidirectional buffering generation module
Hold OEN；The data address multiplexed signals interface of CAN controller is connected to the bidirectional end PAD of bidirectional buffering generation module；It is double
To the most-significant byte data input pin of the output terminal C connection processing devices of buffering generation module.
2. the SoC interface circuit that data address as described in claim 1 is adaptively converted, which is characterized in that the ALE lifes
Include NOT gate D1, trigger D2, NOT gate D3 and door D4 into module；NOT gate D1 receives the clock signal clkout of processor output,
Clkoutn clock signals after output reversely, trigger D2 receive clkoutn clock signals as clock signal, receive iosn
Signal is as input signal, output iosn_reg1 a to input terminal with door D4；NOT gate D3 receives iosn signals, and output connects
It is connected to another input terminal with door D4；Allow to hold ALE with the address latch of door D4 output signals ALE to CAN controller.
3. the SoC interface circuit that data address as claimed in claim 1 or 2 is adaptively converted, which is characterized in that
Direction generation modules include trigger D11, trigger D12, NOT gate D13, trigger D14 or door D15, NAND gate D16,
With door D17, NOT gate D18 or door D19 or door D110, NAND gate D111；Trigger D11 receives the clock signal of processor output
Clkout reads enable signal oen as input signal as clock signal, the space of processor output, and output terminal is connected to or door
An input terminal of D15；Trigger D12 using the clock signal clkout as clock signal, NAND gate D111 output
For direction signals as input signal, output terminal is connected to an input terminal of NAND gate D16；NOT gate D13 receives processor
The input/output space chip selection signal iosn of output, output terminal are connected to an input with an input terminal of door D17 and/or door D110
End；Trigger D14 is using the clock signal clkout as clock signal, and the input/output space chip selection signal iosn is as input
Signal, output are connected to another input terminal with another input terminal of door D17 and/or door D110；Or another is defeated by door D15
Enter end and receive the space reading enable signal oen, output terminal is connected to another input terminal of NAND gate D16；NAND gate D16 is defeated
Outlet is connected to the input terminal of NOT gate D18；It is connected to door D17 output terminals or an input terminal of door D19；NOT gate D18 is exported
End is connected to or another input terminal of door D19；Or door D19 output terminals are connected to an input terminal of NAND gate D111；Or door
D110 output terminals are connected to another input terminal of NAND gate D111；NAND gate D111 outbound courses control signal direction.
4. the SoC interface circuit that data address as claimed in claim 1 or 2 is adaptively converted, which is characterized in that sel is generated
Module is to include trigger D21, NOT gate D22 and NAND gate D23；Trigger D21 receives the clock signal of processor output
Clkout as clock signal, the input/output space chip selection signal iosn of processor output as input signal, output terminal connect with it is non-
An input terminal of door D23；NOT gate D22 receives the input/output space chip selection signal iosn, and output terminal connection NAND gate D23's is another
One input terminal；NAND gate D23 output selection signals sel.
5. the SoC interface circuit that data address as claimed in claim 1 or 2 is adaptively converted, which is characterized in that bidirectional buffering
Generation module includes buffer D31 and buffer D32；The Enable Pin of buffer D31 is the Enable Pin of bidirectional buffering generation module
OEN, input terminal are the input terminal I of bidirectional buffering generation module, and output terminal is the two-way PAD ends of bidirectional buffering generation module；It is slow
The output that device D32 input terminals are rushed with buffer D31 is connected, and output terminal is the output terminal C of bidirectional buffering generation module.
6. a kind of SoC interface circuit adaptively converted using data address described in claims 1 or 22 is to CAN controller
The method of access, it is characterised in that step is as follows：
(1) interface circuit generation address latch allows signal ALE, and being connected to the address latch of CAN controller allows to hold；Place
The input/output space chip select terminal of reason device is connected to the CS# chip select terminal mouths of CAN controller；It is total that the reset terminal of processor is connected to CAN
The reset terminal of lane controller；The 15th middle broken ends of fractured bone for being connected to CAN controller of general purpose I/O port of processor；Processor
Write that enabled interface is connected to CAN controller write enabled interface；The reading of processor enables interface and is connected to CAN bus control
The reading of device processed enables interface；
(2) the data address multiplexed signals of interface circuit generation processor is input to the input terminal I of bidirectional buffering generation module；
Direction control signal direction is generated with after processor data double-direction control end signal progress logical AND, being input to two-way slow
Rush the Enable Pin OEN of generation module；Two-way PAD ends with being connected to the data of CAN controller by bidirectional buffering generation module
Location multiplexed signals interface；When the OEN signals of bidirectional buffering generation module are low level, the data or address signal of processor output
It exports to the address date of CAN controller and is multiplexed end；The data of CAN controller outputting data signals to processor are defeated
Enter end.
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| CN201711232993.5A CN108182164B (en) | 2017-11-30 | 2017-11-30 | SoC interface circuit for data address self-adaptive conversion and access method |
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| US5185736A (en) * | 1989-05-12 | 1993-02-09 | Alcatel Na Network Systems Corp. | Synchronous optical transmission system |
| CN1402140A (en) * | 2002-04-19 | 2003-03-12 | 深圳市盈宁科技有限公司 | Device for switching from non-software drive memory interface to software drive interface |
| CN104461620A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Autonomous reconstruction soft configuration method for SoPC chip |
| CN205564744U (en) * | 2015-12-25 | 2016-09-07 | 北京时代民芯科技有限公司 | ARINC659 bus control circuit with two tunnel low chronogenesis deviation BIU |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5185736A (en) * | 1989-05-12 | 1993-02-09 | Alcatel Na Network Systems Corp. | Synchronous optical transmission system |
| CN1402140A (en) * | 2002-04-19 | 2003-03-12 | 深圳市盈宁科技有限公司 | Device for switching from non-software drive memory interface to software drive interface |
| CN104461620A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Autonomous reconstruction soft configuration method for SoPC chip |
| CN205564744U (en) * | 2015-12-25 | 2016-09-07 | 北京时代民芯科技有限公司 | ARINC659 bus control circuit with two tunnel low chronogenesis deviation BIU |
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