CN108172166A - The driving method of source electrode driver and display panel - Google Patents
The driving method of source electrode driver and display panel Download PDFInfo
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- CN108172166A CN108172166A CN201810020726.XA CN201810020726A CN108172166A CN 108172166 A CN108172166 A CN 108172166A CN 201810020726 A CN201810020726 A CN 201810020726A CN 108172166 A CN108172166 A CN 108172166A
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- transistor
- output pin
- source electrode
- output
- electrode driver
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The present invention provides a kind of source electrode driver and the driving method of display panel, the source electrode driver includes digital analog converter, buffer amplifier, control module and output pin；The control module includes and the same number of transistor of the output pin；Wherein, each output pin is connected by a transistor with the buffer amplifier, each described m adjacent described output pin of buffer amplifier connection, m is the integer more than or equal to 2.The present invention provides a kind of source electrode driver and the driving methods of display panel, by the way that a buffer amplifier is set to drive multiple output pins, buffer amplifier is replaced using lower-cost transistor and simple control circuit, it can be in the case where source electrode driver completion function be constant, the quantity of buffer amplifier is reduced, and then reduces the production cost of source electrode driver.
Description
Technical field
The present invention relates to display technology fields, and in particular to the driving method of source electrode driver and display panel.
Background technology
Current panel market tends to saturation, and the market price constantly reduces, and in order to seek profit, improving innovation reduces cost gesture
It must go.The source electrode driver of display panel occupies higher ratio on a display panel, thus reduce source electrode driver into
This is imperative, and traditional improved method is all the driving technique for changing source electrode driver, although effect is relatively good, improves
The cost and period spent is all long.
As shown in Figure 1, source electrode driver 1, digital analog converter 11, buffer amplifier 12 and output pin 13, existing
In source electrode driver 1, can all there be independent buffer amplifier 12 to be connected with output pin 13, to enhance the driving of output pin 13
Ability, but after the resolution increase of display panel, 13 number of driving pin of every source electrode driver 1 can increase, accordingly
The quantity of buffer amplifier 12 can also increase, and then cause the cost of source electrode driver 1 that can also increase, therefore there is an urgent need for one kind to exist
Under the premise of 1 prior art of source electrode driver is constant, the method for reduction source drive cost.
Invention content
The present invention provides a kind of source electrode driver and the driving method of display panel, to solve in existing source electrode driver
Buffer amplifier demand is excessive and then the problem of causing source electrode driver production cost higher.
To achieve the above object, technical solution provided by the invention is as follows：
According to an aspect of the invention, there is provided a kind of source electrode driver, the source electrode driver includes digital-to-analogue conversion
Device, buffer amplifier, control module and output pin；
Digital analog converter, the digital analog converter are used to convert a digital signal as an analog signal；
Buffer amplifier, each buffer amplifier are coupled to the digital analog converter, for amplifying the simulation letter
Number, to generate output signal；
Control module, including with the same number of transistor of the output pin, the control module connects the buffering
Amplifier and the output pin, for after the clock signal of sequence controller is received, by controlling the transistor
It opens and closes, and then controls the transmission of the output signal；
Output pin is connected to the control module, to export the output signal；
Wherein, each output pin is connected by a transistor with the buffer amplifier, each institute
M adjacent output pins of buffer amplifier connection are stated, m is the integer more than or equal to 2.
According to one preferred embodiment of the present invention, m is equal to 3, and using 3 output pins as one group, output described in every group is drawn
Foot includes red sub-pixel output pin, green sub-pixels output pin and blue subpixels output pin.
According to one preferred embodiment of the present invention, the grid of the corresponding transistor of the red sub-pixel output pin connects
It is connected together, the corresponding transistor of the red sub-pixel output pin forms the first transistor group, the sub- picture of green
The grid of the corresponding transistor of plain output pin links together, the corresponding crystalline substance of the green sub-pixels output pin
Body pipe forms second transistor group, and the grid of the corresponding transistor of the blue subpixels output pin links together,
The corresponding transistor of the blue subpixels output pin forms third transistor group.
According to one preferred embodiment of the present invention, the clock signal includes the first clock signal, the second clock signal and the
Three clock signals；
Wherein, first clock signal controls the first transistor group, the second clock signal control described the
Two-transistor group, the third clock signal controls third transistor group, when the source electrode driver is receiving the sequential
During signal, the first transistor group, the second transistor group and the third transistor group are sequentially opened.
According to one preferred embodiment of the present invention, when the first transistor group is opened, the second transistor group and
Three transistor groups are closed；When the second transistor group is opened, the first transistor group and the third are brilliant
Body pipe group is closed；When the third transistor group is opened, the first transistor group and the second transistor
Group is closed.
According to one preferred embodiment of the present invention, the grid of the transistor is connected with the sequence controller, the crystal
The source electrode of pipe is connected with the output terminal of the buffer amplifier, and the drain electrode of the transistor is connected with the output pin.
According to another aspect of the present invention, a kind of driving method of display panel is provided, the display panel includes
Source electrode driver and sequence controller, the source electrode driver include digital analog converter, buffer amplifier, control module and defeated
Go out pin, the driving method of the display panel includes the following steps：
S10, the source electrode driver receive a digital signal；
The digital signal that the source electrode driver receives is converted to simulation letter by S20, the digital analog converter
Number, it exports to the buffer amplifier；
S30, the buffer amplifier amplify the analog signal, generate output signal；
S40, the source electrode driver are after the clock signal that the sequence controller is sent out is received, the control module
Transistor sequentially open, the output signal, by the output pin, completes the output after the control of control module
The output of signal, the control module include and the same number of transistor of the output pin；
Wherein, each output pin is connected by a transistor with the buffer amplifier, each institute
M adjacent output pins of buffer amplifier connection are stated, m is the integer more than or equal to 2.
According to one preferred embodiment of the present invention, m is equal to 3, and using 3 output pins as one group, output described in every group is drawn
Foot includes red sub-pixel output pin, green sub-pixels output pin and blue subpixels output pin.
According to one preferred embodiment of the present invention, the grid of the corresponding transistor of the red sub-pixel output pin connects
It is connected together, the corresponding transistor of the red sub-pixel output pin forms the first transistor group, the sub- picture of green
The grid of the corresponding transistor of plain output pin links together, the corresponding crystalline substance of the green sub-pixels output pin
Body pipe forms second transistor group, and the grid of the corresponding transistor of the blue subpixels output pin links together,
The corresponding transistor of the blue subpixels output pin forms third transistor group.
According to one preferred embodiment of the present invention, the clock signal includes the first clock signal, the second clock signal and the
Three clock signals；
Wherein, first clock signal controls the first transistor group, the second clock signal control described the
Two-transistor group, the third clock signal control third transistor group；
The S40's includes：
S41, the source electrode driver receive first clock signal, open the first transistor group, described slow
It rushes amplifier and the output signal is passed into the red sub-pixel output pin；
S42, the source electrode driver receive second clock signal, close the first transistor group, open institute
Second transistor group is stated, the output signal is passed to the green sub-pixels output pin by the buffer amplifier；
S43, the source electrode driver receive the third clock signal, close the second transistor group, open institute
Third transistor group is stated, the output signal is passed to the blue subpixels output pin by the buffer amplifier, is closed
Third transistor group completes the output of output signal described in a line, goes to the output of output signal described in next line；
S44, sequentially repeating said steps S41, the step S42 and the step S43, until completing all outputs
The output of signal.
According to one preferred embodiment of the present invention, the grid of the transistor is connected with the sequence controller, the crystal
The source electrode of pipe is connected with the output terminal of the buffer amplifier, and the drain electrode of the transistor is connected with the output pin.
It is an advantage of the current invention that providing the driving method of a kind of source electrode driver and display panel, pass through setting one
A buffer amplifier drives multiple output pins, is put using lower-cost transistor and simple control circuit instead of buffering
Big device can reduce the quantity of buffer amplifier, and then reduce source electrode in the case where the function of source electrode driver completion is constant
The production cost of driver.
Description of the drawings
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution of the prior art
Attached drawing is briefly described needed in description, it should be apparent that, the accompanying drawings in the following description is only some invented
Embodiment, for those of ordinary skill in the art, without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the part-structure schematic diagram of existing source electrode driver；
Fig. 2 is the part-structure schematic diagram of source electrode driver in the present invention；
Fig. 3 is the subdivision graph of the output pin 23 in Fig. 2；
Fig. 4 is the subdivision graph of clock signal 31 in the present invention；
Fig. 5 is the flow chart of displaying panel driving method in the present invention.
Specific embodiment
The explanation of following embodiment is with reference to additional diagram, to illustrate the particular implementation that the present invention can be used to implementation
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be illustrate and understand the present invention rather than to
The limitation present invention.The similar unit of structure is with being given the same reference numerals in the figure.
The present invention is described further in the following with reference to the drawings and specific embodiments：
Fig. 2 is the part-structure schematic diagram of source electrode driver in the present invention in the present invention, and Fig. 3 is the output pin in Fig. 2
23 subdivision graph, Fig. 4 are the flow chart of displaying panel driving method in the present invention.
As shown in Figures 2 and 3, the present invention provides a kind of source electrode driver 2, the source electrode driver 2 turns including digital-to-analogue
Parallel operation 21, buffer amplifier 22, control module 24 and output pin 23；
Digital analog converter 21, the digital analog converter 21 are used to convert digital signals into analog signal；
Buffer amplifier 22, each buffer amplifier 22 are coupled to the digital analog converter 21, described for amplifying
Analog signal, to generate output signal (not shown)；
Control module 24, including transistor 24a, the number of the transistor 24a is identical with 23 number of output pin,
I.e. a pin 23 corresponds to a transistor 24a.The control module 24 connects the buffer amplifier 22 and the output is drawn
Foot 23, after the clock signal 31 of sequence controller 3 is received, by controlling the opening and closing of the transistor 24a, and then
Control the transmission of the output signal (not shown)；
Output pin 23 is connected to the control module 24, to export the output signal；
Wherein, each output pin 23 is connected by a transistor 24a with the buffer amplifier 22, often
One buffer amplifier 22 connects the m adjacent output pins 23, and m is the integer more than or equal to 2.
In an embodiment of the present invention, m is equal to 3, with 3 output pins 23 for one group, output pin described in every group
Including red sub-pixel output pin 23a, green sub-pixels output pin 23b and blue subpixels output pin 23c.
What deserves to be explained is in the present invention, the value of the m not only can only value be 3, or 4,5,6 etc.
Integer more than 2, but since in display panel, a pixel is to include a red sub-pixel, a sub- picture of green
Element and a blue subpixels, it is more convenient in the data processing and sequential operation to display panel when m values are 3, therefore
It is specifically described by taking m=3 as an example in embodiment in the present invention.
Wherein, the grid of the corresponding transistor 24a of the red sub-pixel output pin 23a links together, institute
It states the corresponding transistor 24a of red sub-pixel output pin 23a and forms the first transistor group 241, the green sub-pixels
The grid of the corresponding transistor 24a of output pin 23b links together, and the green sub-pixels output pin 23b is corresponded to
The transistor form second transistor group 242, the corresponding transistor 24a of the blue subpixels output pin 23c
Grid link together, the corresponding transistor 24a of the blue subpixels output pin 23c forms third transistor group
243。
It is clearly limited it should be noted that not done to the distributing order of the output pin in the present invention.
According to one preferred embodiment of the present invention, the clock signal 31 includes the first clock signal 311, the second clock signal
312 and third clock signal 313；
Wherein, first clock signal 311 controls the first transistor group 241, and second clock signal 312 is controlled
The second transistor group 242 is made, the third clock signal 313 controls third transistor group 243, when the source electrode driver
2 when receiving the clock signal 31, sequentially opens the first transistor group 241, the second transistor group 242 and institute
State third transistor group 243.
The purpose done so is, distinguishes the transistor for controlling different colours pixel by using the mode of transistor group
It opens, and then completes the differentiation output of different pixels output signal, and then improve the data-handling efficiency of source electrode driver 2.
Further, when the first transistor group 241 is opened, the second transistor group 242 and third transistor
Group 243 is closed；When the second transistor group 242 is opened, the first transistor group 241 and the third are brilliant
Body pipe group 243 is closed；When the third transistor group 243 is opened, the first transistor group 241 and described
Two-transistor group 242 is closed, and can thus be charged to all pixels in a line.
Preferably, the grid of the transistor 24a is connected with the sequence controller 3, the source electrode of the transistor 24a with
The output terminal of the buffer amplifier 22 is connected, and the drain electrode of the transistor 24a is connected with the output pin 23.
According to another aspect of the present invention, as shown in figure 4, the invention also provides a kind of driving sides of display panel
Method, the display panel include source electrode driver and sequence controller, and the driving method of the display panel includes the following steps：
S10, the source electrode driver receive a digital signal；
The digital signal that the source electrode driver receives is converted to simulation letter by S20, the digital analog converter
Number, it exports to the buffer amplifier；
S30, the buffer amplifier amplify the analog signal, generate output signal；
S40, the source electrode driver are after the clock signal that the sequence controller is sent out is received, the control module
Transistor sequentially open, the output signal, by the output pin, completes the output after the control of control module
The output of signal, the control module include and the same number of transistor of the output pin；
Wherein, each output pin is connected by a transistor with the buffer amplifier, each institute
M adjacent output pins of buffer amplifier connection are stated, m is the integer more than or equal to 2.
Preferably, m is equal to 3, and using 3 output pins as one group, output pin described in every group includes red sub-pixel
Output pin, green sub-pixels output pin and blue subpixels output pin；
The grid of the corresponding transistor of the red sub-pixel output pin links together, the red sub-pixel
The corresponding transistor of output pin forms the first transistor group, the corresponding crystal of the green sub-pixels output pin
The grid of pipe links together, and the corresponding transistor of the green sub-pixels output pin forms second transistor group, institute
The grid for stating the corresponding transistor of blue subpixels output pin links together, the blue subpixels output pin pair
The transistor answered forms third transistor group.
It is to be understood that the clock signal includes the first clock signal, the second clock signal and third clock signal；
Wherein, first clock signal controls the first transistor group, the second clock signal control described the
Two-transistor group, the third clock signal control third transistor group；
The S40's includes：
S41, the source electrode driver receive first clock signal, open the first transistor group, described slow
It rushes amplifier and the output signal is passed into the red sub-pixel output pin；
S42, the source electrode driver receive second clock signal, close the first transistor group, open institute
Second transistor group is stated, the output signal is passed to the green sub-pixels output pin by the buffer amplifier；
S43, the source electrode driver receive the third clock signal, close the second transistor group, open institute
Third transistor group is stated, the output signal is passed to the blue subpixels output pin by the buffer amplifier, is closed
Third transistor group completes the output of output signal described in a line, goes to the output of output signal described in next line；
S44, sequentially repeating said steps S41, the step S42 and the step S43, until completing all outputs
The output of signal.
Preferably, the grid of the transistor is connected with the sequence controller, and the source electrode of the transistor delays with described
The output terminal for rushing amplifier is connected, and the drain electrode of the transistor is connected with the output pin.
The operation principle of the driving method of display panel is consistent with the operation principle of above-mentioned source electrode driver in the present embodiment,
The operation principle of the source electrode driver of above preferred embodiment is specifically referred to, is no longer repeated herein.
The present invention provides a kind of source electrode driver and the driving method of display panel, by setting a buffer amplifier
Multiple output pins are driven, buffer amplifier, Neng Gou are replaced using lower-cost transistor and simple control circuit
In the case that source electrode driver completion function is constant, the quantity of buffer amplifier is reduced, and then reduce the production of source electrode driver
Cost.
In conclusion although the present invention is disclosed above with preferred embodiment, above preferred embodiment is not to limit
The system present invention, those of ordinary skill in the art without departing from the spirit and scope of the present invention, can make various changes and profit
Decorations, therefore protection scope of the present invention is subject to the range that claim defines.
Claims (10)
1. a kind of source electrode driver, which is characterized in that the source electrode driver includes digital analog converter, buffer amplifier, control
Module and output pin；
Digital analog converter, the digital analog converter are used to convert a digital signal as an analog signal；
Buffer amplifier, each buffer amplifier is coupled to the digital analog converter, for amplifying the analog signal, with
Generate output signal；
Control module, including with the same number of transistor of the output pin, the control module connects the Hyblid Buffer Amplifier
Device and the output pin, for after the clock signal of sequence controller is received, by the unlatching for controlling the transistor
And closing, and then control the transmission of the output signal；
Output pin is connected to the control module, to export the output signal；
Wherein, each output pin is connected by a transistor with the buffer amplifier, each is described slow
M adjacent output pins of amplifier connection are rushed, m is the integer more than or equal to 2.
2. source electrode driver according to claim 1, which is characterized in that m is equal to 3, using 3 output pins as one
Group, output pin described in every group include red sub-pixel output pin, green sub-pixels output pin and blue subpixels output
Pin.
3. source electrode driver according to claim 2, which is characterized in that the corresponding institute of the red sub-pixel output pin
The grid for stating transistor links together, and the corresponding transistor of the red sub-pixel output pin forms the first transistor
Group, the grid of the corresponding transistor of the green sub-pixels output pin link together, the green sub-pixels output
The corresponding transistor of pin forms second transistor group, the corresponding transistor of the blue subpixels output pin
Grid links together, and the corresponding transistor of the blue subpixels output pin forms third transistor group.
4. source electrode driver according to claim 3, which is characterized in that the clock signal include the first clock signal,
Second clock signal and third clock signal；
Wherein, first clock signal controls the first transistor group, and the second clock signal control described second is brilliant
Body pipe group, the third clock signal controls third transistor group, when the source electrode driver is receiving the clock signal
When, sequentially open the first transistor group, the second transistor group and the third transistor group.
5. source electrode driver according to claim 4, which is characterized in that described when the first transistor group is opened
Second transistor group and third transistor group are closed；When the second transistor group is opened, the first crystal
Third transistor group is closed described in Guan Zuhe；When the third transistor group is opened, the first transistor group
It is closed with the second transistor group.
6. source electrode driver according to claim 1, which is characterized in that the grid of the transistor and the timing control
Device is connected, and the source electrode of the transistor is connected with the output terminal of the buffer amplifier, the drain electrode of the transistor with it is described defeated
Go out pin to be connected.
7. a kind of driving method of display panel, which is characterized in that the display panel includes source electrode driver and timing control
Device, the source electrode driver include digital analog converter, buffer amplifier, control module and output pin, the display panel
Driving method include the following steps：
S10, the source electrode driver receive a digital signal；
The digital signal that the source electrode driver receives is converted to an analog signal by S20, the digital analog converter, defeated
Go out to the buffer amplifier；
S30, the buffer amplifier amplify the analog signal, generate output signal；
S40, the source electrode driver are after the clock signal that the sequence controller is sent out is received, the crystalline substance of the control module
Body pipe is sequentially opened, and the output signal, by the output pin, completes the output signal after the control of control module
Output, the control module include and the same number of transistor of the output pin；
Wherein, each output pin is connected by a transistor with the buffer amplifier, each is described slow
M adjacent output pins of amplifier connection are rushed, m is the integer more than or equal to 2.
8. the driving method of source electrode driver according to claim 6, which is characterized in that m is equal to 3, is drawn with 3 outputs
Foot is one group, and output pin described in every group includes red sub-pixel output pin, green sub-pixels output pin and the sub- picture of blue
Plain output pin；
The grid of the corresponding transistor of the red sub-pixel output pin links together, the red sub-pixel output
The corresponding transistor of pin forms the first transistor group, the corresponding transistor of the green sub-pixels output pin
Grid links together, and the corresponding transistor of the green sub-pixels output pin forms second transistor group, the indigo plant
The grid of the corresponding transistor of sub-pixels output pin links together, and the blue subpixels output pin is corresponding
The transistor forms third transistor group.
9. the driving method of source electrode driver according to claim 8, which is characterized in that when the clock signal includes first
Sequential signal, the second clock signal and third clock signal；
Wherein, first clock signal controls the first transistor group, and the second clock signal control described second is brilliant
Body pipe group, the third clock signal control third transistor group；
The S40's includes：
S41, the source electrode driver receive first clock signal, open the first transistor group, and the buffering is put
The output signal is passed to the red sub-pixel output pin by big device；
S42, the source electrode driver receive second clock signal, close the first transistor group, open described the
The output signal is passed to the green sub-pixels output pin by two-transistor group, the buffer amplifier；
S43, the source electrode driver receive the third clock signal, close the second transistor group, open described the
The output signal is passed to the blue subpixels output pin by three transistor groups, the buffer amplifier, closes third
Transistor group completes the output of output signal described in a line, goes to the output of output signal described in next line；
S44, sequentially repeating said steps S41, the step S42 and the step S43, until completing all output signals
Output.
10. the driving method of source electrode driver according to claim 1, which is characterized in that the grid of the transistor and institute
It states sequence controller to be connected, the source electrode of the transistor is connected with the output terminal of the buffer amplifier, the leakage of the transistor
Pole is connected with the output pin.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810020726.XA CN108172166A (en) | 2018-01-10 | 2018-01-10 | The driving method of source electrode driver and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810020726.XA CN108172166A (en) | 2018-01-10 | 2018-01-10 | The driving method of source electrode driver and display panel |
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| CN105807518A (en) * | 2016-05-19 | 2016-07-27 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
| CN106292096A (en) * | 2016-10-13 | 2017-01-04 | 武汉华星光电技术有限公司 | A kind of De mux liquid crystal display and driving method thereof |
| CN106898285A (en) * | 2015-12-18 | 2017-06-27 | 硅工厂股份有限公司 | Output buffer and the source electrode drive circuit including output buffer |
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- 2018-01-10 CN CN201810020726.XA patent/CN108172166A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510398A (en) * | 2008-02-15 | 2009-08-19 | 中华映管股份有限公司 | Source electrode drive circuit |
| CN104867474A (en) * | 2015-06-19 | 2015-08-26 | 合肥鑫晟光电科技有限公司 | Source driver applied to TFT-LCD, drive circuit and drive method |
| CN105047157A (en) * | 2015-08-19 | 2015-11-11 | 深圳市华星光电技术有限公司 | Source drive circuit |
| CN106898285A (en) * | 2015-12-18 | 2017-06-27 | 硅工厂股份有限公司 | Output buffer and the source electrode drive circuit including output buffer |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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Application publication date: 20180615 |
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