CN108154903B - Write control method, read control method and device of flash memory - Google Patents
Write control method, read control method and device of flash memory Download PDFInfo
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- CN108154903B CN108154903B CN201711406433.7A CN201711406433A CN108154903B CN 108154903 B CN108154903 B CN 108154903B CN 201711406433 A CN201711406433 A CN 201711406433A CN 108154903 B CN108154903 B CN 108154903B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
Abstract
A write control method and apparatus, a read control method and apparatus, and a memory system for a flash memory are disclosed. The write control method of the flash memory comprises the following steps: segmenting original data according to a first mode to obtain a plurality of first data; segmenting original data according to a second mode to obtain a plurality of second materials, wherein any one of the first materials and one of the second materials have a common part; encoding the first data to obtain a plurality of first code element data; encoding the second data to obtain second code metadata; and storing the original data, the plurality of first symbol data, and the plurality of second symbol data to respective storage locations of the flash memory. By storing the coded data of two dimensions, the decoding and error correction capability of the ECC circuit is improved, and the reliability and the product yield of the flash memory are further improved.
Description
Technical Field
The invention relates to a write control method, a read control method and a device of a flash memory, and a memory system.
Background
Flash memory (flash) is a non-volatile memory, and is widely used in electronic devices such as memory cards, solid state disks, and portable multimedia players (portable multimedia players). Flash memory can be divided into N0R type flash memory and NAND type flash memory.
In order to ensure data security, an ecc (error Checking and correction) circuit is generally provided in a controller of the flash memory, and is used for data recovery and error correction processing. The ECC circuit is arranged at the control end of the flash memory, and in the data writing stage, the code data generated based on the original data coding is stored in the flash memory, and in the data reading stage, the code data is decoded to obtain the original data. The ECC coding and decoding circuit can reduce the error rate of the flash memory and improve the yield of products.
However, with the development of the flash memory process technology, especially the rising of the 3D NAND flash memory, the difference between the yield and the Bit Error Rate (BER) of the 3D NAND flash memory is much higher than that of the conventional 2D (planr) NAND flash memory, especially when the power is abnormally turned off, the Bit Error Rate of 1 to 2 pages (pages) often occurs in the memory block (block) of the 3D NAND flash memory, which is much higher than the Bit Error Rate of the whole flash memory, and cannot be corrected by the ECC circuit.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and a device for controlling writing and reading of a flash memory, which perform encoding and decoding in two dimensions, so as to further reduce the error rate of the flash memory, and improve the reliability and the yield of the flash memory.
According to a first aspect of the present invention, there is provided a write control method of a flash memory, comprising:
segmenting original data according to a first mode to obtain a plurality of first data;
segmenting original data according to a second mode to obtain a plurality of second materials, wherein any one of the first materials and one of the second materials have a common part;
encoding the first data to obtain a plurality of first code element data;
encoding the second data to obtain second code metadata; and
storing the original data, the plurality of first symbol data, and the plurality of second symbol data to respective storage locations of the flash memory.
Preferably, the first method segments the original data according to a semantic direction of the original data to obtain a plurality of first materials, the second method segments each of the plurality of first materials to obtain a plurality of segments, and the plurality of segments form the plurality of second materials, and the plurality of segments forming each of the second materials are at least from two first materials.
Preferably, each first datum is stored in one memory page and each second datum is stored in a plurality of memory pages.
Preferably, the first data and the first symbol data are stored in the same memory block, and the second symbol data are stored in a memory page following the corresponding memory block.
Preferably, a first encoding method is adopted to encode the plurality of first materials; and encoding the plurality of second data by using a second encoding method.
Preferably, the first encoding method is an LDPC encoding method, and the second encoding method is an RS encoding method.
According to a second aspect of the present invention, there is provided a read control method for a flash memory, for reading data written in the flash memory by the write control method, comprising:
reading encoded data from respective locations of the flash memory, the encoded data including original data, first symbol data, and second symbol data; and
iteratively decoding and correcting the original data according to the first symbol data and the second symbol data.
Preferably, the iteratively decoding and error correcting the original data according to the first symbol data and the second symbol data includes:
decoding and error correcting the first symbol data using the first encoding method;
decoding and correcting the second code element data by adopting a second coding method according to the decoding result of the first code element data; and
and decoding and correcting the first code element data by adopting the first coding method according to the decoding result of the second code element data.
Preferably, the method further comprises the following steps: and stopping decoding when all the code words adopting the first coding method and all the code words adopting the second coding method fail to decode.
According to a third aspect of the present invention, there is provided a write control apparatus for a flash memory, comprising:
the segmentation module is used for segmenting the original data according to a first mode to obtain a plurality of first data; segmenting original data according to a second mode to obtain a plurality of second data, wherein any one of the first data and one of the second data have a common part;
a first encoding module, configured to encode the first data to obtain a plurality of first symbol data;
the second coding module is used for coding the second data to obtain second code metadata; and
a storage control module for storing the original data, the plurality of first symbol data and the plurality of second symbol data to corresponding storage locations of the flash memory.
Preferably, the segmentation module segments the original data according to a semantic direction of the original data to obtain a plurality of first materials, segments each of the plurality of first materials to obtain a plurality of segments, groups the plurality of segments into the plurality of second materials, and groups the plurality of segments forming each of the second materials from at least two of the first materials.
Preferably, the storage control module controls each first material to be stored in one storage page, and each second material to be stored in a plurality of storage pages.
Preferably, the storage control module controls the first material, the first material and the first symbol data to be stored in the same storage block and the second symbol data to be stored in a storage page subsequent to the corresponding storage block.
Preferably, the first encoding module encodes the plurality of first materials by using a first encoding method; the second coding module codes the plurality of second data by adopting a second coding method.
Preferably, the first encoding method is an LDPC encoding method, and the second encoding method is an RS encoding method.
Preferably, the write control device for reading the data written into the flash memory according to any one of claims 10 to 15, includes:
a reading module, configured to read encoded data from a corresponding location of the flash memory, where the encoded data includes original data, first symbol data, and second symbol data;
a first decoding module for decoding and correcting errors according to the first symbol data;
the second decoding module is used for decoding and correcting errors according to the second code metadata;
and the iteration control module is used for controlling the first decoding module and the second decoding module to carry out iterative decoding and error correction.
Preferably, the method further comprises the following steps: and the iteration control module stops decoding after judging that all the code words adopting the first coding method and all the code words adopting the second coding method fail.
According to a fourth aspect of the present invention, there is provided a memory system comprising a flash memory and a memory controller, the controller including the above-described write control device and the above-described read control device.
The writing control method provided by the invention is used for encoding the original data in two dimensions to obtain and store the first code element data and the second code element data, and simultaneously, the reading control method is provided for obtaining the original data through iterative decoding of the first code element data and the second code element data. The writing and reading control method improves the number of error codes which can be processed by the ECC circuit, and further improves the reliability of the flash memory.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing embodiments of the present invention with reference to the following drawings, in which:
FIG. 1 is a block diagram of a flash memory system;
FIG. 2 is a schematic diagram of a structure of a write control apparatus according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the storage of the original data after being encoded according to the first embodiment of the present invention;
FIG. 4 is a diagram illustrating the storage of the encoded original data according to a second embodiment of the present invention;
fig. 5 is a schematic storage diagram of original data after being encoded according to a third embodiment of the present invention.
FIG. 6 is a schematic diagram of a read control device according to an embodiment of the present invention;
FIG. 7 is a flow chart of a write control method of an embodiment of the present invention;
FIG. 8 is a flowchart of a read control method according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
Fig. 1 is a structural diagram of a flash memory system.
The flash memory system 100 is, for example, a computer system using a Solid State Disk (SSD). The computer system includes a host 130. The solid state disk includes a flash memory 110 and a memory control device 120.
The host 130 accesses the memory 110 via the memory control device 120. In the flash memory system, the storage data is encoded data generated by encoding original data, and the original data can be obtained only by decoding the storage data in the reading process. The host 130 includes, for example, a processor. In the use state, the processor loads programs or reads data from the memory 110, and writes data to the memory 110.
The flash memory 110 is composed of a plurality of memory pages P _0 to P _ N, each of which includes a plurality of memory cells M _0 to M _ K composed of floating gate transistors, each of which stores data of one or more bits (bits). The memory control device 120 reads the data stored by the memory cell by providing the appropriate sense voltage to the control gate of the transistor. For example, suppose that memory cell M _0 stores 3 bits of data, i.e., binary data that can be stored is 000,001,010,011,100,101,110,111 (2)3) Then, the memory control device 120 needs to set 8 detection voltages, and read the binary data stored in the memory cell based on the 8 detection voltages. This assumption is for illustrative purposes only and is not intended to be limiting.
The memory controller 120 is, for example, a separate integrated circuit chip including a read control device (not shown) and a write control device (not shown) for controlling reading and writing of the flash memory 110, respectively. During a write operation, the write controller encodes the original data to generate the storage data, thereby writing the storage data in the flash memory 110. During a read operation, the read controller retrieves the stored data from the flash memory 110 and then decodes the data to obtain the original data.
Fig. 2 is a schematic structural diagram of a write control apparatus according to an embodiment of the present invention.
Referring to fig. 2, the write control device 121 includes a buffer module 200, an ECC encoding circuit 201, and a memory control module 205.
The buffer module 200 is used for receiving the original data sent from the host 130 and sending the original data to the ECC encoding circuit.
The ECC encoding circuit 201 receives the original data, encodes the original data, and generates encoded data. The encoded data here includes two parts of content: raw data and symbol data. The symbol data is data obtained by encoding selected data among original data for recovering and correcting erroneous data when a read error occurs. The popular coding methods of the current ECC coding circuit include LDPC, RS and BCH.
The storage control module 205 is configured to write the encoded data into a corresponding storage block (block) and a corresponding storage page (page). The memory space of a flash memory may be divided into memory blocks (blocks), each memory block comprising a number of memory pages, each memory page comprising a number of bytes (e.g. comprising 4 kbytes), each byte being an 8-bit (bit). Different models of flash memory may have different sized blocks and pages of memory. In the existing flash memory standard, one memory block includes 64 memory pages, and one memory page includes 4k bytes, but the invention is not limited thereto. The NAND flash memory reads and writes in units of memory pages and erases in units of blocks.
In this example, the ECC encoding circuit further includes a first encoding module 202, a second encoding module 203, and a slicing module 204. The segmentation module 204 is configured to segment the original data according to a first method to obtain a plurality of first data, and segment the original data according to a second method to obtain a plurality of second data, where any one of the plurality of first data and one of the plurality of second data have a common part. The first approach is to segment the original data according to the semantic direction of the original data, for example. For example, the original data is divided according to the size of the memory page, that is, 100k of the original data may be divided into 25 first materials, i.e., 100k/4 k. The second method is to divide the first data into a plurality of divided portions, and select at least one divided portion of the plurality of first data to form the second data. For example, as previously described, a 4k first material is divided into two sliced portions, with 25 first sliced portions of the first material constituting the second material and 25 second sliced portions of the first material constituting the second material. However, the cutting method of the present invention is not limited thereto.
The first encoding module 202 is configured to perform encoding according to the first data and the first code to obtain first symbol data. The second encoding module 203 encodes according to the second data and the second encoding method to obtain second code metadata. The first symbol data and the second symbol data and the original data are written into the respective memory pages by the memory control module 205. Optionally, each of the first encoding method and the second encoding method is one of ldpc (low Density Parity Check code), rs (reed solomon code), and BCH (Bose, Ray, Hocquenghem).
The present embodiment will be further described with reference to the accompanying drawings.
Fig. 3 is a schematic storage diagram of the original data after being encoded according to the first embodiment of the present invention. FIG. 3 illustrates an example block of a NAND flash memory. The block comprises 256 storage pages 0-255, wherein original data Din and code element data Page 0-Page 255 are stored in the storage pages 0-Page 255 respectively, and the code element data ColumnCode 0-ColumnCode 15 are stored in the storage pages 256-Page 257. The symbol data PageCode0 to PageCode255 are symbol data generated from raw data in a corresponding one of the memory pages, and columnCode0 to columnCode15 are symbol data generated from raw data in a corresponding plurality of memory pages. Specifically, assuming that one storage page can store 20 kbytes of data, 4 kbytes of storage symbol data are reserved, the remaining 16 kbytes store original data, and at the same time, the 16 kbytes storage space is divided into 16 equal parts, and data stored in the storage spaces at the same positions in the PageCode 0-PageCode 255 are combined and encoded, so that 16 symbol data, columnCode 0-columnCode 15 are obtained. The symbol data columnCode0 to columnCode15 are stored in the page256 to page257 after block, respectively. Thereby, two-dimensional symbol data is obtained: horizontal and vertical symbol data. The two-dimensional code element data is beneficial to data decoding, and particularly when data has read errors, iterative error correction can be carried out on the basis of the two-dimensional code element data, so that the error correction capability of the ECC circuit is improved.
It should be noted that in this example, the symbol data may be generated by the same or different encoding methods, for example, by using the LDPC encoding method, or the horizontal symbol data may be generated by using the LDPC encoding method and the vertical symbol data may be generated by using the RS encoding method.
Fig. 4 is a schematic storage diagram of original data after being encoded according to a second embodiment of the present invention.
FIG. 4 illustrates an example block of a NAND flash memory. The block comprises 256 storage pages 0-255, wherein original data Din and code element data Page 0-Page 255 are stored in the storage pages 0-Page 255 respectively, and the code element data ColumnCode 0-ColumnCode 15 are stored in the storage pages 256-Page 257. The PageCode 0-PageCode 255 are code element data generated by LDPC coding the data stored in the corresponding memory page. The difference from fig. 3 is that columnCode0 to columnCode15 are symbol data obtained by RS encoding using different codewords (code words). Specifically, as shown in the figure, assuming that one storage page can store 20 kbytes of data, 4 kbytes of data are reserved for storing symbol data, the remaining 16 kbytes store original data, meanwhile, the 16 kbytes are uniformly divided into 16 equal parts, every 2 kbytes of data in the storage pages of the odd-numbered rows are combined together and encoded by using the same code word for RS encoding, and every 2 kbytes of data in the storage pages of the even-numbered rows are combined together and encoded by using the same code word, so that symbol data are generated. In addition, adjacent data adopt different code words as much as possible, for example, the adjacent data in the upper figure adopt four code words of RS0-RS 3. Because adjacent data are encoded by different code words to generate code element data, the probability of reading failure of the whole storage page is reduced during reading, for example, adjacent data can be decoded by adjacent code element data, and the data can be judged by adjacent data, so that the probability of reading failure of the storage page is greatly reduced.
Fig. 5 is a schematic storage diagram of original data after being encoded according to a third embodiment of the present invention.
FIG. 5 illustrates a block of two NAND flash memories. In this example, the horizontal direction is encoded according to the memory pages, i.e. the same encoding as shown in fig. 3-4 is used in the vertical direction, which is different from that of fig. 3 and 4. In this example, two blocks are encoded vertically as a whole. Both odd and even rows are encoded with RS, but the codewords used for encoding by the odd and even rows are different, and thus are distinguished as RS0 and RS 1. Further, symbol data generated based on RS0 is stored in two memory pages after the first block, and symbol data generated based on RS1 is stored in two memory pages after the second block. By storing the corresponding code element data in one block at two different positions, the probability that the code element data is damaged or read wrongly can be reduced, and the error rate can be further reduced.
It should be noted that fig. 3 to 5 are only used for exemplary illustration, and in fact, the storage location of the symbol data may be changed arbitrarily, and may be stored in the same storage block, a storage page, or an adjacent storage block as the original data, or may be stored in another storage block.
Fig. 6 is a schematic structural diagram of a read control device according to an embodiment of the present invention.
Referring to fig. 6, the read control device 122 includes a memory control module 300 and an ECC decoding circuit 301.
The memory control module 300 reads the encoded data from the corresponding memory block and memory page according to the control signal. The encoded data includes original data and symbol data.
The ECC decoding circuit 301 acquires data stored in the memory cell, decodes the encoded data, and performs data error correction processing. The ECC decoding circuit includes an iteration control module 303, a first decoding module 304, and a second decoding module 305. The iteration control module 303 is used to control the iterative decoding process, i.e. to control the alternating execution of the first decoding module 304 and the second decoding module 305. The first decoding module 304 is configured to perform decoding error correction by using a first encoding method. The second decoding module 305 is configured to perform decoding error correction by using a second decoding method. Moreover, when the first decoding module and the second decoding module fail to decode, the decoding should be stopped at this time when the original data cannot be decoded by the alternative decoding error correction.
For example. Corresponding to the written data in fig. 3, the first encoding method may be used to decode the data of pages 0-Page 255, but if the decoding of Page10 fails during the decoding process, the second encoding method is used to decode columnCode 0-columnCode 15, and since the data stored in pages 0-Page 9 and pages 11-Page 255 are successfully decoded during the first decoding, the original data at the corresponding position of Page10 can be decoded based on columnCode 0-columnCode 15. I.e. all raw data are obtained by two iterations. Of course, in other cases, more than two iterations may be required to obtain all of the raw data. Similarly, for the data written in fig. 4 and 5, iterative decoding and error correction can be performed by the first decoding module and the second decoding module, so as to obtain a higher decoding success rate.
Fig. 7 is a flowchart of a write control method according to an embodiment of the present invention. The write control method is applied to the flash memory and specifically comprises the following steps.
In step S701, the original data is segmented according to a first method to obtain a plurality of first data.
In step S702, the original data is segmented according to a second method to obtain a plurality of second data.
Raw data such as binary data, ASCII data, etc. The first data and the second data are obtained through two different segmentation modes. Any one of the first data and at least one of the second data have a common portion.
In step S703, a plurality of first data are encoded to obtain a plurality of first symbol data.
In step S704, a plurality of second data are encoded to obtain a plurality of second metadata.
The first symbol data and the second symbol data are generated by a plurality of coding methods such as LDPC, BCH, and RS.
In step S705, the original data, the plurality of first symbol data, and the plurality of second symbol data are stored to corresponding storage locations of the flash memory.
The original data, the first symbol data and the second symbol data may be dispersedly stored in corresponding locations of the flash memory, for example, the original data is stored in memory pages, and each memory page is followed by the first symbol data corresponding to the stored data in the memory page. The second code metadata and the original data are stored in the same memory block or in a memory page subsequent to the memory block to which the original data belongs.
FIG. 8 is a flowchart of a read control method according to an embodiment of the present invention. The read control method is applied to the flash memory and is used for reading the data written into the flash memory by the write control method of the embodiment.
In step S801, encoded data is read from a corresponding location of the flash memory, the encoded data including original data, first symbol data, and second symbol data.
In step S802, the original data is iteratively decoded and error-corrected based on the first symbol data and the second symbol data. When the read original data is in error or needs to be verified, iterative decoding and error correction can be adopted for checking and correcting. In the process, for example, the correct data obtained from all code words of the first coding method can be substituted into the decoding process of the second coding method to obtain more correct data until all the original data are finally obtained or until more data cannot be decoded finally.
In summary, the write control method provided by the present invention performs two-dimensional encoding when writing into the flash memory, and stores two-dimensional encoded data, so as to improve the decoding and error correction capability of the ECC circuit, and further improve the reliability and product yield of the flash memory.
Although the preferred embodiments of the present invention have been disclosed in the foregoing description, it should be understood that they are not intended to limit the scope of the claims, but rather the scope of the invention is to be defined by the following claims.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (16)
1. A write control method of a flash memory includes:
segmenting original data according to a first mode to obtain a plurality of first data;
segmenting original data according to a second mode to obtain a plurality of second materials, wherein any one of the first materials and one of the second materials have a common part;
encoding the first data to obtain a plurality of first code element data;
encoding the second data to obtain second code metadata; and
storing the original data, the plurality of first symbol data, and the plurality of second symbol data to respective storage locations of the flash memory,
the first mode divides the original data according to the semantic direction of the original data to obtain a plurality of first materials, the second mode divides each first material in the plurality of first materials to obtain a plurality of divided parts, the plurality of divided parts form the plurality of second materials, and the plurality of divided parts forming each second material are at least from two first materials.
2. The write control method according to claim 1, wherein each of the first data is stored in one memory page, and each of the second data is stored in a plurality of memory pages.
3. The write control method according to claim 2, wherein the first data and the first symbol data are stored in a same memory block, and the second symbol data are stored in a memory page subsequent to the corresponding memory block.
4. The write control method according to claim 1, wherein the plurality of first data are encoded by a first encoding method; and encoding the plurality of second data by using a second encoding method.
5. The write control method according to claim 4, wherein the first encoding method is an LDPC encoding method, and the second encoding method is an RS encoding method.
6. A read control method of a flash memory for reading data written in the flash memory by the write control method according to any one of claims 4 to 5, comprising:
reading encoded data from respective locations of the flash memory, the encoded data including original data, first symbol data, and second symbol data; and
iteratively decoding and correcting the original data according to the first symbol data and the second symbol data.
7. The read control method of claim 6, wherein the iteratively decoding and error correcting the original data according to the first symbol data and the second symbol data comprises:
decoding and error correcting the first symbol data using the first encoding method;
decoding and correcting the second code element data by adopting the second coding method according to the decoding result of the first code element data; and
and decoding and correcting the first code element data by adopting the first coding method according to the decoding result of the second code element data.
8. The read control method of claim 7, further comprising: and stopping decoding when all the code words adopting the first coding method and all the code words adopting the second coding method fail to be decoded.
9. A write control apparatus of a flash memory, comprising:
the segmentation module is used for segmenting the original data according to a first mode to obtain a plurality of first data; segmenting original data according to a second mode to obtain a plurality of second data, wherein any one of the first data and one of the second data have a common part;
a first encoding module, configured to encode the first data to obtain a plurality of first symbol data;
the second coding module is used for coding the second data to obtain second code metadata; and
a storage control module for storing the original data, the plurality of first symbol data and the plurality of second symbol data to respective storage locations of the flash memory,
the segmentation module segments the original data according to the semantic direction of the original data to obtain a plurality of first data, segments each of the plurality of first data to obtain a plurality of segments, combines the plurality of segments into a plurality of second data, and combines the plurality of segments of each second data from at least two first data.
10. The write control device according to claim 9, wherein the memory control module controls each first datum to be stored in one memory page, and each second datum to be stored in a plurality of memory pages.
11. The write control device according to claim 10, wherein the storage control module controls the first material and the first symbol data to be stored in a same memory block and the second symbol data to be stored in a memory page subsequent to the corresponding memory block.
12. The write control apparatus according to claim 9, wherein the first encoding module encodes the plurality of first materials by a first encoding method; the second coding module codes the plurality of second data by adopting a second coding method.
13. The write control apparatus according to claim 12, wherein the first encoding method is an LDPC encoding method, and the second encoding method is an RS encoding method.
14. A read control device of a flash memory for reading data written into the flash memory by the write control device of the flash memory according to any one of claims 9 to 13, comprising:
a reading module, configured to read encoded data from a corresponding location of the flash memory, where the encoded data includes original data, first symbol data, and second symbol data;
a first decoding module for decoding and correcting errors according to the first symbol data;
the second decoding module is used for decoding and correcting errors according to the second code metadata;
and the iteration control module is used for controlling the first decoding module and the second decoding module to carry out iterative decoding and error correction.
15. The read control device of the flash memory according to claim 14, further comprising: and the iteration control module stops decoding after judging that the first decoding module and the second decoding module fail to decode.
16. A memory system comprising a flash memory and a memory controller, the controller comprising the write control apparatus of any one of claims 9 to 13 and the read control apparatus of any one of claims 14 to 15.
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|---|---|---|---|---|
| US9230684B2 (en) * | 2012-12-19 | 2016-01-05 | Kabushiki Kaisha Toshiba | Memory controller, storage device, and memory control method |
| CN107402829A (en) * | 2016-04-05 | 2017-11-28 | 阿里巴巴集团控股有限公司 | For detecting and correcting equipment, the method and computer program product of bit-errors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9230684B2 (en) * | 2012-12-19 | 2016-01-05 | Kabushiki Kaisha Toshiba | Memory controller, storage device, and memory control method |
| CN107402829A (en) * | 2016-04-05 | 2017-11-28 | 阿里巴巴集团控股有限公司 | For detecting and correcting equipment, the method and computer program product of bit-errors |
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