CN108154849B - Pixel, reference circuit and timing technique - Google Patents

Abstract

A system and method for compensating images produced by active matrix light emitting diode devices and other emissive displays is disclosed. The calibration and compensation are performed by using the existing data lines or other lines which can be individually controlled, and the luminance abnormality generated by the pixel circuit and the bias current generated by the current bias circuit for driving the current bias program pixel are corrected by the calibration and compensation.

Description

Pixel, reference circuit and timing technique

Technical Field

The present invention relates to pixels, current biasing, and signal timing for light emitting visual display technology, and in particular, to systems and methods for programming and calibrating pixels and pixel current biasing in active matrix light emitting diode devices (AMOLEDs) and other emissive displays.

This application claims priority to U.S. patent application 15/361,660 filed on 28/11/2016 and the entire contents of this priority document are incorporated herein by reference.

Background

Many current display technologies are adversely affected by imperfections, variations and non-uniformities that arise during manufacture, and may also be adversely affected by aging and degradation over the lifetime of the display, which results in deviations of the generated image from the desired image. Methods of image calibration and compensation are used to calibrate these defects to produce a more accurate, uniform image, or to produce an image that more closely reproduces the image data represents. Some displays utilize a current bias voltage programming drive scheme, with each pixel of the display being a Current Bias Voltage Programming (CBVP) pixel. In such displays, there are also requirements for generating and maintaining accurate image reproduction as follows: the current biasing element (i.e., current source or current sink) used to provide the current bias provides the appropriate level of current bias to those pixels.

Since variations in manufacturing and variations in usage degradation cannot be avoided, some of the current biasing elements provided for the display and the pixels of the display, while designed to be equally uniform and accurate and programmed to provide a desired current bias level and corresponding desired brightness, actually exhibit a deviation in current bias and corresponding provided brightness. To correct for visual defects caused by these current sources or current sinks and non-uniformities and inaccuracies in the pixels, calibration and selective monitoring and compensation are added to the programming of the current biasing elements and pixels.

As the resolution of array semiconductor devices increases, the number of lines and elements required to drive, calibrate and/or monitor the array increases dramatically. This may result in higher power consumption, higher manufacturing costs, and a larger physical footprint. In the case of CBVP pixel displays, as the number of rows or columns increases, providing circuitry to program, calibrate, and monitor the current sources or current sinks can increase the cost and complexity of the integrated circuit.

Disclosure of Invention

According to a first aspect, there is provided a system for generating a current for a pixel of an emissive display system, each pixel having a light emitting device, the system comprising: a plurality of pixels; a plurality of current generating circuits for supplying a current to at least one corresponding pixel; and a controller connected to the current generation circuit via a plurality of signal lines to control the current generation circuit; wherein each of the current generation circuits includes: at least one drive transistor for providing a current to the pixel; and a storage capacitor for being programmed and for setting a magnitude of a current provided by the at least one drive transistor, wherein the controller controls each of the current generation circuits to include: charging the storage capacitor to a defined level during a programming cycle; and after the programming period, partially discharging the storage capacitor as a function of the characteristics of the at least one drive transistor during a calibration period.

In some embodiments, the at least one driving transistor comprises a driving transistor, and the controller controls each of the current generation circuits further comprises: charging the storage capacitor connected to the gate terminal of the drive transistor to contain a threshold voltage of the drive transistor during the programming cycle such that a voltage between the source terminal and the drain terminal during the lighting cycle is a function of the threshold voltage of the drive transistor during the lighting cycle.

In some embodiments, the at least one driving transistor comprises a driving transistor, and the controller controls each of the current generation circuits further comprises: charging the storage capacitor connected to the gate terminal of the drive transistor during the programming period to include at least a first voltage applied to the source terminal of the drive transistor such that the voltage between the source terminal and the drain terminal is independent of the first voltage during a light emission period in which the source terminal of the drive transistor is held at the first voltage.

In some embodiments, the first voltage is one of VDD and VMON. In some embodiments, each current generating circuit comprises one of a reference current sink and a reference current source for providing a current for the at least one corresponding pixel, the current being arranged to provide a reference current bias for the at least one corresponding pixel. In some embodiments, each pixel comprises the current generating circuit for providing the current to the pixel, the current being arranged to drive the light emitting device of the pixel. In some embodiments, the light emitting device is an Organic Light Emitting Diode (OLED).

In some embodiments, the controller controlling each of the current generation circuits further comprises: resetting at least one of an anode of the OLED and a terminal of the at least one driving transistor to a low reference voltage during a reset period starting at substantially the same time as the light emitting period.

According to a second aspect of the present invention there is provided a method of generating a current for pixels of an emissive display system, each pixel having a light emitting device, the system comprising a plurality of pixels, a plurality of current generating circuits for supplying a current to at least one respective pixel, each said current generating circuit comprising at least one drive transistor for supplying said current to said pixel and a storage capacitor for being programmed and setting the magnitude of said current to be supplied by said at least one drive transistor, the method comprising controlling each said current generating circuit via a plurality of lines, comprising: charging the storage capacitor to a defined level during a programming cycle; and after the programming period, partially discharging the storage capacitor as a function of the characteristics of the at least one drive transistor during a calibration period.

In some embodiments, the at least one drive transistor comprises a drive transistor, and controlling each of the current generation circuits further comprises: charging the storage capacitor connected to the gate terminal of the drive transistor to contain a threshold voltage of the drive transistor during the programming period such that a voltage between the source terminal and the drain terminal is a function of the threshold voltage of the drive transistor during a lighting period.

In some embodiments, the at least one drive transistor comprises a drive transistor, and controlling each of the current generation circuits further comprises: charging the storage capacitor connected to the gate terminal of the drive transistor during the programming period to include at least a first voltage applied to the source terminal of the drive transistor such that the voltage between the source terminal and the drain terminal is independent of the first voltage during a light emission period in which the first voltage is maintained at the source terminal of the drive transistor.

In some embodiments, controlling each of the current generation circuits further comprises: resetting at least one of an anode of the OLED and a terminal of the at least one driving transistor to a low reference voltage during a reset period starting at substantially the same time as the light emitting period.

The foregoing and additional aspects and embodiments of the present invention will become apparent to those of ordinary skill in the art in view of the detailed description of the various embodiments and/or aspects, which proceeds with reference to the accompanying figures, a brief description of which is provided next.

Drawings

The above and other advantages of the invention will become more apparent upon reading the following detailed description and upon reference to the accompanying drawings.

FIG. 1 illustrates an exemplary display system utilizing the disclosed methods and including the disclosed pixels and current biasing elements;

FIG. 2 is a circuit diagram of a current sink according to one embodiment;

FIG. 3 is a timing diagram of current sink and current source programming and calibration according to one embodiment;

FIG. 4 is a circuit diagram of a current source according to another embodiment;

FIG. 5 is a circuit diagram of a 4T1C pixel circuit according to an embodiment;

FIG. 6A is a timing diagram illustrating the programming and driving of a 4T1C pixel circuit;

FIG. 6B is a timing diagram illustrating the programming and measurement of a 4T1C pixel circuit;

fig. 7 is a circuit diagram of a 6T1C pixel circuit according to an embodiment;

FIG. 8A is a timing diagram illustrating the programming and driving of a 6T1C pixel circuit;

FIG. 8B is a timing diagram illustrating the programming and measurement of a 6T1C pixel circuit;

FIG. 9 is a timing diagram for improved driving of the rows of pixels;

FIG. 10 is a circuit diagram of a 4T1C pixel circuit operating in current mode according to an embodiment;

FIG. 11 is a circuit diagram of a 6T1C pixel circuit operating in current mode according to an embodiment;

fig. 12 is a timing diagram illustrating programming and driving of the 4T1C pixel circuit and the 6T1C pixel circuit in fig. 10 and 11;

FIG. 13 is a circuit diagram of a 4T1C reference current sink according to an embodiment;

FIG. 14 is a circuit diagram of a 6T1C reference current sink according to an embodiment;

FIG. 15 is a circuit diagram of a 4T1C reference current source according to an embodiment;

fig. 16 is a circuit diagram of a 6T1C reference current source according to an embodiment;

FIG. 17 is a reference row timing diagram illustrating the programming and driving of the 4T1C, 6T1C reference current sink and reference current source in FIGS. 13-16; and

FIG. 18 is a schematic diagram of on-panel multiplexing (on-panel multiplexing) of data lines and monitor lines.

While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Detailed Description

The system and method disclosed hereinafter addresses these problems by: the timing and calibration of the pixel circuits and the set of current biasing elements are controlled while utilizing circuitry integrated on the display in a manner that uses existing display components.

Although the embodiments described herein are based on the context of an AMOLED display, it should be understood that the systems and methods described herein can be applied to any other display that contains pixels that can be biased with current, including but not limited to light emitting diode displays (LEDs), electroluminescent displays (ELDs), organic light emitting diode displays (OLEDs), plasma display panels (PSPs), and other displays.

It should be understood that the embodiments described herein relate to systems and methods of calibration and compensation and are not limited to display technologies based on their operation and the operation of the displays in which they are implemented. The systems and methods described herein can be applied to various types and implementations of various visual display technologies.

FIG. 1 is a diagram of an example of a display system 150 implementing the method and including circuitry to be described below. The display system 150 includes a display panel 120, an address driver 108, a source driver 104, a controller 102, and a memory 106.

The display panel 120 includes an array of pixels 110a, 110b (only two are explicitly shown) arranged in rows and columns. Each pixel 110a, 110b is individually programmable to emit light at an individually programmed luminance value and is a current bias voltage programmed pixel (CBVP). The controller 102 receives digital data representing information to be displayed on the display panel 120. The controller 102 sends a signal 132 to the source driver 104 and a scheduling signal 134 to the address driver 108 to drive the pixels 110 in the display panel 120 to display the indicated information. The plurality of pixels 110 of the display panel 120 thus comprise a display array or screen adapted to dynamically display information in accordance with input digital data received by the controller 102. The display screen is capable of displaying a stream of images and video information based on the data received by the controller 102. The supply voltage 114 provides a constant voltage or can be used as an adjustable voltage source controlled by a signal from the controller 102. The display system 150 includes features from current bias elements 155a, 155b (current sources or current sinks, shown as current sinks) to provide bias currents to the pixels 110a, 110b in the display panel 120, thereby reducing the programming time of the pixels 110. Although shown separately from the source driver 104, the current biasing elements 155a, 155b may be formed separately from the source driver 104 or may be integrated as separate elements. It will be appreciated that the current biasing elements 155a, 155b used to provide current biasing for the pixel may also be current sources other than the current sink shown in figure 1.

For purposes of illustration, only two pixels 110a and 110b are explicitly shown in the display system 150 in FIG. 1. It should be understood that display system 150 is implemented with a display screen that includes an array of pixels, such as pixels 110a and 110b, and that the display screen is not limited to a particular number of rows and columns of pixels. For example, the display system 150 can be implemented with a display screen having a plurality of rows and columns of pixels commonly available in displays for mobile devices, display-based devices, and/or projection devices. In a multi-channel or color display, there are a plurality of different kinds of pixels in the display, each pixel being responsible for reproducing the color of a characteristic channel or a color such as red, green or blue. Such pixels may also be referred to as "subpixels," because a group of such pixels collectively provide a desired color in a particular row and column of the display, and the group of subpixels may also be collectively referred to as a "pixel.

Each pixel 110a, 110b is operated by a drive circuit or pixel circuit, which typically includes a drive transistor and a light emitting device. Hereinafter, the pixels 110a, 110b may be referred to as pixel circuits. The light emitting devices can alternatively be organic light emitting diodes, but embodiments of the invention employ pixel circuits with other electroluminescent devices, including current driven light emitting devices and those listed above. Alternatively, the driving transistors in the pixels 110a, 110b are n-type or p-type amorphous silicon thin film transistors, but embodiments of the present invention are not limited to pixel circuits having transistors of a particular polarity or to pixel circuits having thin film transistors. The pixel circuits 110a, 110b can also include storage capacitors for storing programming information and enabling the pixel circuits 110 to drive the light emitting devices after being addressed. Thus, the display panel 120 can be an active matrix display array.

As shown in FIG. 1, each pixel 110a, 110b in the display panel 120 is connected to a respective select line 124a, 124b, a respective power line 126a, 126b, a respective data line 122a, 122b, a respective current bias line 123a, 123b, and a respective monitor line 128a, 128 b. A read line may also be included for controlling the connection of the monitor line. In one embodiment, the power supply voltage 114 can also provide a second power supply line to each pixel 110a, 110 b. For example, each pixel can be connected to a first power line 126a, 126b charged with Vdd and a second power line 127a, 127b connected to Vss, and the pixel circuit 110a, 110b can be located between the first and second power lines to drive current between the two power lines during the emission phase of the pixel circuit. It should be understood that each pixel 110 in the pixel array of the display 120 is connected to the appropriate select, power, data, and monitor lines. Note that aspects of the present invention are applicable to pixels having additional connections, such as connections to additional select lines, and to pixels having fewer connections, as well as to pixels sharing multiple connections.

Referring to the pixel 110a of the display panel 120, the select line 124a is set by the address driver 108 and can be used to enable a programming operation of the pixel 110a by: the switch or transistor is activated to cause the data line 122a to program the pixel 110 a. The data line 122a transmits programming information from the source driver 104 to the pixel 110 a. For example, the data line 122a can be used to apply a programming voltage or a programming current to the pixel 110a to program the pixel 110a to emit a desired amount of brightness. The programming voltage (or programming current) provided by source driver 104 via data line 122a is a voltage (or current) suitable for causing pixel 110a to emit light at a desired amount of brightness in accordance with the digital data received by controller 102. A programming voltage (or a programming current) can be applied to the pixel 110a during a programming operation of the pixel 110a to charge a storage device (such as a memory, etc.) in the pixel 110a, thereby enabling the pixel 110a to emit light with a desired amount of brightness during an emission operation after the programming operation. For example, the storage device in the pixel 110a may be charged during a programming operation to apply a voltage to one or more of the gate or source terminals of the drive transistor during an emission operation, thereby causing the drive transistor to pass a drive current through the light emitting device according to the voltage stored in the storage device. The current bias element 155a provides a bias current to the pixel 110a via the current bias line 123a in the display panel 120, thereby reducing the programming time of the pixel 110 a. The current biasing element 155a is also connected to the data line 122a and the current output of the current biasing element is programmed using the data line 122a when not being used to program a pixel as described below. In some embodiments, the current biasing elements 155a, 155b are also connected to a reference/monitor line 160 connected to the controller 102 for monitoring and controlling the current biasing elements 155a, 155 b.

Generally, in the pixel 110a, a driving current transmitted through the light emitting device by the driving transistor during an emission operation of the pixel 110a is a current supplied from the first power line 126a and discharged to the second power line 127 a. The first power line 126a and the second power line 127a are connected to the power supply voltage 114. The first power line 126a can provide a positive power supply voltage (e.g., a voltage collectively referred to as "Vdd" in circuit design) and the second power line 127a can provide a negative power supply voltage (e.g., a voltage collectively referred to as "Vss" in circuit design). Embodiments of the invention can be implemented with one or the other of the power lines (e.g., power line 127a) being tied to a ground voltage or another reference voltage.

The display system 150 also includes a monitoring system 112. Referring again to the pixel 110a of the display panel 120, the monitor line 128a connects the pixel 110a to the monitor system 112. The monitoring system 112 can be integrated with the source driver 104 or can be a separate stand-alone system. In particular, the monitoring system 112 can be selectively implemented by monitoring the current and/or voltage of the data line 122a during a monitoring operation of the pixel 110a, and the monitoring line 128a can be omitted entirely. The monitor line 128a enables the monitoring system 112 to measure a current or voltage associated with the pixel 110a to extract information indicative of degradation or aging of the pixel 110a or indicative of the temperature of the pixel 110 a. In some embodiments, the display panel 120 includes temperature sensing circuitry implemented in the pixels 110a that is dedicated to sensing temperature, while in other embodiments the pixels 110a include circuitry that participates in both sensing temperature and driving the pixels. For example, the monitoring system 112 can extract the current flowing through the drive transistor in the pixel 110a via the monitoring line 128a, and can thus determine the threshold voltage or offset of the drive transistor based on the detected current and the voltage supplied to the drive transistor during the measurement. In some embodiments, the monitoring system 112 extracts information about the current biasing element via the data lines 122a, 122b or the reference/monitor line 160, and in some embodiments this is done by the controller 102 or in cooperation with the controller 102.

The monitoring system 112 is also capable of extracting an operating voltage of the light emitting device (e.g., a voltage drop across the light emitting device when the light emitting device is operating to emit light). The monitoring system 112 can then communicate the signal 132 with the controller 102 and/or the memory 106 to enable the display system 150 to store the extracted aging information in the memory 106. During subsequent programming and/or emission operations of the pixel 110a, this aging information is retrieved from the memory 106 by the controller 102 via the stored signal 136, and the controller 102 then compensates for the extracted degradation information in subsequent programming and/or emission operations of the pixel 110 a. For example, once the degradation information is extracted, the programming information transmitted to the pixel 110a via the data line 122a can be appropriately adjusted during a subsequent programming operation of the pixel 110a to cause the pixel 110a to emit light with a desired amount of luminance that is not affected by the degradation of the pixel 110 a. In an example, an increase in the threshold voltage of the drive transistor in the pixel 110a can be compensated for by appropriately increasing the programming voltage applied to the pixel 110 a. In a similar manner, the monitoring system 112 can extract the bias current of the current biasing element 155 a. The monitoring system 112 can then communicate the signal 132 with the controller 102 and/or the memory 106 to enable the display system 150 to store the extracted information in the memory 106. In subsequent programming of the current biasing element 155a, this information is retrieved from the memory 106 by the controller 102 via the stored signal 136, and the controller 102 then compensates for the error in the previously detected current with the adjustment in subsequent programming of the current biasing element 155 a.

Referring now to fig. 2, a circuit configuration of a current sink 200 according to an embodiment is illustrated. The current sink 200 corresponds, for example, to the single current bias element 155a, 155b of the display system 150 shown in fig. 1, which provides a bias current Ibias to the CBVP pixel 110a, 110b through the current bias line 123a, 123 b. The current sink 200 shown in fig. 2 is based on PMOS transistors. PMOS based current sources are contemplated, constructed and function according to similar principles described herein. It should be understood that variations of the current sink and its function are contemplated and include different types of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The current sink 200 comprises a first switching transistor 202(T4), the first switching transistor 202 being controlled by an enable signal EN connected to its gate terminal and being connected via one of the source and drain terminals to a current bias line 223(Ibias), for example corresponding to the current bias line 123a of fig. 1, and via the other of the source and drain terminals to a first terminal of the storage capacitor 210. The gate terminal of the current drive transistor 206(T1) is connected to the second terminal of the storage capacitor 210, and one of the source terminal and the drain terminal of the current drive transistor 206 is connected to the first terminal of the storage capacitor 210. The other of the source terminal and the drain terminal of the current drive transistor 206 is connected to VSS. The gate terminal of the second switching transistor 208(T2) is connected to a write signal line (WR), and one of the source terminal and the drain terminal thereof is connected to a voltage bias or data line 222(Vbias) corresponding to the data line 122a shown in fig. 1, for example. The other of the source terminal and the drain terminal of the second switching transistor 208(T2) is connected to the second terminal of the storage capacitor 210. The gate terminal (T3) of the third switching transistor 204 is connected to a calibration control line (CAL), and one of the source terminal and the drain terminal thereof is connected to a reference monitor line 260 corresponding to the reference monitor line 160 shown in fig. 1, for example. The other of the source terminal and the drain terminal of the third switching transistor 204 is connected to the first terminal of the storage capacitor 210. As described above, the data lines are shared and used to provide the transformed bias or data for the pixels during certain periods of the frame and to provide the voltage bias for the current biasing element (here, the current sink) during other periods of the frame. This reuse of the data line enables the additional benefits of programming and compensation by multiple separate current sinks using only one additional reference monitor line 160.

Referring also to fig. 3, a timing example of a current control cycle for programming and calibrating the current sink 200 shown in fig. 2 is now described. The complete control period 300 typically occurs once per frame and includes four sub-periods: an off period 302, a programming period 304, a calibration period 306, and a stabilization period 308. During the off period 302, the current sink 200 stops providing the bias current Ibias to the current bias line 223 in response to the EN signal going high and the first switching transistor 202 turning off. The second and third switching transistors 208, 204 remain off by virtue of the CAL and WR signals going high. The duration of the open period 302 also provides a settling time for the current sink 200 current. The EN signal remains high throughout control period 300 and goes low only when current sink 200 has completed programming, calibration, and settling and is ready to provide bias current via current bias line 223. Once the current sink 200 stabilizes after the off period 302 is completed, the programming period 304 begins by the WR signal going low turning on the second switching transistor 208 and the CAL signal going low turning on the third switching transistor 204. During the programming cycle 304, the third switching transistor 204 connects a reference monitor line 260, having a known reference signal (which may be a voltage or current) transmitted thereon, to a first terminal of the storage capacitor 210, while the second switching transistor 208 connects a voltage bias or data line 222, having a voltage Vbias input thereto, to the gate terminal of the current drive transistor 206 and to a second terminal of the storage capacitor 210. Thus, the storage capacitor 210 is charged to a defined value. This value is approximately that which would be expected to be necessary to control the current drive transistor 206 to deliver the appropriate current bias Ibias, taking into account the optional calibration described below.

After the programming period 304 and during the calibration period 306, the circuit is reset for draining a portion of the voltage (charge) of the storage capacitor 210 through the current drive transistor 206. The calibration signal CAL goes high, thereby turning off the third switching transistor 204 and disconnecting the first terminal of the storage capacitor 210 from the reference monitor line 260. The amount of draining is a function of the primary elements of the current sink 200 (i.e., the current drive transistor 206 or its associated components). For example, if the current drive transistor 206 is "strong," draining occurs relatively quickly, and relatively more charge is drained from the storage capacitor 210 via the current drive transistor 206 for a fixed duration of the calibration period 306. On the other hand, if the current drive transistor 206 is "weak," draining occurs relatively slowly, and relatively less charge is drained from the storage capacitor 210 via the current drive transistor 206 for a fixed duration of the calibration period 306. Thus, for a relatively strong current drive transistor, the voltage (charge) stored in the storage capacitor 210 decreases relatively more; conversely, for relatively weak current drive transistors, the voltage (charge) stored in the storage capacitor 210 is reduced relatively less, thereby providing some compensation for non-uniformities and differences in the current drive transistors throughout the display, whether due to differences in manufacturing or differences in degradation over time.

After the calibration period 306, a stabilization period 308 occurs before the bias current Ibias is provided to the current bias line 223. During the settling period 308, the first and third switching transistors 202, 204 remain off, while the WR signal goes high to turn off the second switching transistor 208 as well. After the end of the duration of the stabilization period 308, the enable signal EN goes low to turn on the first switching transistor 202 and enable the current driving transistor 206 to sink the bias current Ibias on the current bias line 223 to provide compensation for the specific characteristics of the current driving transistor 206 in accordance with the voltage (charge) stored in the storage capacitor 210 having a value that has been drained as a function of the current driving transistor 206 as described above.

In some embodiments, the calibration period 306 is eliminated. In such a case, compensation, which appears as a change in the voltage (charge) stored by the storage capacitor 210 as a function of the characteristics of the current drive transistor 206, is not automatically provided. In such a case, a form of manual compensation may be employed in conjunction with the monitoring.

In some embodiments, after the current sink 200 is programmed, and before providing the bias current to the current bias line 223, the current of the current sink 200 is measured via the reference monitor line 260 by controlling the CAL signal to go low to turn on the third switching transistor 204. As shown in fig. 1, in some embodiments, the reference monitor line 160 is shared and therefore during measurement of the target current sink 200, all other current sinks are programmed or controlled so that they do not source or sink any current on the reference monitor line 160. Once the current of the current sink 200 has been measured in response to known programming of the current sink 200 and possibly after a plurality of various current measurements in response to a plurality of programmed values have been measured and stored in the memory 106, the controller 102 and the memory 106 (possibly in conjunction with other components of the display system 150) adjust the voltage Vbias used to program the current sink 200 to compensate for deviations exhibited by the current sink 200 from a desired or ideal current sink. Such monitoring and compensation need not be done every frame and can be done in a periodic manner over the lifetime of the display to correct for degradation of the current sink 200.

In some embodiments, a combination of calibration and monitoring and compensation is used. In such a case, in conjunction with periodic monitoring and compensation, calibration may be performed every frame.

A circuit configuration of a current source 400 according to an embodiment will now be explained with reference to fig. 4. The current source 400, for example, corresponds to the single current bias element 155a, 155b of the display system 150 shown in fig. 1, which provides a bias current Ibias to the CBVP pixel 110a, 110b via the current bias line 123a, 123 b. As will be explained in detail below, the manner in which the current source 400 is connected and integrated in the display system 150 is slightly different than that shown in fig. 1 for the current sink 200. The current source 400 shown in fig. 4 the current source 400 is based on PMOS transistors. It should be understood that variations of this current source and its function are contemplated and include different kinds of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The current source 400 comprises a first switching transistor 402(T4), the first switching transistor 402 being controlled by an enable signal EN connected to its gate terminal and connected via one of the source and drain terminals of the first switching transistor 402 to a current bias line 423(Ibias), for example, corresponding to the current bias line 123a of fig. 1. The gate terminal of the current-driving transistor 406(T1) is connected to the first terminal of the storage capacitor 410, a first one of the source terminal and the drain terminal of the current-driving transistor 406 is connected to the other one of the source terminal and the drain terminal of the first switching transistor 402, and a second one of the source terminal and the drain terminal of the current-driving transistor 406 is connected to the second terminal of the storage capacitor 410. A second terminal of the storage capacitor 410 is connected to VDD. The gate terminal of the second switching transistor 408(T2) is connected to the write signal line (WR), one of the source terminal and the drain terminal thereof is connected to the first terminal of the storage capacitor 410, and the other of the source terminal and the drain terminal thereof is connected to the first of the source terminal and the drain terminal of the current driving transistor 406. The gate terminal of the third switching transistor 404(T3) is connected to a calibration control line (CAL), one of its source and drain terminals is connected to a voltage bias monitor line 460, for example, corresponding to the voltage bias or data lines 122a, 122b shown in fig. 1. The other of the source terminal and the drain terminal of the third switching transistor 404 is connected to the first of the source terminal and the drain terminal of the current driving transistor 406.

In the embodiment shown in FIG. 4, the current source is not connected to the reference monitor line 160 as shown in FIG. 1. Instead of programming the current source 400 with Vbias and a reference voltage as is the case with the current sink 200, the storage capacitor 410 of the current source 400 is charged to a defined value using VDD and a voltage bias signal Vbias provided by a voltage bias or data line 122 a. In this embodiment, the data lines 122a, 122b are used as monitor lines when needed.

Referring again to fig. 3, an example of the timing of the circuit control cycle 300 shown in the figure for programming and calibrating the current source 400 will now be described. The timing of the circuit control cycle 300 for programming and calibrating the current source 400 of fig. 4 is the same as that for the current sink 200 of fig. 2.

The complete control period 300 typically occurs once per frame and includes four sub-periods: an off period 302, a programming period 304, a calibration period 306, and a stabilization period 308. During the off period 302, the current source 400 stops providing the bias current Ibias to the current bias line 423 in response to the EN signal going high and the first switching transistor 402 being turned off. The second and third switching transistors 408, 404 remain off by virtue of the CAL and WR signals going high. The duration of the off period 302 also provides a settling time for the current source 400 circuit. The EN signal remains high throughout control period 300 and goes low only when current source 400 has completed programming, calibration, and settling and is ready to provide bias current via current bias line 423. Once the current source 400 stabilizes after the off period 302 is completed, the programming period 304 begins by the WR signal going low to turn on the second switching transistor 408 and the CAL signal going low to turn on the third switching transistor 404. Thus, during the programming cycle 304, the third switching transistor 404 and the second switching transistor 408 connect the voltage bias monitor line 460, having the known Vbias signal transmitted thereon, to the first terminal of the storage capacitor 410. Thus, since the second terminal of the storage capacitor 410 is connected to the top VDD, the storage capacitor 410 is charged to a defined value. This value is approximately that which would be expected to be necessary to control the current drive transistor 406 to deliver the appropriate current bias Ibias, taking into account the optional calibration described below.

After the programming period 304 and during the calibration period 306, the circuit is reset for draining a portion of the voltage (charge) of the storage capacitor 410 through the current drive transistor 406. The calibration signal CAL goes high, thereby turning off the third switching transistor 404 and disconnecting the first terminal of the storage capacitor 410 from the voltage bias monitor line 460. The amount drained is a function of the primary element of the current source 400 (i.e., the current drive transistor 406 or its associated components). For example, if the current drive transistor 406 is "strong," draining occurs relatively quickly, and relatively more charge is drained from the storage capacitor 410 via the current drive transistor 406 for a fixed duration of the calibration period 306. On the other hand, if the current drive transistor 406 is "weak," draining occurs relatively slowly and relatively less charge is drained from the storage capacitor 410 via the current drive transistor 406 for a fixed duration of the calibration period 306. Thus, for a relatively strong current drive transistor, the voltage (charge) stored in the storage capacitor 410 is reduced relatively more; conversely, for relatively weak current drive transistors, the voltage (charge) stored in the storage capacitor 410 is reduced relatively less, thereby providing some compensation for non-uniformity and variability of the current drive transistors across the display (whether due to differences in manufacturing or differences in degradation over time).

After the calibration period 306, a stabilization period 308 occurs before the bias current Ibias is provided to the current bias line 423. During the stabilization period 308, the first and third switching transistors 402, 404 remain off, while the WR signal goes high to turn off the second switching transistor 408 as well. After the end of the duration of the stabilization period 308, the enable signal EN goes low to turn on the first switching transistor 402 and enable the current driving transistor 406 to provide the bias current Ibias on the current bias line 423 to provide compensation for the specific characteristics of the current driving transistor 406 in accordance with the voltage (charge) stored in the storage capacitor 410 having the value that has been drained as a function of the current driving transistor 206 as described above.

In some embodiments, the calibration period 306 is eliminated. In such a case, compensation, which appears as a change in the voltage (charge) stored by the storage capacitor 410 as a function of the characteristics of the current drive transistor 406, is not automatically provided. In such a case, similar to the above-described embodiment based on the current sink 200, a form of manual compensation may be employed in connection with the monitoring for the current source 400.

In some embodiments, after the current source 400 is programmed, and before providing bias current to the current bias line 423, the current of the current source 400 is measured via the voltage bias monitor line 460 by controlling the CAL signal to go low to turn on the third switching transistor 404.

Once the current of the current source 400 has been measured in response to the known programming of the current source 400 and possibly after a plurality of current measurements in response to a plurality of programmed values have been measured and stored in the memory 106, the controller 102 and the memory 106 (possibly in conjunction with other components of the display system 150) adjust the voltage Vbias used to program the current source 400 to compensate for the deviation exhibited by the current source 400 from a desired or ideal current source. Such monitoring and compensation need not be done every frame and can be done in a periodic manner over the lifetime of the display to correct for degradation of the current source 400.

Although the current sink 200 of fig. 2 and the current source 400 of fig. 4 are illustrated as having a single current drive transistor 206, 406, it should be understood that they may each include a cascode transistor structure for providing the same function as illustrated and described in association with fig. 2 and 4.

Referring to fig. 5, the structure of a four transistor-capacitor (4T1C) pixel circuit 500 according to an embodiment will now be described. The 4T1C pixel circuit 500 corresponds, for example, to the single pixel 110a of the display system 150 shown in fig. 1, which in some embodiments is not necessarily a current-biased pixel. The 4T1C pixel circuit 500 shown in fig. 5 is based on NMOS transistors. It should be understood that variations of this pixel and its function are contemplated and include different kinds of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The 4T1C pixel circuit 500 includes a driving transistor 510(T1), a light emitting device 520, a first switching transistor 530(T2), a second switching transistor 540(T3), a third switching transistor 550(T4), and a storage capacitor 560 (C4)_S). The driving transistor 510(T1), the first switching transistor 530, the second switching transistor 540, and the third switching transistor 550 have a first terminal, a second terminal, and a gate terminal, respectively, and the light emitting device 520 and the storage capacitor 560 have a first terminal and a second terminal, respectively.

The gate terminal of the driving transistor 510 is connected to the first terminal of the storage capacitor 560, the first terminal of the driving transistor 510 is connected to the second terminal of the storage capacitor 560, and the second terminal of the driving transistor 510 is connected to the first terminal of the light emitting device. A second terminal of the light emitting device 520 is connected to the first reference potential ELVSS. The capacitance of the light emitting device 520 is shown as C in FIG. 5_LD. In some embodiments, the light emitting device 520 is an OLED. The gate terminal of the first switching transistor 530 is connected to a write signal line (WR), and the first terminal of the first switching transistor 530 is connected to a data signal line (V)_DATA) And a second terminal of the first switching transistor 530 is connected to the gate terminal of the driving transistor 510. The node common to the gate terminal of the drive transistor 510 and the storage capacitor 560 and the first switching transistor 530 is shown with its voltage V_GAnd marking. The gate terminal of the second switching transistor 540 is connected to a read signal line (RD), and the first terminal of the second switching transistor 540 is connected to a monitor signal line (V)_MON) A second terminal of the second switching transistor 540 is connected to a second terminal of the storage capacitor 560. Third openingA gate terminal of the off transistor 550 is connected to an emission signal line (EM), a first terminal of the third switching transistor 550 is connected to the second reference potential ELVDD, and a second terminal of the third switching transistor 550 is connected to a second terminal of the storage capacitor 560. The node common to the second terminal of the storage capacitor 560, the drive transistor 510, the second switching transistor 540, and the third switching transistor 550 is shown by its voltage V_SIndicated.

Referring to fig. 6A, an example of a display timing 600A of the 4T1C pixel circuit 500 shown in fig. 5 is illustrated. The complete display sequence 600A typically occurs once per frame and includes a programming period 602A, a calibration period 604A, a stabilization period 606A, and a light emitting period 608A. At the lapse of time period T_RDDuring the programming period 602A, the read signal (RD) and the write signal (WR) are held low and the emission signal (EM) is held high. The emission signal (EM) is held high during the entire programming, calibration and settling periods 602A-606A to ensure that the third switching transistor 550 is in these periods (T |)_EM) The inner part is kept cut off.

During the programming cycle 602A, both the first switching transistor 530 and the second switching transistor 540 remain on. Storing the voltage of capacitor 560 and thus the voltage V of drive transistor 510_SGIs charged to V_MON－V_DATAA value of (b), wherein V_MONIs monitoring the voltage of the line and V_DATAIs the voltage of the data line. These voltages are set according to a desired programming voltage for causing the pixel 500 to emit light at a desired luminance according to image data.

At the beginning of calibration period 604A, read line (RD) goes high to turn off second switching transistor 540, thereby draining a portion of the voltage (charge) of storage capacitor 560 through drive transistor 510. The amount of draining is a function of the characteristics of the drive transistor 510. For example, if the drive transistor 510 is "strong," then draining occurs relatively quickly, and for a fixed duration T of the calibration period 604A_IPCRelatively more charge is drained from the storage capacitor 560 via the drive transistor 510. On the other hand, if the drive transistor 510 is "weak," draining occurs relatively slowly and relatively during the calibration period 604ALess charge is drained from the storage capacitor 560 via the drive transistor 510. Thus, for a relatively strong drive transistor, the voltage (charge) stored in the storage capacitor 560 is reduced relatively more; conversely, for relatively weak drive transistors, the voltage (charge) stored in the storage capacitor 560 is reduced relatively less, thereby providing some compensation for non-uniformity and variability of the drive transistors throughout the display, whether due to differences in manufacturing or differences in degradation over time.

After the calibration period 604A, a stabilization period 606A is performed before transmission. During the stabilization period 606A, the second and third switching transistors 540, 550 remain off, while the WR signal goes high to turn off the first switching transistor 530 as well. After the end of the duration of the stabilization period 606A, at the beginning of the light emitting period 608A, the emission signal (EM) goes low to turn on the third switching transistor 550, enabling current to flow through the light emitting device 520 according to the calibrated storage voltage in the storage capacitor 560.

An example of a measurement timing 600B of the 4T1C pixel circuit 500 in fig. 5 is now described with reference to fig. 6B. The complete measurement timing 600B generally occurs within the same period as the display frame and includes a programming cycle 602B, a calibration cycle 604B, a stabilization cycle 606B, and a measurement cycle 610B. The programming cycle 602B, calibration cycle 604B, and stabilization cycle 606B are substantially the same as described above in connection with FIG. 6A, however, are V_DATA、V_MONThe amount of voltage set and stored in the storage capacitor 560 is determined for the purpose of measuring the pixel circuit 500, and not for displaying any particular brightness according to image data.

Once the programming cycle 602B, calibration cycle 604B, and stabilization cycle 606B are completed, there is a duration T_MSThe measurement period 610B begins. At the beginning of the measurement period 610B, the emission signal (EM) goes high to turn off the third switching transistor 550 while the read signal (RD) goes low to turn on the second switching transistor 540, thereby providing a read of the monitor line.

To measure the drive transistor 510, a programming cycle 602B and a calibration cycle 604B will be used to drive the crystalProgramming voltage V of tube 510_SGSet to a desired level, and then for a duration T of a measurement period 610B_MSIn the inner, in the monitoring line V_MONAnd current/charge is observed. To measure the voltage V on the drive transistor 510, the voltage on the monitor line is monitored_MONRemains at a sufficiently high level to operate the drive transistor 510 in saturation mode.

To measure the light emitting device 520, a programming voltage V for driving the transistor 510 is applied through a programming period 602B and a calibration period 604B_SGSet to the data line V_DATAThe highest possible voltage (e.g., a value corresponding to a peak white gray scale) that can be obtained, thereby operating the driving transistor 510 in the triode region (switching mode). In this state, the duration T of the measurement period 610B_MSIn addition, the voltage/current of the light emitting device 520 can be directly modulated/measured through the monitoring line.

Referring to fig. 7, the structure of a six-transistor one-capacitor (6T1C) pixel circuit 700 according to an embodiment will now be described. The pixel circuit 700 of 6T1C, for example, corresponds to a single pixel 110a of the display system 150 of fig. 1, which in some embodiments is not necessarily a current-biased pixel. The pixel circuit 700 of 6T1C in fig. 7 is based on NMOS transistors. It should be understood that variations of this pixel and its function are contemplated and include different kinds of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The 6T1C pixel circuit 700 includes a drive transistor 710(T1), a light emitting device 720, a storage capacitor 730 (C)_S) A first switching transistor 740(T2), a second switching transistor 750(T3), a third switching transistor 760(T4), a fourth switching transistor 770(T5), and a fifth switching transistor 780 (T6). The driving transistor 710(T1), the first switching transistor 740, the second switching transistor 750, the third switching transistor 760, the fourth switching transistor 770, and the fifth switching transistor 780 have a first terminal, a second terminal, and a gate terminal, respectively, and the light emitting device 720 and the storage capacitor 730 have a first terminal and a second terminal, respectively.

The gate terminal of the drive transistor 710 is connected to a first terminal of a storage capacitor 730, the drive transistorA first terminal of the driving transistor 710 is connected to the first reference potential ELVDD, and a second terminal of the driving transistor 710 is connected to a first terminal of the third switching transistor 760. A gate terminal of the third switching transistor 760 is connected to a read signal line (RD) and a second terminal of the third switching transistor 760 is connected to a monitor/reference current line V_MON/I_REF. A gate terminal of the fourth switching transistor 770 is connected to an emission signal line (EM), a first terminal of the fourth switching transistor 770 is connected to a first terminal of the third switching transistor 760, and a second terminal of the fourth switching transistor 770 is connected to a first terminal of the light emitting device 720. A second terminal of the light emitting device 720 is connected to the second reference potential ELVSS. The capacitance of the light emitting device 720 is illustrated as C in FIG. 7_LD. In some embodiments, the light emitting device 720 is an OLED. A gate terminal of the first switching transistor 740 is connected to a write signal line (WR), a first terminal of the first switching transistor 740 is connected to a first terminal of the storage capacitor 730, and a second terminal of the first switching transistor 740 is connected to a first terminal of the third switching transistor 760. The gate terminal of the second switching transistor 750 is connected to a write signal line (WR), and the first terminal of the second switching transistor 750 is connected to a data signal line (V)_DATA) And a second terminal of the second switching transistor 750 is connected to a second terminal of the storage capacitor 730. The node common to the gate terminal of the drive transistor 710 and the storage capacitor 730 and the first switching transistor 740 is shown at its voltage V_GAnd marking. A gate terminal of the fifth switching transistor 780 is connected to the emission signal line (EM), a first terminal of the fifth switching transistor 780 is connected to the reference potential VBP, and a second terminal of the fifth switching transistor 780 is connected to the second terminal of the storage capacitor 730. The node common to the second terminal of the storage capacitor 730, the second switching transistor 750 and the fifth switching transistor 780 is used in FIG. 7 by its voltage V_CBAnd marking.

An example of a display timing 800A of the 6T1C pixel circuit 700 shown in fig. 7 is now described with reference to fig. 8A. The full display sequence 800A typically occurs once per frame and includes a programming period 802A, a calibration period 804A, a settling period 806A, and a lighting period 808A. At the lapse of time period T_RD A programming cycle 802A ofDuring this time, the read signal (RD) and the write signal (WR) are kept low and the emission signal (EM) is kept high. The emission signal (EM) is held high throughout the programming, calibration and settling periods 802A, 804A and 806A to ensure that the fourth switching transistor 770 and the fifth switching transistor 780 are on during these periods (T)_EM) The inner part is kept cut off.

During the programming period 802A, the first switch transistor 740, the second switch transistor 750, and the third switch transistor 760 are all kept on. The voltage of the storage capacitor 730 is charged to the following value: v_CB-V_G＝V_DATA-(V_DD–V_SG(T1))≈V_DATA–V_DD+V_th(T1) wherein V_DATAIs the voltage on the data line, V_DDIs a voltage of a first reference potential (also referred to as ELVDD), V_SG(T1) is the voltage between the gate terminal and the first terminal of the drive transistor 710, V_th(T1) is the threshold voltage of the drive transistor 710. Here, V_DATAIs set in consideration of a desired program voltage for causing the pixel 700 to emit light with a desired luminance according to image data.

At the beginning of calibration period 804A, read line (RD) goes high to turn off third switching transistor 760, thereby draining a portion of the voltage (charge) of storage capacitor 730 through drive transistor 710. The amount of draining is a function of the characteristics of the drive transistor 710. For example, if the drive transistor 710 is "strong," then draining occurs relatively quickly, and for a fixed duration T of the calibration period 804A_IPCRelatively more charge is drained from the storage capacitor 730 via the drive transistor 710. On the other hand, if the drive transistor 710 is "weak," draining occurs relatively slowly, and relatively less charge is drained from the storage capacitor 730 via the drive transistor 710 during the calibration period 804A. Thus, for a relatively strong drive transistor, the voltage (charge) stored in the storage capacitor 730 is reduced relatively more; conversely, for relatively weak drive transistors, the voltage (charge) stored in the storage capacitor 730 is reduced relatively less, resulting in non-uniformity and variability (whether by the drive transistor of the entire display)Differences in manufacturing are also a result of differences in degradation over time).

After the calibration period 804A, a stabilization period 806A is performed before the light emitting period 808A. During the settling period 806A, the third, fourth, and fifth switching transistors 760, 770, and 780 remain off, while the write signal (WR) goes high to turn off the first and second switching transistors 740 and 750 as well. After the end of the duration of the stabilization period 806A, at the beginning of the light emitting period 808A, the emission signal (EM) goes low to turn on the fourth and fifth switching transistors 770, 780. This enables the drive transistor 710 to be driven by the voltage V_SG＝V_DD-V_G＝V_DD–(VBP–V_CS)＝V_DD–VBP+V_DATA–V_DD+V_th(T1)＝V_DATA+V_th(T1) -VBP drive. This enables a current to flow through the light emitting device 720 according to the calibrated storage voltage in the storage capacitor 730, and the current is also the threshold voltage V of the driving transistor 710_thA function of (T1) and V_DDIs irrelevant.

An example of a measurement timing 800B of the 6T1C pixel circuit 700 shown in fig. 7 is now described with reference to fig. 8B. The complete measurement timing 800B generally occurs within the same period as the display frame and includes a programming cycle 802B, a calibration cycle 804B, a stabilization cycle 806B, and a measurement cycle 810B. The programming period 802B, calibration period 804B, and stabilization period 806B are substantially the same as described above in connection with FIG. 8A, however, are V_DATA、V_MONThe amount of voltage VBP set and stored in the storage capacitor 730 is determined for the purpose of measuring the pixel circuit 700, and not for displaying any particular brightness according to image data.

Once the programming cycle 802B, calibration cycle 804B, and stabilization cycle 806B are completed, there is a duration T_MSThe measurement period 810B begins. At the beginning of measurement period 810B, the read signal (RD) goes low to turn on the third switching transistor 760, providing a read of the monitor line. The emission signal (EM) remains low and therefore the fourth and fifth switching transistors 770, 780 are measuring for the entire duration T_MSThe internal is kept conductive.

To measure the drive transistor 710, a programming voltage V for the drive transistor 710 is applied through a programming period 802B, a calibration period 804B, and a stabilization period 806B_SGSet to a desired level, and then measure the duration T of the period 810B_MSIn the inner, in the monitoring line V_MONAnd current/charge is observed. To avoid interference from the light emitting device 720, the voltage of the second reference potential (ELVSS) is raised to a sufficiently high level (e.g., to ELVDD).

To measure the light emitting device 720, a programming voltage V for driving the transistor 710 is applied through a programming period 802B, a calibration period 804B, and a stabilization period 806B_SGSet to the data line V_DATAThe lowest possible voltage (e.g., a value corresponding to a black level gray scale) that can be obtained avoids interference from the light emitting device 720.

A diagram of an improved timing 900 for driving rows of pixels, such as the 4T1C and 6T1C pixels described herein, similar to the timing cycle illustrated herein is now described with reference to fig. 9.

For purposes of illustration, the improved timing sequence 900 is shown in association with the application of its four consecutive rows Row # (i-2), Row # (i-1), Row # (i), and Row # (i + 1). The high emission signal EM spans three rows Row # (i +1), Row # (i) and Row # (i-1), the preamble EM token spanning Row Row # (i +1) is connected after the effective EM token spanning Row Row # (i), and the effective EM token spanning Row Row # (i) is connected after the tracking EM token spanning Row Row # (i-1). These are used to ensure a steady state condition for all pixels on a Row during the effective programming time of Row # (i). The start of a valid RD token on Row # (i) tracks the leading EM token, but is aligned with a valid WR token, and corresponds to the simultaneous going low of the RD and WR signals at the beginning of the programming cycle as described in association with other timing diagrams herein. For Row # (i), the valid RD token ends before the end of the valid WR token, which corresponds to a calibration period that enables partial draining of the storage capacitor. Tracking RD token Row # (i-2) is provided with a certain gap after a valid RD token (and once EN is low and the pixel just starts to emit light) to reset the anode of the light emitting device (OLED) and the drain of the drive transistor to a low reference voltage available on the monitor line. This further "reset period" via the monitor line is particularly useful in embodiments such as the 6T1C pixels 700, 1100 of fig. 7 and 11.

The structure of a four transistor-capacitor (4T1C) pixel circuit 1000 operating in current mode according to an embodiment will now be described with reference to fig. 10. The 4T1C pixel circuit 1000 corresponds, for example, to the single pixel 110a of the display system 150 shown in fig. 1. The embodiment shown in fig. 10 is a current biased pixel. An associated bias circuit 1070 for biasing the 4T1C pixel circuit 1000 is illustrated. Bias circuit 1070 biases via a monitor/current bias line (V)_MON/I_REF) To the 4T1C pixel circuit 1000. The 4T1C pixel circuit 1000 shown in fig. 10 is based on NMOS transistors. It should be understood that variations of this pixel and its function are contemplated and include different kinds of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The 4T1C pixel circuit 1000 is substantially identical in structure to the 4T1C pixel circuit 500 shown in fig. 5. The 4T1C pixel circuit 1000 includes a driving transistor 1010(T1), a light emitting device 1020, a first switching transistor 1030(T2), a second switching transistor 1040(T3), a third switching transistor 1050(T4), and a storage capacitor 1060 (C4)_S). The driving transistor 1010(T1), the first switching transistor 1030, the second switching transistor 1040, and the third switching transistor 1050 have a first terminal, a second terminal, and a gate terminal, respectively, and the light emitting device 1020 and the storage capacitor 1060 have a first terminal and a second terminal, respectively.

A gate terminal of the driving transistor 1010 is connected to a first terminal of the storage capacitor 1060, a first terminal of the driving transistor 1010 is connected to a second terminal of the storage capacitor 1060, and a second terminal of the driving transistor 1010 is connected to a first terminal of the light emitting device 1020. A second terminal of the light emitting device 1020 is connected to the first reference potential ELVSS. The capacitance of the light emitting device 1020 is shown as C in FIG. 10_LD. In some embodiments, the light emitting device 1020 is an OLED. A gate terminal of the first switching transistor 1030 is connected to a write signal line (WR), and a first terminal of the first switching transistor 1030 is connected to a data signal line (WR)Number line (V)_DATA) And a second terminal of the first switching transistor 1030 is connected to the gate terminal of the driving transistor 1010. The node common to the gate terminal of the drive transistor 1010 and the storage capacitor 1060 and the first switching transistor 1030 is shown with its voltage V_GAnd marking. The gate terminal of the second switching transistor 1040 is connected to the read signal line (RD), and the first terminal of the second switching transistor 1040 is connected to the monitor/reference current line (V)_MON/I_REF) A second terminal of the second switching transistor 1040 is connected to a second terminal of the storage capacitor 1060. A gate terminal of the third switching transistor 1050 is connected to an emission signal line (EM), a first terminal of the third switching transistor 1050 is connected to the second reference potential ELVDD, and a second terminal of the third switching transistor 1050 is connected to the second terminal of the storage capacitor 1060. A node common to the second terminal of the storage capacitor 1060, the driving transistor 1010, the second switching transistor 1040, and the third switching transistor 1050 is shown by its voltage V_SIndicated.

Connected to the monitor/reference current line is a bias circuit 1070 that includes a current source 1072 and a reference voltage V_REFThe current source 1072 provides a reference current I for current biasing of the pixel_REFThe reference voltage VREF is selectively connected to the monitor/reference current line via a switch 1074 controlled by a Reset Signal (RST).

The function of the 4T1C pixel circuit 1000 is substantially similar to that described above in connection with the 4T1C pixel circuit 500 of fig. 5. However, the 4T1C pixel circuit 1000 of fig. 10 operates in current mode in conjunction with the bias circuit 1070, the timing of which will be described below in conjunction with fig. 12.

The structure of a six transistor-capacitor (6T1C) pixel circuit 1100 operating in current mode according to an embodiment will now be described with reference to fig. 11. The 6T1C pixel circuit 1100 corresponds, for example, to the single pixel 110a of the display system 150 of fig. 1. The embodiment shown in fig. 11 is a current biased pixel. An associated bias circuit 1190 for biasing the 6T1C pixel circuit 1100 is illustrated. Bias circuit 1190 via monitor/current bias line (V)_MON/I_REF) To the 6T1C pixel circuit 1100. The 6T1C pixel shown in FIG. 11The circuit 1100 is based on NMOS transistors. It should be understood that variations of this pixel and its function are contemplated and include different kinds of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The 6T1C pixel circuit 1100 has substantially the same structure as the 6T1C pixel circuit 700 shown in fig. 7. The 6T1C pixel circuit 1100 includes a driving transistor 1110(T1), a light emitting device 1120, and a storage capacitor 1130 (C)_S) A first switching transistor 1140(T2), a second switching transistor 1150(T3), a third switching transistor 1160(T4), a fourth switching transistor 1170(T5), and a fifth switching transistor 1180 (T6). The driving transistor 1110, the first switching transistor 1140, the second switching transistor 1150, the third switching transistor 1160, the fourth switching transistor 1170, and the fifth switching transistor 1180 have a first terminal, a second terminal, and a gate terminal, respectively, and the light emitting device 1120 and the storage capacitor 1130 have a first terminal and a second terminal, respectively.

A gate terminal of the driving transistor 1110 is connected to a first terminal of the storage capacitor 1130, a first terminal of the driving transistor 1110 is connected to the first reference potential ELVDD, and a second terminal of the driving transistor 1110 is connected to a first terminal of the third switching transistor 1160. A gate terminal of the third switching transistor 1160 is connected to a read signal line (RD) and a second terminal of the third switching transistor 1160 is connected to a monitor/reference current line V_MON/I_REF. A gate terminal of the fourth switching transistor 1170 is connected to an emission signal line (EM), a first terminal of the fourth switching transistor 1170 is connected to a first terminal of the third switching transistor 1160, and a second terminal of the fourth switching transistor 1170 is connected to a first terminal of the light emitting device 1120. A second terminal of the light emitting device 1120 is connected to the second reference potential ELVSS. The capacitance of the light emitting device 1120 is illustrated as C in FIG. 11_LD. In some embodiments, light emitting device 1120 is an OLED. A gate terminal of the first switching transistor 1140 is connected to a write signal line (WR), a first terminal of the first switching transistor 1140 is connected to a first terminal of the storage capacitor 1130, and a second terminal of the first switching transistor 1140 is connected to a first terminal of the third switching transistor 1160. Second switch crystalA gate terminal of the transistor 1150 is connected to a write signal line (WR), and a first terminal of the second switching transistor 1150 is connected to a data signal line (V)_DATA) And a second terminal of the second switching transistor 1150 is connected to a second terminal of the storage capacitor 1130. The node common to the gate terminal of the drive transistor 1110 and the storage capacitor 1130 and the first switching transistor 1140 is shown at its voltage V_GAnd marking. A gate terminal of the fifth switching transistor 1180 is connected to the emission signal line (EM), a first terminal of the fifth switching transistor 1180 is connected to the reference potential VBP, and a second terminal of the fifth switching transistor 1180 is connected to the second terminal of the storage capacitor 1130. The node shared by the second terminal of the storage capacitor 1130, the second switching transistor 1150, and the fifth switching transistor 1180 is used in FIG. 11 for its voltage V_CBAnd marking.

Connected to the monitor/reference current line is a bias circuit 1190, which includes a current sink 1192 and a reference voltage V_REF Current sink 1192 provides a reference current I for current biasing of the pixel_REFThe reference voltage VREF is selectively connected to the monitor/reference current line via a switch 1194 controlled by a Reset Signal (RST).

An example of a display timing 1200 of the 4T1C pixel circuit 1000 shown in fig. 10 and the 6T1C pixel circuit 1100 shown in fig. 11 is now explained with reference to fig. 12. A complete display sequence 1200 typically occurs once per frame and includes a first programming period 1202 and a second programming period 1203, a calibration period 1204, a stabilization period 1206, and a light emitting period 1208. At the lapse of time period T_RSTDuring the first programming period 1202, the Reset Signal (RST), the read signal (RD), and the write signal (WR) are held low and the emission signal (EM) is held high. The emission signal (EM) is for the entire duration T of the entire programming, calibration and settling periods 1202, 1203, 1204 and 1206_EMInner is held high. During the second programming, calibration, stabilization and lighting periods 1203, 1204, 1206 and 1208, the 4T1C pixel circuit 1000 and the 6T1C pixel circuit 1100, in addition to being current biased, function as described above in connection with fig. 5 and 7.

For the 4T1C pixel circuit 1000,during the first programming cycle 1202, the reference voltage V_REFA node common to the storage capacitor 1060, the driving transistor 1010 and the third switching transistor 1050 is connected through a switch 1074 and a second switching transistor 1040 to apply a voltage V_SReset to V_REF. The voltage of the storage capacitor 1060, and in turn the voltage V of the drive transistor 1010_SGIs charged to V_REF-V_DATAA value of (b), wherein V_REFIs the voltage of the monitoring line, V_DATAIs the voltage of the data line. These voltages are set according to a desired programming voltage for causing the pixel 1000 to emit light at a desired luminance according to image data. At the end of the first programming cycle 1202, the reset signal goes high to turn off the switch 1074 and disconnect the monitor/reference current line from the reference voltage V_REF. After the first programming cycle, the reset signal is held high to cause the reference current I_REFThe pixel 1000 can be continuously biased during the second programming period 1203. To achieve the desired level of compensation for threshold and mobility differences, each pixel in a row is referenced to a current I during programming of the pixel (including during the first and second programming periods 1202, 1203)_REFAnd (5) driving.

For the 6T1C pixel circuit 1100, during the first programming cycle 1202, the reference voltage V_REFA node common to the first switching transistor 1140, the driving transistor 1110, the third switching transistor 1160, and the fourth switching transistor 1170 is connected through a switch 1194 and a third switching transistor 1160 to apply a voltage V_DReset to V_REFAnd the first switching transistor 1140, the second switching transistor 1150, and the third switching transistor 1160 are all turned on. Voltage V of storage capacitor 1130_CSIs charged to the following value: v_CB-V_G＝V_DATA-(V_DD–V_SG(T1))≈V_DATA–V_DD+V_th(T1) wherein V_DATAIs the voltage of the data line, V_DDIs a voltage of a first reference potential (also referred to as ELVDD), V_SG(T1) is a voltage between the gate terminal and the first terminal of the driving transistor 1110, and V_th(T1) is the threshold voltage of the driving transistor 1110. Here, V_DATAIs set in consideration of a desired program voltage for causing the pixel 1100 to emit light with a desired luminance according to image data.

At the end of the first programming cycle 1202, the Reset Signal (RST) goes high to turn off the switch 1194 and disconnect the monitor/reference current line from the reference voltage V_REF. After the first programming period 1202, the reset signal remains high to enable the reference current source 1192 to continuously bias the pixel 1100 during the second programming period 1203. To achieve the desired level of compensation for threshold and mobility differences, each pixel in a row is referenced to a current I during programming of the pixel (including during the first and second programming periods 1202, 1203)_REFAnd (5) driving.

At the beginning of calibration period 1204, read line (RD) goes high to turn off third switching transistor 1160, thereby draining a portion of the voltage (charge) of storage capacitor 1130 through drive transistor 1110 and stopping the current bias of bias circuit 1190. The amount of draining is a function of the characteristics of the drive transistor 1110. For example, if the drive transistor 1110 is "strong," draining occurs relatively quickly, and for a fixed duration T of the calibration period 1204_IPCRelatively more charge is drained from the storage capacitor 1130 via the drive transistor 1110. On the other hand, if the drive transistor 1110 is "weak," draining occurs relatively slowly, and relatively less charge is drained from the storage capacitor 1130 via the drive transistor 1110 during the calibration period 1204. Thus, for a relatively strong drive transistor, the voltage (charge) stored in the storage capacitor 1130 is reduced relatively more; conversely, for relatively weak drive transistors, the voltage (charge) stored in the storage capacitor 1130 is reduced relatively less, thereby providing some compensation for non-uniformity and variability of the drive transistors throughout the display, whether due to differences in manufacturing or differences in degradation over time.

After the calibration period 1204, a stabilization period 1206 is performed before a lighting period 1208. During the stabilization period 1206, the third, fourth, and fifth switching transistors 1160, 1170, and 1180 remain off, and the write signal (WR) goes high to turn the first onThe off and second switching transistors 1140, 1150 are also turned off. After the end of the duration of the stabilization period 1206, at the beginning of the light emitting period 1208, the emission signal (EM) goes low to turn on the fourth and fifth switching transistors 1170, 1180. This enables the driving transistor 1110 to be driven by the voltage V_SG＝V_DD-V_G＝V_DD–(VBP–V_CS)＝V_DD–VBP+V_DATA–V_DD+V_th(T1)＝V_DATA+V_th(T1) -VBP drive. This enables a current to flow through the light emitting device 1120 according to the calibrated storage voltage in the storage capacitor 1130, and the current is also the threshold voltage V of the driving transistor 1110_thA function of (T1) and V_DDIs irrelevant.

The structure of the 4T1C reference current sink 1300 of the four transistor one capacitor (4T1C) according to an embodiment is now described with reference to fig. 13. The 4T1C reference current sink 1300 corresponds to, for example, the sink 155 of the display system 150 shown in fig. 1 or the sink 1192 shown in fig. 11. The 4T1C reference current sink 1300 shown in fig. 13 is based on NMOS transistors. It should be understood that variations of this absorber and its function are contemplated and include different kinds of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The 4T1C reference current sink 1300 includes a drive transistor 1310(T1), a first switch transistor 1330(T2), a second switch transistor 1340(T3), a third switch transistor 1350(T4), and a storage capacitor 1360 (C)_S). The driving transistor 1310(T1), the first switching transistor 1330, the second switching transistor 1340, and the third switching transistor 1350 have first, second, and gate terminals, respectively, and the storage capacitor 1360 has first and second terminals, respectively.

A gate terminal of the driving transistor 1310 is connected to a first terminal of the storage capacitor 1360, a first terminal of the driving transistor 1310 is connected to a second terminal of the storage capacitor 1360, and a second terminal of the driving transistor 1310 is connected to the reference potential VBS. The gate terminal of the first switching transistor 1330 is connected to a write signal line (WR), and the first switching transistor 1330 is connected to a data signal line (V)_DATA) And a second terminal of the first switching transistor 1330 is connected to the gate terminal of the driving transistor 1310. The node common to the gate terminal of the drive transistor 1310 and the storage capacitor 1360 and the first switching transistor 1330 is shown with its voltage V_GAnd marking. The gate terminal of the second switching transistor 1340 is connected to a read signal line (RD), and the first terminal of the second switching transistor 1340 is connected to a monitor signal line (V)_MON) A second terminal of the second switch transistor 1340 is connected to a second terminal of the storage capacitor 1360. A gate terminal of the third switching transistor 1350 is connected to an emission signal line (EM), a first terminal of the third switching transistor 1350 is connected to a monitor signal line, and a second terminal of the third switching transistor 1350 is connected to a second terminal of the storage capacitor 1360. The node common to the second terminal of the storage capacitor 1360, the driving transistor 1310, the second switching transistor 1340, and the third switching transistor 1350 is shown by its voltage V_SIndicated.

The function of the 4T1C reference current sink 1300 will be explained in conjunction with the timing diagram of fig. 17 discussed below.

The structure of a six transistor-capacitor (6T1C) reference current sink 1400 according to an embodiment is now described with reference to fig. 14. The 6T1C reference current sink 1400 corresponds, for example, to the sink 155a of the display system 150 of fig. 1 or the sink 1192 shown in fig. 11. The 6T1C reference current sink 1400 shown in fig. 14 is based on NMOS transistors. It should be understood that variations of this absorber and its function are contemplated and include different kinds of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The 6T1C reference current sink 1400 includes a drive transistor 1410(T1), a storage capacitor 1430 (C)_S) A first switching transistor 1440(T2), a second switching transistor 1450(T3), a third switching transistor 1460(T4), a fourth switching transistor 1470(T5), and a fifth switching transistor 1480 (T6). The driving transistor 1410, the first switching transistor 1440, the second switching transistor 1450, the third switching transistor 1460, the fourth switching transistor 1470, and the fifth switching transistor 1480 respectively haveA first terminal, a second terminal, and a gate terminal, and the storage capacitor 1430 has a first terminal and a second terminal, respectively.

The gate terminal of the driving transistor 1410 is connected to a first terminal of the storage capacitor 1430, and the first terminal of the driving transistor 1410 is connected to a monitor/current reference line (V)_MON/I_REF) And a second terminal of the driving transistor 1410 is connected to a first terminal of the third switching transistor 1460. A gate terminal of the third switching transistor 1460 is connected to a read signal line (RD) and a second terminal of the third switching transistor 1460 is connected to VBS. A gate terminal of the fourth switching transistor 1470 is connected to an emission signal line (EM), a first terminal of the fourth switching transistor 1470 is connected to a first terminal of the third switching transistor 1460, and a second terminal of the fourth switching transistor 1470 is connected to a second terminal of the third switching transistor 1460. A gate terminal of the first switching transistor 1440 is connected to a write signal line (WR), a first terminal of the first switching transistor 1440 is connected to a first terminal of the storage capacitor 1430, and a second terminal of the first switching transistor 1440 is connected to a first terminal of the third switching transistor 1460. A gate terminal of the second switching transistor 1450 is connected to a write signal line (WR), and a first terminal of the second switching transistor 1450 is connected to a data signal line (V)_DATA) And a second terminal of the second switching transistor 1450 is connected to a second terminal of the storage capacitor 1430. The node common to the gate terminal of the driving transistor 1410 and the storage capacitor 1430 and the first switching transistor 1440 is shown at its voltage V_GAnd marking. A gate terminal of the fifth switching transistor 1480 is connected to the emission signal line (EM), a first terminal of the fifth switching transistor 1480 is connected to the reference potential VBP, and a second terminal of the fifth switching transistor 1480 is connected to a second terminal of the storage capacitor 1430. The node common to the second terminal of the storage capacitor 1430, the second switching transistor 1450 and the fifth switching transistor 1480 is used in fig. 14 with its voltage V_CBAnd marking.

The function of the 6T1C reference current sink 1400 will be explained in conjunction with the timing diagram of fig. 17 discussed below.

The structure of the reference current source 1500 of four transistors one capacitor (4T1C) according to an embodiment will now be explained with reference to fig. 15. The 4T1C reference current source 1500 corresponds to, for example, the current source 155a of the display system 150 shown in fig. 1 or the current source 1072 shown in fig. 10. The 4T1C reference current source 1500 shown in fig. 15 is based on NMOS transistors. It should be understood that variations of this current source and its function are contemplated and include different kinds of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The 4T1C reference current source 1500 includes a drive transistor 1510(T1), a first switch transistor 1530(T2), a second switch transistor 1540(T3), a third switch transistor 1550(T4), and a storage capacitor 1560 (C4)_S). The driving transistor 1510(T1), the first switching transistor 1530, the second switching transistor 1540, and the third switching transistor 1550 have a first terminal, a second terminal, and a gate terminal, respectively, and the storage capacitors 1560 have a first terminal and a second terminal, respectively.

The gate terminal of the drive transistor 1510 is connected to a first terminal of a storage capacitor 1560, a first terminal of the drive transistor 1510 is connected to a second terminal of the storage capacitor 1560, and a second terminal of the drive transistor 1510 is connected to the monitor/reference current line V_MON/I_REF. A gate terminal of the first switching transistor 1530 is connected to a write signal line (WR), and a first terminal of the first switching transistor 1530 is connected to a data signal line (V)_DATA) And a second terminal of the first switching transistor 1530 is connected to the gate terminal of the driving transistor 1510. The node common to the gate terminal of the drive transistor 1510 and the storage capacitor 1560 and the first switching transistor 1530 is shown with its voltage V_GAnd marking. A gate terminal of the second switching transistor 1540 is connected to the read signal line (RD), a first terminal of the second switching transistor 1540 is connected to the reference potential (ELVDD), and a second terminal of the second switching transistor 1540 is connected to a second terminal of the storage capacitor 1560. A gate terminal of the third switching transistor 1550 is connected to an emission signal line (EM), a first terminal of the third switching transistor 1550 is connected to ELVDD, and a second terminal of the third switching transistor 1550 is connected to a second terminal of the storage capacitor 1560. Second of storage capacitor 1560The node common to the terminal, the driving transistor 1510, the second switching transistor 1540, and the third switching transistor 1550 is shown by its voltage V_SIndicated.

The function of 4T1C reference current source 1500 will be explained in conjunction with the timing diagram of fig. 17 discussed below.

The structure of a six transistor-capacitor (6T1C) reference current source 1600 according to an embodiment will now be described with reference to fig. 16. The 6T1C reference current source 1600 corresponds, for example, to the source 155a of the display system 150 shown in fig. 1 or the source 1072 shown in fig. 10. The 6T1C reference current source 1600 shown in fig. 16 is based on NMOS transistors. It should be understood that variations of this source and its function are contemplated and include different kinds of transistors (PMOS, NMOS, or CMOS) and different semiconductor materials (e.g., LTPS, metal oxide, etc.).

The 6T1C reference current source 1600 includes a drive transistor 1610(T1), a storage capacitor 1630 (C)_S) A first switch transistor 1640(T2), a second switch transistor 1650(T3), a third switch transistor 1660(T4), a fourth switch transistor 1670(T5), and a fifth switch transistor 1680 (T6). The driving transistor 1610, the first switching transistor 1640, the second switching transistor 1650, the third switching transistor 1660, the fourth switching transistor 1670, and the fifth switching transistor 1680 have a first terminal, a second terminal, and a gate terminal, respectively, and the storage capacitor 1630 has a first terminal and a second terminal, respectively.

A gate terminal of the driving transistor 1610 is connected to a first terminal of the storage capacitor 1630, a first terminal of the driving transistor 1610 is connected to a reference potential (ELVSS), and a second terminal of the driving transistor 1610 is connected to a first terminal of the third switching transistor 1660. A gate terminal of the third switching transistor 1660 is connected to a read signal line (RD) and a second terminal of the third switching transistor 1660 is connected to a monitor/reference current line (V)_MON/I_REF). A gate terminal of the fourth switching transistor 1670 is connected to the emission signal line (EM), a first terminal of the fourth switching transistor 1670 is connected to a first terminal of the third switching transistor 1660, and a second terminal of the fourth switching transistor 1670 is connected to a second terminal of the third switching transistor 1660. First switchA gate terminal of the transistor 1640 is connected to a write signal line (WR), a first terminal of the first switching transistor 1640 is connected to a first terminal of the storage capacitor 1630, and a second terminal of the first switching transistor 1640 is connected to a first terminal of the third switching transistor 1660. A gate terminal of the second switching transistor 1650 is connected to a write signal line (WR), and a first terminal of the second switching transistor 1650 is connected to a data signal line (V)_DATA) And a second terminal of the second switching transistor 1650 is connected to a second terminal of the storage capacitor 1630. The node common to the gate terminal of the drive transistor 1610 and the storage capacitor 1630 and the first switching transistor 1640 is shown at its voltage V_GAnd marking. A gate terminal of the fifth switching transistor 1680 is connected to the emission signal line (EM), a first terminal of the fifth switching transistor 1680 is connected to the reference potential VBP, and a second terminal of the fifth switching transistor 1680 is connected to the second terminal of the storage capacitor 1630. The node common to the second terminal of the storage capacitor 1630, the second switching transistor 1650, and the fifth switching transistor 1680 is used in fig. 16 for its voltage V_CBAnd marking.

The function of the 6T1C reference current source 1600 will be explained in conjunction with the timing diagram of fig. 17 discussed below.

Examples of reference row timing 1700 for the 4T1C reference current sink 1300 shown in fig. 13, the 6T1C reference current sink 1400 shown in fig. 14, the 4T1C reference current source 1500 shown in fig. 15, and the 6T1C reference current source 1600 shown in fig. 16 will now be described with reference to fig. 17. All of these current sinks and sources 1300, 1400, 1500 and 1600 use the same control signals (EM, WR, RD) and similar timing as the active rows, which makes them convenient for integration in the display panel, e.g. in the first or last row of the display panel. It should be noted that since the pixel circuits that are current biased during programming use as their inputs the bias current provided by the current source (or current sink), and since these sources or sinks have been programmed, appropriate delays or synchronization is used to ensure that programming of these sources and sinks occurs when the bias current is not required by the pixel, and to ensure that the bias current is provided when the pixel requires it.

The full display timing 1700 typically occurs once per frame and includes a programming period 1702, a calibration period 1704, a stabilization period 1706, and a lighting period 1708. At the lapse of time period T_RSTDuring the first programming period 1702, the read signal (RD) and the write signal (WR) are held low and the emission signal (EM) is held high. The emission signal (EM) is for the entire duration T of the entire programming, calibration and settling periods 1702, 1704 and 1706_EMInner is held high.

For the 4T1C reference current sink 1300 shown in fig. 13, during the programming period 1702, both the first switching transistor 1330 and the second switching transistor 1340 are turned on. Storing the voltage of the capacitor 1360 and thus the voltage V of the drive transistor 1310_SGIs charged to V_MON-V_DATAA value of (b), wherein V_MONIs the voltage of the monitoring line, V_DATAIs the voltage of the data line. These voltages are set according to a desired programming voltage for causing the pixel 1300 to emit light at a desired brightness according to image data.

At the beginning of calibration period 1704, read line (RD) goes high to turn off second switch transistor 1340, thereby draining a portion of the voltage (charge) of storage capacitor 1360 through drive transistor 1310. The amount of draining is a function of the characteristics of the drive transistor 1310. For example, if the drive transistor 1310 is "strong," then draining occurs relatively quickly, and for a fixed duration T of the calibration period 1704_IPCRelatively more charge is drained from the storage capacitor 1360 via the drive transistor 1310. On the other hand, if the drive transistor 1310 is "weak," draining occurs relatively slowly, and relatively less charge drains from the storage capacitor 1360 via the drive transistor 1310 during the calibration period 1704. Thus, for a relatively strong drive transistor, the voltage (charge) stored in the storage capacitor 1360 is reduced relatively more; conversely, for relatively weak drive transistors, the voltage (charge) stored in the storage capacitor 1360 is reduced relatively less, thereby providing some compensation for non-uniformity and variability in the reference current provided for the entire display, whether due to variations in manufacturing or variations in degradation over time.

After the calibration period 1704, a stabilization period 1706 occurs before transmission. During the stabilization period 1706, the second and third switching transistors 1340, 1350 remain off, while the write signal (WR) goes high to turn off the first switching transistor 1330 as well. After the end of the duration of the stabilization period 1706, at the beginning of the light emission period 1708, the emission signal (EM) goes low to turn on the third switching transistor 1350, which causes the reference current I_REFCan be provided to the monitor/reference current line according to the calibrated storage voltage in the storage capacitor 1360.

For the 6T1C reference current sink 1400 shown in fig. 14, during the programming period 1702, the first switching transistor 1440, the second switching transistor 1450, and the third switching transistor 1460 are all turned on. Voltage V of storage capacitor 1430_CSIs charged to the following value: v_CB-V_G＝V_DATA-(V_MON–V_SG(T1))≈V_DATA–V_MON+V_th(T1) wherein V_DATAIs the voltage of the data line, V_MONIs the voltage, V, of the monitor/reference current line_SG(T1) is a voltage between the gate terminal and the first terminal of the driving transistor 1410, and V_th(T1) is the threshold voltage of the driving transistor 1410. Here, V_DATAIs set in consideration of a desired programming voltage for causing reference current sink 1400 to generate a desired level of reference current.

At the beginning of calibration period 1704, read line (RD) goes high to turn off third switching transistor 1460, thereby draining a portion of the voltage (charge) of storage capacitor 1430 through drive transistor 1410. The amount of draining is a function of the characteristics of the drive transistor 1410. For example, if the drive transistor 1410 is "strong," then draining occurs relatively quickly, and for a fixed duration T of the calibration period 1704_IPCRelatively more charge is drained from the storage capacitor 1430 via the drive transistor 1410. On the other hand, if the drive transistor 1410 is "weak," draining occurs relatively slowly, and relatively less charge drains from the storage capacitor 1430 via the drive transistor 1410 during the calibration period 1704. Thus, theFor a relatively strong drive transistor, the voltage (charge) stored in the storage capacitor 1430 is reduced relatively more; conversely, for relatively weak drive transistors, the voltage (charge) stored in the storage capacitor 1430 is reduced relatively less, providing some compensation for non-uniformity and variability of the current sink 1400 across the display (whether due to differences in manufacturing or differences in degradation over time).

After the calibration period 1704, a stabilization period 1706 occurs before the illumination period 1708. During the stabilization period 1706, the third, fourth, and fifth switching transistors 1460, 1470, and 1480 remain off, while the write signal (WR) goes high to turn off the first and second switching transistors 1440, 1450 as well. After the duration of the stabilization period 1706 is over, at the beginning of the light emission period 1708, the emission signal (EM) goes low to turn on the fourth and fifth switching transistors 1470, 1480. This enables the driving transistor 1410 to be driven by the voltage V_SG＝V_MON-V_G＝V_MON–(VBP–V_CS)＝V_MON–VBP+V_DATA–V_MON+V_th(T1)＝V_DATA+V_th(T1) -VBP drive. This results in a reference current I_REFCan be supplied to the monitor/reference current line according to the calibrated storage voltage in the storage capacitor 1430, and the reference current is also the threshold voltage V of the drive transistor 1410_thA function of (T1) and V_MONIndependently of V, also_DDIs irrelevant.

For the 4T1C reference current source 1500 shown in fig. 15, during the programming cycle 1702, both the first switching transistor 1530 and the second switching transistor 1540 are turned on. The voltage of the storage capacitor 1560 and thus the voltage V of the drive transistor 1510_SGIs charged to V_DD-V_DATAA value of (b), wherein V_DDIs the voltage, V, of the reference potential line ELVDD_DATAIs the voltage of the data line. At least one of these voltages is set according to a desired programming voltage for causing the reference current source 1500 to generate a desired level of reference current.

At the beginning of calibration period 1704, read line (RD) changesTo be high to turn off the second switching transistor 1540, thereby draining a part of the voltage (charge) of the storage capacitor 1560 through the driving transistor 1510. The amount of draining is a function of the characteristics of the drive transistor 1510. For example, if the drive transistor 1510 is "strong," then draining occurs relatively quickly, and for a fixed duration T of the calibration period 1704_IPCRelatively more charge is drained from the storage capacitor 1560 via the drive transistor 1510. On the other hand, if the drive transistor 1510 is "weak," draining occurs relatively slowly, and relatively less charge drains from the storage capacitor 1560 via the drive transistor 1510 during the calibration period 1704. Thus, for a relatively strong drive transistor, the voltage (charge) stored in the storage capacitor 1560 is reduced relatively more; conversely, for relatively weak drive transistors, the voltage (charge) stored in the storage capacitor 1560 is reduced relatively less, thereby providing some compensation for non-uniformity and variability in the reference current provided for the entire display, whether due to variations in manufacturing or variations in degradation over time.

After the calibration period 1704, a stabilization period 1706 is performed before the lighting period. During the stabilization period 1706, the second and third switching transistors 1540 and 1550 remain off, and the write signal (WR) becomes high to turn off the first switching transistor 1530 as well. After the end of the duration of the stabilization period 1706, at the beginning of the light emission period 1708, the emission signal (EM) becomes low to turn on the third switching transistor 1550, which causes the reference current I_REFCan be provided to the monitor/reference current line according to the calibrated storage voltage in storage capacitor 1560.

For the 6T1C reference current source 1600 shown in fig. 16, during the programming cycle 1702, the first switch transistor 1640, the second switch transistor 1650 and the third switch transistor 1660 are all turned on. Voltage V of storage capacitor 1630_CSIs charged to the following value: v_CB-V_G＝V_DATA-(V_DD–V_SG(T1))≈V_DATA–V_DD+V_th(T1) wherein V_DATAIs the voltage of the data line, V_DDIs the reference potential ELVDDVoltage of V_SG(T1) is the voltage between the gate terminal and the first terminal of the drive transistor 1610, and V_th(T1) is the threshold voltage of the driving transistor 1610. Here, V_DATAIs set in consideration of a desired program voltage for causing the reference current source 1600 to generate a desired level of reference current.

At the beginning of calibration period 1704, read line (RD) goes high to turn off third switching transistor 1660, thereby draining a portion of the voltage (charge) of storage capacitor 1630 through drive transistor 1610. The amount of draining is a function of the characteristics of the drive transistor 1610. For example, if the drive transistor 1610 is "strong," draining occurs relatively quickly and for a fixed duration T of the calibration period 1704_IPCRelatively more charge is drained from the storage capacitor 1630 via the drive transistor 1610. On the other hand, if the drive transistor 1610 is "weak," draining occurs relatively slowly and relatively less charge drains from the storage capacitor 1630 via the drive transistor 1610 during the calibration period 1704. Thus, for a relatively strong drive transistor, the voltage (charge) stored in the storage capacitor 1630 is reduced relatively more; conversely, for a relatively weak drive transistor, the voltage (charge) stored in the storage capacitor 1630 is reduced relatively less, thereby providing some compensation for non-uniformity and variability of the current source 1600 across the display (whether due to differences in manufacturing or differences in degradation over time).

After the calibration period 1704, a stabilization period 1706 occurs before the illumination period 1708. During the stabilization period 1706, the third, fourth, and fifth switch transistors 1660, 1670, and 1680 remain off, and the write signal (WR) goes high to turn off the first and second switch transistors 1640, 1650 as well. After the end of the duration of the stabilization period 1706, at the beginning of the light emission period 1708, the emission signal (EM) goes low to turn on the fourth and fifth switching transistors 1670, 1680. This enables the driving transistor 1610 to be driven by the voltage V_SG＝V_DD-V_G＝V_DD–(VBP–V_CS)＝V_DD–VBP+V_DATA–V_DD+V_th(T1)＝V_DATA+V_th(T1) -VBP drive. This results in a reference current I_REFCan be provided to the monitor/reference current line according to the calibrated storage voltage in the storage capacitor 1630, and the reference current is also the threshold voltage V of the drive transistor 1610_thA function of (T1) and V_DDIs irrelevant.

Referring to FIG. 18, on-panel multiplexing of data and monitoring lines will now be discussed. A driver chip (not shown) provides drive signals via data/monitor lines DM _ R, DM _ G and DM _ B for, for example, a column of red, green, and blue pixels. Each of these lines is connected to a separate corresponding data line and monitor line via two switches. For example, DM _ R is connected to Data _ R and Mon _ R for the red subpixel, DM _ G is connected to Data _ G and Mon _ G for the green subpixel, and DM _ B is connected to Data _ B and Mon _ B for the blue subpixel. The switches on the Data _ X and Mon _ X lines used to de-multiplex the DM _ X signals are controlled by a Data Enable (DEN) signal line (corresponding to the WR signal described herein) and a Monitor Enable (MEN) signal line (corresponding to the RD signal described herein), respectively. Each monitor line is connected to a separate reference voltage via an additional switch. For example, MON _ R is connected to VrefR, MON _ G is connected to VrefG, and MON _ B is connected to VrefB. These respective additional switches connecting the monitor lines to respective reference voltages are controlled by a Reset Enable (REN) signal line (corresponding to the RST signal described herein). Multiplexing provides a reduction in the I/O count of the driver chip (not shown).

While particular embodiments and applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and compositions disclosed herein and that various changes, modifications and variations may be apparent from the foregoing descriptions without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A system for generating a current for a pixel of an emissive display system, each pixel having a light emitting device, the system comprising:

a plurality of pixels;

a plurality of current generating circuits for supplying a current to at least one corresponding one of the pixels; and

a controller connected to the current generation circuit and for controlling the current generation circuit via a plurality of signal lines;

wherein each of the current generation circuits includes:

at least one drive transistor for providing the pixel with the current; and

a storage capacitor for being programmed and for setting a magnitude of the current provided by the at least one drive transistor;

wherein the control of each of the current generation circuits by the controller includes:

charging the storage capacitor to a defined level during a programming cycle; and

after the programming period, partially discharging the storage capacitor as a function of the characteristics of the at least one drive transistor during a calibration period.

2. The system of claim 1, wherein the at least one drive transistor comprises one drive transistor, and the control of each of the current generating circuits by the controller further comprises:

charging the storage capacitor connected to the gate terminal of the drive transistor during the programming period to contain at least a threshold voltage of the drive transistor such that during a lighting period a voltage between a source terminal and a drain terminal during the lighting period is a function of the threshold voltage of the drive transistor.

3. The system of claim 1, wherein the at least one drive transistor comprises one drive transistor, and the control of each of the current generating circuits by the controller further comprises:

charging the storage capacitor connected to the gate terminal of the drive transistor during the programming period to include at least a first voltage applied to the source terminal of the drive transistor such that the voltage between the source and drain terminals is independent of the first voltage during a light emission period in which the first voltage is maintained at the source terminal of the drive transistor.

4. The system of claim 3, wherein the first voltage is V_DDAnd V_MONOne of them.

5. The system of claim 1, wherein each of the current generation circuits comprises one of a reference current sink and a reference current source for providing the current for the at least one respective pixel, the current being used to provide a reference current bias for the at least one respective pixel.

6. The system of claim 1, wherein each of the pixels includes the current generation circuit for providing the pixel with the current for driving the light emitting device of the pixel.

7. The system of claim 6, wherein the light emitting device is an Organic Light Emitting Diode (OLED).

8. The system of claim 7, wherein the control of each of the current generating circuits by the controller further comprises:

resetting at least one of an anode of the OLED and a terminal of the at least one driving transistor to a low reference voltage during a reset period that begins substantially simultaneously with a light emitting period.

9. A method of generating a current for a pixel of an emissive display system, each pixel having a light emitting device, the system comprising a plurality of pixels; a plurality of current generating circuits for providing a current to at least one respective said pixel, each said current generating circuit comprising at least one drive transistor for providing said current to said pixel and a storage capacitor for being programmed and for setting the magnitude of said current provided by said at least one drive transistor, said method comprising:

controlling each of the current generation circuits via a plurality of lines, the controlling comprising:

charging the storage capacitor to a defined level during a programming cycle; and

after the programming period, partially discharging the storage capacitor as a function of the characteristics of the at least one drive transistor during a calibration period.

10. The method of claim 9, wherein the at least one drive transistor comprises one drive transistor, and controlling each of the current generating circuits further comprises:

charging the storage capacitor connected to the gate terminal of the drive transistor during the programming period to contain at least a threshold voltage of the drive transistor such that a voltage between the source terminal and the drain terminal is a function of the threshold voltage of the drive transistor during a lighting period.

11. The method of claim 9, wherein the at least one drive transistor comprises one drive transistor, and the controlling of each of the current generating circuits further comprises:

charging the storage capacitor connected to the gate terminal of the drive transistor during the programming period to include at least a first voltage applied to the source terminal of the drive transistor such that the voltage between the source terminal and the drain terminal is independent of the first voltage during a light emission period in which the first voltage is maintained at the source terminal of the drive transistor.

12. The method of claim 11, wherein the first voltage is V_DDAnd V_MONOne of them.

13. The method of claim 9, wherein each of the current generation circuits includes one of a reference current sink and a reference current source for providing the current for the at least one respective pixel, the current being used to provide a reference current bias for the at least one respective pixel.

14. The method of claim 9, wherein each of the pixels includes the current generating circuit for providing the pixel with the current for driving the light emitting device of the pixel.

15. The method of claim 14, wherein the light emitting device is an Organic Light Emitting Diode (OLED).

16. The method of claim 15, wherein controlling each of the current generating circuits further comprises:

resetting at least one of an anode of the OLED and a terminal of the at least one driving transistor to a low reference voltage during a reset period starting at substantially the same time as a light emitting period.

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