CN108153705A - A kind of efficient parallel acquisition method towards isomerous multi-source big data - Google Patents
A kind of efficient parallel acquisition method towards isomerous multi-source big data Download PDFInfo
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- CN108153705A CN108153705A CN201711428068.XA CN201711428068A CN108153705A CN 108153705 A CN108153705 A CN 108153705A CN 201711428068 A CN201711428068 A CN 201711428068A CN 108153705 A CN108153705 A CN 108153705A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
Abstract
The invention discloses a kind of efficient parallel acquisition method towards isomerous multi-source big data, this method is realized using 7000 SoC chips of ZYNQ of Xilinx companies, including：Design the isomerous multi-source big data acquisition module based on FPGA, and it is mounted in piece in AXI buses, the acquisition module includes a static zones and multiple dynamic areas, the realization of AXI bus protocols and the data interaction with multiple dynamic areas in piece are responsible in wherein static zones, and each dynamic area is according to the external interface and logic function of the different designs independence for the device protocol to be acquired；The Memory Allocation of isomerous multi-source big data acquisition module and dynamic restructuring module distribute different memories for each dynamic area, reconstituted state machine are realized in ARM cores, and pass through the dynamic restructuring of the memory initial address completion dynamic area of PCAP ports and each dynamic area.Realize the live different agreement of manufacture, the efficient parallel acquisition of mass data of distinct device is the key that realize intelligence manufacture, the present invention can realize the efficient parallel acquisition of isomerous multi-source big data.
Description
Technical field
The invention belongs to electronic engineering and computer science, and in particular to a kind of height towards isomerous multi-source big data
Imitate parallel acquisition method.
Background technology
With the proposition of national strategy " made in China 2025 ", intelligence manufacture has become the hot spot noun of contemporary China.But
It is to realize that intelligence manufacture be unable to do without data, these data more specifically show as the data at manufacture scene, but manufacture scene
Equipment is different, and hardware interface and communications protocol also have very big difference, if for each equipment, each interface and every
If a kind of agreement all designs a dedicated data collector, not only increase cost, but also the data collector of broad categories
Also the placement-and-routing for necessarily causing manufacture scene is numerous and diverse, directly affects collecting efficiency and causes security risk.It is achieved that manufacture
The highly effective gathering of live isomerous multi-source data, which can speed up, realizes that China becomes manufacturing power, to realize the highly effective gathering of data
It just needs to realize the unified acquisition of heterogeneous device, isomery interface and heterogeneous protocol data, realize data acquisition equipment and is adopted pair
Original " one-to-one " framework arrives the transformation of " one-to-many " framework as between, while there is the big spies of amount for isomerous multi-source data
Point, manufacture scene is there is the very harsh occasion of the requirement of real-time acquired to data, such as the state of producing line, the position of lathe milling cutter
It puts, in order to improve the real-time of data acquisition, the parallel acquisition of data is a kind of effectively method.
SoC (System on Chip, system on chip) is a kind of system-level microprocessor, be generally integrated with including
The processors such as FPGA, ARM, Microblaze, DSP, FPGA have the hardware concurrent characteristic of height, also have other processors not
The dynamic restructuring characteristic having, ARM can transplant embedded system, can carry out system-level processing.It is more in FPGA internal builds
A dynamic area, each dynamic area are independently responsible for the data acquisition of distinct interface, different agreement, and the dynamic weight for passing through dynamic area
Structure (or in limited resources) acquisition can need the data that many embedded microprocessors could acquire in the past on one piece of FPGA,
And these dynamic areas are independent of one another, are achieved that the efficient parallel acquisition of data；In addition the dynamic dispatching of ARM, realization pair
The control of FPGA dynamic restructurings just constitutes the efficient parallel acquisition scheme of an isomerous multi-source big data.Therefore, the present invention carries
Go out a kind of efficient parallel acquisition method towards isomerous multi-source big data, this method can realize isomerous multi-source data it is efficient simultaneously
Row acquisition.
Invention content
The technical problem to be solved in the present invention is：A kind of efficient parallel acquisition side towards isomerous multi-source big data is provided
Method, this method can realize the efficient parallel acquisition to heterogeneous device, isomery interface and heterogeneous protocol data.
The present invention solves its technical problem and following technical scheme is taken to realize：It is a kind of towards isomerous multi-source big data
Efficient parallel acquisition method, includes the following steps：
Step 1：The isomerous multi-source big data acquisition module based on FPGA is designed, and is mounted in piece in AXI buses, it should
Isomerous multi-source big data acquisition module based on FPGA includes a FPGA static zones and multiple FPGA dynamic areas, wherein FPGA are quiet
It is responsible for the realization of AXI bus protocols and the data interaction with multiple FPGA dynamic areas, multiple FPGA dynamic areas in piece and passes through in state area
Dynamic restructuring completes the acquisition of isomerous multi-source big data, is implemented as follows：
1. establishing multiple FPGA dynamic areas, each dynamic area is according to pair of the different designs independence for the data protocol to be acquired
External tapping and logic function, the external interface of FPGA static zones and the external interface formation of all dynamic areas map one by one, simultaneously
FPGA static zones provide unified driving clock signal for all dynamic areas；
2. the data interaction between each dynamic area is completed in FPGA static zones, and passes through the data with AXI buses in piece
The data interaction with ARM cores is realized in interaction.FPGA static zones are mounted to as slave device in piece in AXI buses, in FPGA static state
AXI bus protocols state machine in piece is write in area：The address-bus width for setting AXI buses in piece is 32, data-bus width
It is 32, the device address ranging from hexadecimal 00000000 that setting is mounted in piece in AXI buses arrives hexadecimal
The Read-write Catrol that enabled and write enable signal is completed with AXI buses interact in piece is read in FFFFFFFF, setting；
Step 2：The Memory Allocation of isomerous multi-source big data acquisition module and dynamic restructuring module are each FPGA dynamics
Area distributes different memories, and ARM cores complete FPGA dynamics by the memory initial address of PCAP ports and each FPGA dynamic areas
The dynamic restructuring in area, is implemented as follows：
1. the Memory Allocation range of each FPGA dynamic areas need to arrive hexadecimal FFFFFFFF in hexadecimal 00000000
Between, different initial addresses is set according to the size of each FPGA dynamic areas, and the memory range of each FPGA dynamic areas is mutual
It is independent；
2. the design reconfiguration state machine in ARM cores will intend the FPGA dynamic areas of reconstruct under the control of reconstituted state machine
Initial address and size write-in PCAP interfaces complete the dynamic restructuring of the FPGA dynamic areas.
A kind of efficient parallel acquisition method towards isomerous multi-source big data that the present invention designs is suitable for Xilinx companies
ZYNQ-7000SoC chips.
The advantages of the present invention over the prior art are that：
(1) by the way that in the multiple dynamic areas of FPGA interior designs, each dynamic area is responsible for acquiring the data of different agreement, dynamic
Between area independently of one another, parallel, a dynamic area can realize different acquisition functions by dynamic restructuring, can be achieved in this way
Data acquisition equipment and the transformation that original " one-to-one " framework between object arrives " one-to-many " framework is adopted, reduce data and acquire
Cost improves collecting efficiency；
(2) the AXI bus protocol state machines in FPGA static zones design piece, enable to each dynamic areas of FPGA to pass through piece
Interior high speed AXI buses are interacted with ARM cores, can be called as slave device by ARM cores, be realized the dynamic restructuring control based on ARM cores
System, and this reconstruct mode is easy to operate, reconstruct is efficient.
Description of the drawings
Fig. 1 is the structure diagram of the present invention；
Fig. 2 is the logic function block diagram of the present invention.
Specific embodiment
Further detailed description is done to the present invention below in conjunction with the accompanying drawings.
The present invention relates to a kind of efficient parallel acquisition method towards isomerous multi-source big data, using Xilinx companies
ZYNQ-7000SoC chips.The equipment for manufacturing scene is different, and hardware interface and communications protocol also have very big difference, this method
For how with a small amount of embedded microprocessor acquisition different agreement, distinct interface, distinct device mass data, and phase
Treat the demand of efficient parallel acquisition, proposition method of the present invention can realize the efficient parallel acquisition of isomerous multi-source big data.
The present invention structure diagram as shown in Figure 1, logic function block diagram as shown in Fig. 2, specific embodiment is as follows：
(1) the isomerous multi-source big data acquisition module 1 based on FPGA in Fig. 1, is implemented as follows：
1. establishing multiple FPGA dynamic areas, each dynamic area is according to pair of the different designs independence for the data protocol to be acquired
External tapping and logic function can be achieved with the parallel acquisition to isomerous multi-source data in this way；The external interface of FPGA static zones with
The external interface formation of all dynamic areas maps one by one, and dynamic area is completed pin by static zones and constrained；FPGA static zones are institute
There is dynamic area to provide unified driving clock signal, ensure that static zones and all dynamic areas are not in across clock in this way
The situation in domain；
2. the data interaction between each dynamic area is completed in FPGA static zones, and passes through the data with AXI buses in piece
The data interaction with ARM cores is realized in interaction.FPGA static zones are mounted to as slave device in piece in AXI buses, in FPGA static state
AXI bus protocols state machine in piece is write in area：The address-bus width for setting AXI buses in piece is 32, data-bus width
It is 32, the device address ranging from hexadecimal 00000000 that setting is mounted in piece in AXI buses arrives hexadecimal
The Read-write Catrol that enabled and write enable signal is completed with AXI buses interact in piece is read in FFFFFFFF, setting.It enables in this way
The each dynamic areas of FPGA are interacted by high speed AXI buses in piece with ARM cores, can be called as slave device by ARM cores, realize base
It is controlled in the dynamic restructuring of ARM cores, and this reconstruct mode is easy to operate, reconstruct is efficient；
(2) Memory Allocation of isomerous multi-source big data acquisition module and dynamic restructuring module 2 in Fig. 1, specific implementation is such as
Under：
1. the Memory Allocation range of each dynamic area need in hexadecimal 00000000 between hexadecimal FFFFFFFF,
Different initial addresses is set according to the size of each dynamic area, and the memory range of each dynamic area is mutual indepedent；
2. the design reconfiguration state machine in ARM cores will intend the starting of the dynamic area of reconstruct under the control of reconstituted state machine
Address and size write-in PCAP interfaces complete the dynamic restructuring of the dynamic area.
In conclusion the invention discloses a kind of efficient parallel acquisition method towards isomerous multi-source big data, including：If
The isomerous multi-source big data acquisition module based on FPGA is counted, and is mounted in piece in AXI buses；Isomerous multi-source big data acquires mould
The Memory Allocation of block and dynamic restructuring module.This method can be realized to heterogeneous device, isomery interface and heterogeneous protocol data
Efficient parallel acquires.
The content not being described in detail in description of the invention belongs to the prior art well known to professional and technical personnel in the field.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (2)
1. a kind of efficient parallel acquisition method towards isomerous multi-source big data, it is characterised in that：Include the following steps：
Step 1：The isomerous multi-source big data acquisition module based on FPGA is designed, and is mounted in piece in AXI buses, this is based on
The isomerous multi-source big data acquisition module of FPGA includes a FPGA static zones and multiple FPGA dynamic areas, wherein FPGA static zones
It is responsible for the realization of AXI bus protocols and the data interaction with multiple FPGA dynamic areas, multiple FPGA dynamic areas in piece and passes through dynamic
The acquisition of isomerous multi-source big data is completed in reconstruct, is implemented as follows：
1. establishing multiple FPGA dynamic areas, each FPGA dynamic areas are according to pair of the different designs independence for the data protocol to be acquired
External tapping and logic function, the external interface of FPGA static zones and the external interface formation of all dynamic areas map one by one, simultaneously
FPGA static zones provide unified driving clock signal for all dynamic areas；
2. the data interaction between each dynamic area is completed in FPGA static zones, and by the data interaction with AXI buses in piece,
Realize the data interaction with ARM cores.FPGA static zones are mounted to as slave device in piece in AXI buses, in FPGA static zones
Write AXI bus protocols state machine in piece：The address-bus width for setting AXI buses in piece is 32, data-bus width 32,
The device address ranging from hexadecimal 00000000 that setting is mounted in piece in AXI buses arrives hexadecimal FFFFFFFF, if
Put the Read-write Catrol for reading that enabled and write enable signal is completed with AXI buses interact in piece；
Step 2：The Memory Allocation of isomerous multi-source big data acquisition module and dynamic restructuring module are that each FPGA dynamics are distinguished
With different memories, ARM cores complete the dynamic restructuring of dynamic area by the memory initial address of PCAP ports and each dynamic area,
It is implemented as follows：
1. the Memory Allocation range of each FPGA dynamic areas need in hexadecimal 00000000 between hexadecimal FFFFFFFF,
Different initial addresses is set according to the size of each FPGA dynamic areas, and the memory range of each FPGA dynamic areas is mutual indepedent；
2. the design reconfiguration state machine in ARM cores will intend the starting of the FPGA dynamic areas of reconstruct under the control of reconstituted state machine
Address and size write-in PCAP interfaces complete the dynamic restructuring of the FPGA dynamic areas.
2. a kind of efficient parallel acquisition method towards isomerous multi-source big data as described in claim 1, it is characterised in that：Institute
The method stated is suitable for Xilinx companies ZYNQ-7000SoC chips.
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| CN109032982A (en) * | 2018-08-02 | 2018-12-18 | 郑州云海信息技术有限公司 | A kind of data processing method, device, equipment, system, FPGA board and combinations thereof |
| CN109803322A (en) * | 2019-01-04 | 2019-05-24 | 烽火通信科技股份有限公司 | A kind of data frame repeater system and method |
| CN110287141A (en) * | 2019-06-27 | 2019-09-27 | 天津津航计算技术研究所 | A kind of FPGA reconstructing method and system based on multiple interfaces |
| CN112214448A (en) * | 2020-10-10 | 2021-01-12 | 中科声龙科技发展（北京）有限公司 | Data dynamic reconstruction circuit and method of heterogeneous integrated workload proving operation chip |
| CN113703848A (en) * | 2021-07-13 | 2021-11-26 | 中国电子科技集团公司第五十三研究所 | Reconfigurable flexible control method based on SoC chip and oriented to bit flipping effect |
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