CN108153669A - The method that application time axis configuration mode realizes FPGA software emulation task schedulings - Google Patents
The method that application time axis configuration mode realizes FPGA software emulation task schedulings Download PDFInfo
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- CN108153669A CN108153669A CN201711225458.7A CN201711225458A CN108153669A CN 108153669 A CN108153669 A CN 108153669A CN 201711225458 A CN201711225458 A CN 201711225458A CN 108153669 A CN108153669 A CN 108153669A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3684—Test management for test design, e.g. generating new test cases
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3676—Test management for coverage analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3688—Test management for test execution, e.g. scheduling of test suites
Abstract
The invention belongs to FPGA Software Simulation Test technical fields, and in particular to a kind of method that application time axis configuration mode realizes FPGA software emulation task schedulings.The present invention realizes FPGA software test cases in a manner of task scheduling, and task scheduling is configured in a manner of task point.Wherein task point is arranged in reference axis, the two-dimensional coordinate axis that the reference axis is made of transversal device and longitudinal time, by using to target each in reference axis in the way of timing requirements configuration task point, realize the systematization of test case and sequentialization operation, and then the capacity of system configuration of FPGA software emulation task schedulings is improved, improve test case batch processing ability.
Description
Technical field
The invention belongs to FPGA Software Simulation Test technical fields, and in particular to a kind of application time axis configuration mode is realized
The method of FPGA software emulation task schedulings.
Background technology
At present when carrying out FPGA Software Simulation Tests, test specification document is write by tester first, which says
Plaintext shelves include whole test cases of FPGA softwares to be measured.Each test case describes test purpose, test input number
According to, testing procedure and it is expected test result.Test case description is as shown in Figure 1.
FPGA Software Simulation Tests need above-mentioned test case being changed into the language that FPGA emulates tool and can identify
Speech performs emulation to be loaded into the tool of emulating.The realization of test case at present is in Code Edit environment, passes through people
Work edit code realizes TESTBENCH files, need to consume a large amount of manpowers and time.The TESTBENCH completed by line by line coding
File, as shown in Figure 2.
The line by line coding realization method of above-mentioned test case is difficult to embody whole test cases with testing the corresponding pass of code
System, and be difficult to the execution to single test case or multiple test cases and implement effective control.Also test can not be clearly shown
Use-case timing is realized, has both influenced testing progress and quality, it is also difficult to realize that the batch of FPGA emulation testings performs, FPGA is imitated
The elevator belt of true measuring technology development and personage's quality level carrys out problem.
Invention content
(1) technical problems to be solved
The technical problem to be solved by the present invention is to：The object of the present invention is to provide a kind of sides for automating generation test and excitation
Method, solves that current cost of labor is big, complicated contradiction is debugged, suitable for the emulation testing of FPGA softwares.
(2) technical solution
In order to solve the above technical problems, the present invention, which provides a kind of application time axis configuration mode, realizes that FPGA software emulations are appointed
The method for being engaged in dispatching, is as follows：
Step 1：By the system architecture of the tested FPGA of analysis, tested FPGA and its peripheral interface device are analyzed, is formed
The two-dimensional coordinate axis achievement of two-dimensional coordinate axis operation with above-mentioned device；
Step 2：On the basis of the two-dimensional coordinate axis achievement obtained by configuration task point module in step 1, further according to
Task point is configured according to the requirement of test case, obtains task point achievement of allocation；
Step 3：On the basis of establishing task point achievement of allocation in the time shaft of each device, task is further carried out
The setting of point, each task point is configured in the requirement according to test case, for the test pair described in test case
As, affiliated partner, test and excitation and sequential, response requirement, determine critical data, and the above-mentioned related content of test case is configured
To the task point in reference axis, and pass through task dot characteristics and describe test case title, obtain task point setting outcome data；
Step 4：On the basis of test case setting task point setting outcome data, whole test cases are further carried out
The configuration of task point, each task point can correspond to test case description explanation and enable control, form task point sequence
Achievement and test case sequence achievement；
Step 5：In task point sequence achievement and test case sequence performance basis, in further being emulated
Single test case may be selected in test cases selection, can also select multiple or whole test cases as needed, according to selection
Test case is different, forms the hardware description language code file that sustainable tripartite's emulation tool performs emulation, obtains batch and survey
Example generation Simulation Engineering file achievement on probation.
Wherein, in the step 1, in the two-dimensional coordinate axis achievement, abscissa is tested FPGA and its peripheral interface device
Part, ordinate are corresponding time scheduling.
Wherein, in the step 2, the task point is set as concurrent scheduling, by performing the configuration operation of task point, obtains
Task point achievement of allocation 2.
Wherein, in the step 2, the task point is set as sequential scheduling, by performing the configuration operation of task point, obtains
Task point achievement of allocation 2.
Wherein, in the step 3, critical data includes the triggered time of task point.
Wherein, in the step 3, critical data includes the trigger condition of task point.
Wherein, in the step 3, critical data includes test input data.
(3) advantageous effect
The present invention realizes FPGA software test cases in a manner of task scheduling, to task in a manner of task point
Scheduling is configured.Wherein task point is arranged in reference axis, the reference axis be made of transversal device and longitudinal time two
Dimension coordinate axis, by using to target each in reference axis in the way of timing requirements configuration task point, realize test case
Systematization and sequentialization operation, and then improve FPGA software emulation task schedulings capacity of system configuration, improve test case
Batch processing ability.
By implementing above-mentioned technical proposal, preferably resolve existing FPGA emulation testings and illustrate that test case is real in document
Test code is edited when applying line by line, leads to largely to test code being difficult to the problem of effective corresponding with test case.Appointed by setting
Business point, each task point can be corresponding with test case, can preferably embody task scheduling and whole test cases
Correspondence, so as to which the preferably coverage test of task point be enable to illustrate the test case in document.
The present invention preferably resolves the graphical interfaces showing problem of the systematicness of FPGA test case sequences, timing.
By reference axis, to each device on Simulation Model, task point, the setting of task point are set according to its timing requirements
Comprehensively corresponding and covering can be realized with test case, FPGA test cases is enable systematically to be opened up in task scheduling interface
Show.
The present invention, which is preferably resolved, to be asked what the execution of single test case or multiple test cases was implemented effectively to control
Topic.It can realize the test case combination selection in simulation process by way of user interface selection, realize that single test is used
Example, multiple test cases and batch testing use-case emulate, to realize that FPGA automation simulations provide preferable method.
Description of the drawings
Fig. 1 describes schematic diagram for FPGA software test cases.
Fig. 2 is the hardware description language schematic diagram that artificial edit code line by line realizes test case.
Fig. 3 is FPGA to be measured and its peripheral interface device test case two-dimensional coordinate axis achievement schematic diagram.
Fig. 4 is time shaft configuration schedules task point achievement schematic diagram.
Fig. 5 sets code achievement schematic diagram for scheduler task point.
Fig. 6 corresponds to test case achievement schematic diagram for task point.
Fig. 7 is task point sequence achievement schematic diagram.
Fig. 8 is test case sequence achievement schematic diagram.
Fig. 9 generates Simulation Engineering file achievement schematic diagram for batch testing use-case.
Figure 10 is task point schematic diagram.
Figure 11 inputs schematic diagram for task point attribute.
Specific embodiment
To make the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to the present invention's
Specific embodiment is described in further detail.
In order to solve the above technical problems, the present invention, which provides a kind of application time axis configuration mode, realizes that FPGA software emulations are appointed
The method for being engaged in dispatching, is as follows：
Step 1：By the system architecture of the tested FPGA of analysis, tested FPGA and its peripheral interface device are analyzed, is formed
The two-dimensional coordinate axis achievement of two-dimensional coordinate axis operation with above-mentioned device, as shown in Figure 3；
Step 2：On the basis of the two-dimensional coordinate axis achievement obtained by configuration task point module in step 1, further according to
Task point is configured according to the requirement of test case, obtains task point achievement of allocation, as shown in Figure 4；
Step 3：On the basis of establishing task point achievement of allocation in the time shaft of each device, task is further carried out
The setting of point, each task point is configured in the requirement according to test case, for the test pair described in test case
As, affiliated partner, test and excitation and sequential, response requirement, determine to include the triggered time of task point, trigger condition, test it is defeated
Enter the critical data including data, and the above-mentioned related content of test case is allocated to the task point in reference axis, and pass through and appoint
Business dot characteristics describe test case title, as shown in Figures 5 and 6, obtain task point setting outcome data；
Step 4：On the basis of test case setting task point setting outcome data, whole test cases are further carried out
The configuration of task point, each task point can correspond to test case description explanation and enable control, form task point sequence
Achievement and test case sequence achievement, as shown in Figures 7 and 8；
Step 5：In task point sequence achievement and test case sequence performance basis, in further being emulated
Single test case may be selected in test cases selection, can also select multiple or whole test cases as needed, according to selection
Test case is different, forms the hardware description language code file that sustainable tripartite's emulation tool performs emulation, obtains batch and survey
Example generation Simulation Engineering file achievement on probation, as shown in Figure 9.
Wherein, in the step 1, in the two-dimensional coordinate axis achievement, abscissa is tested FPGA and its peripheral interface device
Part, ordinate are corresponding time scheduling.
Wherein, in the step 2, the task point could be provided as concurrent scheduling, by performing the configuration operation of task point,
Acquisition task point achievement of allocation 2.
Wherein, in the step 2, the task point could be provided as sequential scheduling, by performing the configuration operation of task point,
Acquisition task point achievement of allocation 2.
Wherein, in the step 3, critical data includes the triggered time of task point.
Wherein, in the step 3, critical data includes the trigger condition of task point.
Wherein, in the step 3, critical data includes test input data.
Embodiment 1
In the present embodiment, concrete scheme is as follows：
1) this method is applied in FPGA emulation support platforms.In the emulation platform, FPGA and its periphery system are analyzed
System framework determines tested FPGA and its peripheral interface device.
The characteristics of 2) analyzing test case, determining input and output object, the output output data of test case related data,
Test case sequential relationship feature.
3) reference axis is established, which is tested FPGA and its peripheral interface device, ordinate are the time.
Each device on abscissa corresponds to a longitudinal axis.
4) it by the time shaft where tested FPGA, peripheral interface device, is carried out according to the requirement of parallel sequential, serial sequential
The task of sequential and data point is set.As shown in Figure 10.
5) above-mentioned task point is required to be configured according to test case, there is preferable correspondence with test case,
As shown in figure 11.
6) by the configuration of reference axis whole task point, FPGA software emulations is automatically generated and perform code.
To sum up, the design method of test case loading is realized in a manner that task point is configured the present invention relates to FPGA softwares.
Solve it is existing test case is realized by human-edited's code line by line, lack from system perspective and hold test assignment and sequential,
The drawbacks of being difficult to batch control and implementation of test cases.The present invention is suitable for FPGA Software Simulation Tests, according to system sequence
It is required that test case is embodied as to the test request of batch task scheduling.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformation can also be made, these are improved and deformation
Also it should be regarded as protection scope of the present invention.
Claims (7)
1. a kind of method that application time axis configuration mode realizes FPGA software emulation task schedulings, which is characterized in that specific step
It is rapid as follows：
Step 1：By the system architecture of the tested FPGA of analysis, tested FPGA and its peripheral interface device are analyzed, formation carries
The two-dimensional coordinate axis achievement of the two-dimensional coordinate axis operation of above-mentioned device；
Step 2：On the basis of the two-dimensional coordinate axis achievement obtained by configuration task point module in step 1, according further to survey
Task point is configured in the requirement of example on probation, obtains task point achievement of allocation；
Step 3：On the basis of establishing task point achievement of allocation in the time shaft of each device, task point is further carried out
Setting is configured each task point according to the requirement of test case, for described in test case test object, close
Join object, test and excitation and sequential, response requirement, determine critical data, and the above-mentioned related content of test case is allocated to seat
Task point in parameter, and pass through task dot characteristics and describe test case title, obtain task point setting outcome data；
Step 4：On the basis of test case setting task point setting outcome data, appointing for whole test cases is further carried out
Business point configuration, each task point can correspond to a test case description explanation and enable control, form task point sequence achievement
With test case sequence achievement；
Step 5：In task point sequence achievement and test case sequence performance basis, the test in further being emulated
Single test case may be selected in case selection, can also select multiple or whole test cases as needed, the test according to selection
Use-case is different, forms the hardware description language code file that sustainable tripartite's emulation tool performs emulation, obtains batch testing and use
Example generation Simulation Engineering file achievement.
2. the method that application time axis configuration mode as described in claim 1 realizes FPGA software emulation task schedulings, special
Sign is, in the step 1, in the two-dimensional coordinate axis achievement, abscissa is tested FPGA and its peripheral interface device, indulges and sits
It is designated as corresponding time scheduling.
3. the method that application time axis configuration mode as described in claim 1 realizes FPGA software emulation task schedulings, special
Sign is, in the step 2, the task point is set as concurrent scheduling, by performing the configuration operation of task point, obtains task point
Achievement of allocation 2.
4. the method that application time axis configuration mode as described in claim 1 realizes FPGA software emulation task schedulings, special
Sign is, in the step 2, the task point is set as sequential scheduling, by performing the configuration operation of task point, obtains task point
Achievement of allocation 2.
5. the method that application time axis configuration mode as described in claim 1 realizes FPGA software emulation task schedulings, special
Sign is, in the step 3, critical data includes the triggered time of task point.
6. the method that application time axis configuration mode as described in claim 1 realizes FPGA software emulation task schedulings, special
Sign is, in the step 3, critical data includes the trigger condition of task point.
7. the method that application time axis configuration mode as described in claim 1 realizes FPGA software emulation task schedulings, special
Sign is, in the step 3, critical data includes test input data.
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| CN109061448A (en) * | 2018-10-29 | 2018-12-21 | 北京京航计算通讯研究所 | IC testing stimuli based on modularization excitation model generates system |
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