CN108153372A

CN108153372A - Adjuster

Info

Publication number: CN108153372A
Application number: CN201810020546.1A
Authority: CN
Inventors: 龚劲峰; 王永刚; 常建光
Original assignee: Huaian Imaging Device Manufacturer Corp
Current assignee: Huaian Imaging Device Manufacturer Corp
Priority date: 2018-01-10
Filing date: 2018-01-10
Publication date: 2018-06-12

Abstract

This disclosure relates to adjuster.A kind of adjuster on chip, including：Input terminal, for receiving the power supply from chip exterior；Output terminal, for providing power supply output；Output module for receiving power supply, and provides power supply output, and wherein output module includes transmission transistor, and transmission transistor has coordination electrode capacitance, and coordination electrode capacitance causes adjuster that secondary pole is presented in the frequency response；Amplifier receives reference voltage and the first feedback signal associated with power supply output, and provides the Regulate signal for stabilized power source output；Buffer stage receives Regulate signal, and provides control signal to the control terminal of output module, and wherein buffer stage is configured as that the output impedance lower than the output impedance of amplifier is presented, and is configured such that secondary pole except desired gain frequency range.

Description

Adjuster

Technical field

This disclosure relates to adjuster (regulator), more particularly, to (on-chip) adjuster on chip.

Background technology

Adjuster (regulator) is widely used in integrated circuits.In such as cmos image sensor (CIS) (on-chip) voltage regulator is widely used on chip in CMOS integrated circuits.Adjuster can on chip or in its His circuit (for example, internal circuit) provides the power supply of better quality.

Accordingly, it is desirable to provide improved low pressure drop (LDO) adjuster.

Invention content

According to one aspect of the disclosure, the adjuster on a kind of chip is provided, including：Input terminal comes for receiving From the power supply of chip exterior；Output terminal, for providing power supply output；Output module, for receiving the power supply, and described in offer Power supply exports, wherein the output module includes transmission transistor, the transmission transistor has coordination electrode capacitance, the control Electrode capacitance processed causes the adjuster that secondary pole is presented in the frequency response；Amplifier, receive reference voltage and with institute It states power supply and exports associated first feedback signal, and the Regulate signal for stablizing the power supply output is provided；Buffer stage, The Regulate signal is received, and control terminal of the control signal to the output module is provided, wherein the buffer stage is configured For the output impedance lower than the output impedance of the amplifier is presented, and it is configured such that the secondary pole in desired increasing Except beneficial frequency range.

According to another aspect of the present disclosure, a kind of chip is provided, including the adjuster according to any embodiment.

In accordance with an embodiment of the present disclosure, improved adjuster can be provided, the occupied chip face of adjuster can be reduced Product.According to some embodiments of the present disclosure, since the output of buffer stage can be from lower power rail (for example, GND) to upper power rail (V_PS), therefore the performance of adjuster can be improved.According to some embodiments of the present disclosure, the stability of adjuster can also be improved And reliability.According to some embodiments of the present disclosure, the robustness to technique and device variation can also be improved.According to the disclosure Some embodiments, IC yields can be improved.

Low pressure drop can be had, and can support high current load range according to the adjuster of the embodiment of the present disclosure. According to some embodiments of the present disclosure, it can provide and export rail-to-rail buffer stage, so as to reduce the ruler of power MOSFET It is very little.According to some embodiments of the present disclosure, more accurately current sensing circuit is employed in the regulators, so as to improve adjusting Device performance, and may insure adjuster for PVT tests and the stability when different manufacturers manufacture.

By referring to the drawings to the detailed description of the exemplary embodiment of the disclosure, the other feature of the disclosure and its Advantage will become apparent.

Description of the drawings

A part for attached drawing constitution instruction shows some embodiments of the present disclosure, and uses together with the description In the principle for explaining the disclosure.According to detailed description with reference to the accompanying drawings, the disclosure can be more clearly understood, in attached drawing In：

Fig. 1 is the schematic diagram for showing the chip including adjuster according to an embodiment of the present disclosure；

Fig. 2 shows the schematic diagrames of the adjuster on the chip according to an embodiment of the present disclosure；

Fig. 3 shows the schematic diagram of the adjuster according to an embodiment of the present disclosure；

Fig. 4 shows the schematic diagram of the further improved adjuster according to an embodiment of the present disclosure；

Fig. 5 shows the schematic diagram of the adjuster according to disclosure further embodiment.

Note that in embodiments described below, same reference numeral is used in conjunction between different attached drawings sometimes Come the part for representing same section or there is identical function, and omit its repeated explanation.In the present specification, using similar mark Number and letter represent similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair It is further discussed.

In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. does not indicate that reality sometimes Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..

Specific embodiment

The various exemplary embodiments of the disclosure are described in detail now with reference to attached drawing.It should be noted that：It is unless in addition specific Illustrate, component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is unlimited to make this public affairs The range opened.In addition, technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, But in the appropriate case, the technology, method and apparatus should be considered as authorizing part of specification.

Word "front", "rear", " top ", " bottom " in specification and claim, " on ", " under " etc., if deposited If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way Language is interchangeable in appropriate circumstances so that embodiment of the disclosure described herein, for example, can in this institute Those of description show or other are orientated in other different orientations and operate.

The arbitrary realization method of this exemplary description be not necessarily to be interpreted it is more preferred than other realization methods or Advantageous.Moreover, the disclosure is not gone out by given in above-mentioned technical field, background technology, invention content or specific embodiment Theory that is any stated or being implied limited.

In the present specification, " adjuster " refers to that its a part or whole part can be special by using the semiconductor of semiconductor element Property and all devices to work, therefore, electro-optical device, electrooptical device, semiconductor circuit and electronic equipment etc. are all adjusters.

As used in this, word " substantially " mean comprising by design or manufacture the defects of, device or element appearance Arbitrary small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar Caused by sound and the other practical Considerations being likely to be present in practical realization method with perfect or ideal situation Between difference.

Foregoing description can indicate to be " connected " or " coupling " element together or node or feature.As used herein , unless explicitly stated otherwise, " connection " means an element/node/feature with another element/node/feature in electricity Above, it is directly connected mechanically, in logic or in other ways (or direct communication).Similarly, unless explicitly stated otherwise, " coupling " mean an element/node/feature can with another element/node/feature in a manner of direct or be indirect in machine On tool, electrically, in logic or in other ways link to allow to interact, even if the two features may not direct Connection is also such.That is, " coupling " is intended to encompass the direct connection and connection indirectly of element or other feature, including profit With the connection of one or more intermediary elements.

In addition, just to the purpose of reference, can also be described below it is middle use certain term, and thus not anticipate Figure limits.For example, unless clearly indicated by the context, be otherwise related to the word " first " of structure or element, " second " and it is other this Class number word does not imply order or sequence.

It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour Work, unit and/or component and/or combination thereof.

In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering obtain object all modes As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembling ", and/or " order " object etc..

The description of at least one exemplary embodiment is merely illustrative below, is not to the disclosure and its application Or any restrictions used.

Adjuster usually requires to have low pressure drop (dropout) to provide enough voltage headrooms (headroom).By In chip may it is a variety of it is possible there is very different power rating in the case of work, such as from very low power state (e.g., the standby mode of power saving) to high power state (e.g., high performance state, for example, present 4K clarity video flowing feelings Condition), therefore adjuster is required to support a variety of loading conditions.Under different loading conditions, in the chips and adjusting There may be a variety of transient state situations in device.Therefore, adjuster needs keep its output voltage opposite in desired working range Accurately, basic (or as far as possible) keep stablizing.In addition, the size of adjuster or shared chip area need to minimize, with drop Its low shared cost in entire chip.

In order to meet low pressure drop demand, usually using PMOS power MOSFET (Metal-oxide-semicondutor fields in LDO Effect transistor).Term " power MOSFET " used herein above or " power transistor " or " power device " are only used for Device as explanation or transistor be for supplying power to other circuits or internal circuit, with other transistors (e.g., For logic or the transistor of pixel unit) it distinguishes.Therefore, power transistor or power MOSFET are also often transmitted transistor (pass transistor).Hereinafter referred to as transmission transistor.

Transmission transistor general size is larger, to support high output current.However, since its size is big, crystal is transmitted It may there are big coordination electrode capacitances (grid capacitance) at the coordination electrode (grid) of pipe.So as to cause in adjuster There may be the low-frequency poles except dominant pole in frequency response.This can influence the stability of adjuster.

Present inventor is in view of the understanding to the above problem, after in-depth study, it is proposed that is disclosed Solution and technology, at least to mitigate or overcome the problems, such as one or more of to mention above and below.

Fig. 1 is the schematic diagram for showing the chip including adjuster according to an embodiment of the present disclosure.As shown in Figure 1, core Piece 100 includes adjuster 101.Adjuster 101 can receive power supply, such as VAA from outside, and the power supply is adjusted for chip Internal circuit or other circuits 105 use, and VAAPIX_int are such as adjusted to, for pel array, booster, driver etc. It uses.

In the example depicted in fig. 1, chip can also directly receive VAAPIX from external, to be carried by power switch 103 The internal circuit or other circuits 105 for supplying chip use.Power switch 107 is also shown in Fig. 1, electricity will be obtained from outside Source VAA is provided to other analog circuits 109 and is used for it.

Fig. 2 shows the schematic diagrames of the adjuster on the chip according to an embodiment of the present disclosure.As shown in Fig. 2, it adjusts Device 200 includes input terminal IN, for receiving the power supply V from chip exterior_IN.Adjuster 200 further includes output terminal OUT, is used for Power supply output Vout is provided.Power supply output Vout can be provided to the internal circuit of such as chip.

Adjuster 200 further includes output module 201, shown in the dotted line frame as indicated by 201 in Fig. 2.Output module 201 For receiving the power supply, and provide the power supply output.Output module 201 can have first terminal, Second terminal and control Terminal processed.First terminal is connected to input terminal IN.Second terminal is connected to output terminal OUT.

Adjuster 200 further includes amplifier 203, receives reference voltage VREF and associated with power supply output Vout the One feedback signal (FB1) 209, and the Regulate signal 211 for stabilized power source output is provided.In this sense, amplifier 203 It can be referred to as error amplifier.Reference voltage VREF can by it is external provide or by chip other circuits (for example, Pass through a reference source of such as band gap reference) it provides.

Adjuster 200 further includes buffer stage 205, receives Regulate signal 211, and provides control signal 213 to output mould The control terminal of block 201.Buffer stage 205, which can be configured as, is presented the output impedance lower than the output impedance of amplifier 203, with Increase frequency response range of the output module 201 under expected gain.

Usually, in the range of ± the 3dB of target gain, it is believed that such gain is desirably.With this Corresponding frequency range is considered frequency response range of the circuit (adjuster as described in this) under expected gain. In most embodiment, target gain can be unit gain (unit gain).Unit gain frequency range can be wherein The range of the output module 201 frequency with unit gain substantially.As previously described, in the model of ± 3dB of unit gain In enclosing, it is believed that circuit has unit gain substantially.

Here, as shown in Figure 2, output module 201 can include transmission transistor Mp.The first electricity of transmission transistor Mp Stream carrying electrode (for example, source S) be connected to output module 201 first terminal (therefore, the first terminal can also with S come Mark), and therefore it is connected to input terminal IN.The second current carrying electrode (for example, drain D) of transmission transistor Mp is connected to defeated Go out the Second terminal (therefore, which can also be indicated with D) of module 201, and be therefore connected to output terminal OUT.It passes The coordination electrode (for example, grid G) of defeated transistor Mp is connected to control terminal (therefore, control terminal of output module 201 Can be indicated with G), and therefore it is connected to the output of buffer stage 205.In the figure 2 example, transistor Mp is p-type MOS crystal Pipe.It should be understood, however, that the disclosure is not limited to this.

In some implementations, the size of transmission transistor Mp is (for example, grid width/grid length is than (assuming that other conditions phase Can be together)) that other transistors (such as form transistor in amplifier 203 and the transistor or logic of buffer stage 205 Or the transistor in pixel unit) size hundred times, thousand times, ten thousand times of even higher magnitudes.Therefore, transmission transistor Mp Coordination electrode capacitance (grid capacitance) can be hundred times of coordination electrode capacitance of other transistors, thousand times, ten thousand times it is even higher.

The grid capacitance Cp of transmission transistor Mp is schematically shown in Fig. 2.Big grid capacitance Cp may result in To the capacitive channels of ground (for example, substrate).Grid capacitance Cp causes adjuster that secondary pole is presented in the frequency response.Along band Illustrate, the person skilled in the art will easily understand usually, in the frequency analysis of circuit, the minimum pole of frequency is referred to as Dominant pole.The pole of higher frequency can be referred to as secondary pole.It in accordance with an embodiment of the present disclosure, can be by providing buffer stage To cause secondary pole except desired gain frequency range.

Adjuster 200 can also include feedback circuit 207.Feedback circuit 207 is connected to the output terminal OUT and low potential Between reference mode (for example, ground), for providing the first feedback signal FB1 to amplifier 203.In the figure 2 example, feedback electricity Road 207 includes the resistor R1 and R2 that are connected in series with.Feedback signal FB1 is provided from node therebetween.Here, feedback circuit 207 can be also used for adjusting the voltage of power supply output Vout.

In addition, as shown in Fig. 2, error amplifier 203, which receives other supply voltage VDD, carrys out work.It should be understood that this is only It is exemplary.In some implementations, amplifier 203 can be received different from V_INSupply voltage, can also be alternatively Receive V_INIt is used as power supply or Vout can also be received and carrys out work as supply voltage.

In addition, the load for being connected to output OUT is also shown in figure.As an example, load can include but is not limited to One or more of following or combination：Resistive load ESR, capacity load (with capacitor using Co and Cb as example), Current source Ir etc..

Fig. 3 shows the schematic diagram of the adjuster according to an embodiment of the present disclosure.As shown in figure 3, adjuster 300 includes Input terminal IN, for receiving the power supply V from chip exterior_IN, output terminal OUT is further included, for providing power supply output Vout.It adjusts Section device 300 further includes output module 301, shown in the dotted line frame as indicated by 301 in Fig. 3.Output module 301 can have the One terminal, Second terminal and control terminal.First terminal is connected to input terminal IN.Second terminal is connected to output terminal OUT.

Adjuster 300 further includes amplifier 303, receives reference voltage VREF and associated with power supply output Vout the One feedback signal (FB1), and the Regulate signal (not indicating) for stabilized power source output is provided.

Adjuster 300 further includes buffer stage 305, receives Regulate signal, and provides control signal to output module 301 Control terminal.Buffer stage 305, which can be configured as, is presented the output impedance lower than the output impedance of amplifier 303, defeated to increase Go out frequency response range of the module 301 under expected gain.

Here, as shown in Figure 3, output module 301 can include transmission transistor Mp.The first electricity of transmission transistor Mp Stream carrying electrode (for example, source electrode) is connected to the first terminal of output module 301, and be therefore connected to input terminal IN.Transmission is brilliant The second current carrying electrode (for example, drain D) of body pipe Mp is connected to the Second terminal of output module 301, and be therefore connected to Output terminal OUT.(therefore, the coordination electrode (for example, grid G) of transmission transistor Mp is connected to the control terminal of output module 301 The control terminal can also be indicated with G), and therefore it is connected to the output of buffer stage 305.

In this example, transistor Mp can be N-type MOS transistor.The size of transmission transistor Mp is (for example, grid width/grid It is long than (assuming that other conditions are identical)) can be other transistors (such as form amplifier 303 and the transistor of buffer stage 305, Or the transistor in the transistor or pixel unit in logic) size hundred times, thousand times, ten thousand times of even higher magnitudes. Correspondingly, the coordination electrode capacitance (grid capacitance) of transmission transistor Mp can be the hundred of the coordination electrode capacitance of other transistors Times, thousand times, ten thousand times it is even higher.

As shown in Figure 3, buffer stage 305 can include：First buffer module 3051 and provide the first of bias current partially Circuits 3053.Buffer stage 305 is configured as that the output impedance lower than the output impedance of amplifier 303 is presented.First buffering mould Block 3051 can have first terminal, Second terminal and control terminal.The control terminal of first buffer module 3051, which is connected to, to be put The Regulate signal that the output terminal (that is, node N1) of big device 303 is exported with reception amplifier 303.The of first buffer module 3051 One terminal is connected to the first end (node N2) of the first biasing circuit 3053, and is connected to the control terminal of output module 301 (simultaneously Therefore it is connected to the grid of transmission transistor Mp).

The second end of first biasing circuit 3053 may be coupled to input terminal IN to receive the supply voltage V of input_INOr It can connect to receive other supply voltage V_PS.In other words, power supply V_PSIt can be with the power supply V of input_INIt is identical or different.

In sample implementation, the first buffer module 3051 can include the first transistor M1.The first transistor M1's Coordination electrode (for example, grid) may be coupled to the control terminal of the first buffer module 3051, the first electric current of the first transistor Carrying electrode (for example, source electrode) may be coupled to the first terminal (node N2) of the first buffer module 3051.The first transistor Second current carrying electrode (for example, drain electrode) may be coupled to low potential reference mode NL (such as, but not limited to, ground).At other In embodiment, the second current carrying electrode (for example, drain electrode) of the first transistor may be coupled to other circuits, such as such as Fig. 4 Shown in biasing circuit etc..

By the buffer stage (transistor M1) for being configured as source follower as shown in Figure 3, unit gain can be provided. Also, compared to the output impedance of amplifier, the output impedance of source follower reduces, so that secondary pole is being adjusted Except the desired gain frequency range for saving device.In addition, by biasing circuit 3053, it can be by buffer module 3051 (in other words, Transistor M1) appropriate operating point is placed in, so as to further reduce output impedance.

Adjuster 300 can also include feedback circuit 307.Feedback circuit 307 is connected to the output terminal OUT and low potential Between reference mode (for example, ground), for providing the first feedback signal FB1 to amplifier 303.In the example of fig. 3, feedback electricity Road 307 includes the resistor R1 being connected in parallel and capacitor C1 and the resistor R2 being connected in series with the parallel combination.From string Interlink point N4 provides feedback signal FB1.Here, feedback circuit 307 can be also used for adjusting the voltage of power supply output Vout.

Adjuster 300 can also include compensation circuit 309.Compensation circuit 309 can be arranged on the control of buffer module 3051 Between terminal and low potential reference mode processed.Compensation circuit 309 can be set to have variable or programmable RC coefficients. In example shown in Fig. 3, compensation circuit 309 includes variable or programmable resistor R3 and/or variable or programmable capacitance Device C2.It is thus possible to the further frequency response of the RC constants of regulation resistance, further improvement circuit.

However, for scheme shown in Fig. 3, in order to make buffer stage minimum resistance, the device ruler of pmos source follower It is very little to need larger or its bias current needs larger.This may be unfavorable in some cases.Fig. 4 is shown according to this The schematic diagram of the further improved adjuster of open one embodiment.

As shown in figure 4, adjuster 400 includes input terminal IN, for receiving the power supply V from chip exterior_IN, further include defeated Outlet OUT, for providing power supply output Vout.Adjuster 400 further includes output module 401, as indicated by 401 in Fig. 4 Shown in dotted line frame.Output module 401 can have first terminal, Second terminal and control terminal.First terminal is connected to input Hold IN.Second terminal is connected to output terminal OUT.

Adjuster 400 further includes amplifier 403, receives reference voltage VREF and associated with power supply output Vout the One feedback signal (FB1), and the Regulate signal (not indicating) for stabilized power source output is provided.

Adjuster 400 further includes buffer stage 405, receives the Regulate signal, and provides control signal to output module 401 control terminal.Buffer stage 405, which can be configured as, is presented the output impedance lower than the output impedance of amplifier 403, to increase Add frequency response range of the output module 401 under expected gain.

Here, as shown in Figure 4, output module 401 can include transmission transistor Mp.The first electricity of transmission transistor Mp Stream carrying electrode (for example, source electrode) is connected to the first terminal of output module 401, and be therefore connected to input terminal IN.Transmission is brilliant The second current carrying electrode (for example, drain D) of body pipe Mp is connected to the Second terminal of output module 401, and be therefore connected to Output terminal OUT.(therefore, the coordination electrode (for example, grid G) of transmission transistor Mp is connected to the control terminal of output module 401 The control terminal can also be indicated with G), and therefore it is connected to the output of buffer stage 405.In this example, transistor Mp quilts It is shown as N-type MOS transistor.The size (for example, grid width/grid length is than (assuming that other conditions are identical)) of transmission transistor Mp can be with (such as transistor or pixel list in amplifier 403 and the transistor or logic of buffer stage 405 are formed for other transistors Transistor in member) size hundred times, thousand times, ten thousand times of even higher magnitudes.Correspondingly, the control electricity of transmission transistor Mp Electrode capacitance (grid capacitance) can be hundred times of coordination electrode capacitance of other transistors, thousand times, ten thousand times it is even higher.

It can similarly or adaptively be suitable for the reality with regard to the content of the corresponding component of other embodiment description above Apply the described corresponding component of example.

As shown in Figure 4, buffer stage 405 can include：First buffer module 4051 and provide the first of bias current partially Circuits 4053.Buffer stage 405 is configured as that the output impedance lower than the output impedance of amplifier 403 is presented.First buffering mould Block 4051 can have first terminal, Second terminal and control terminal.The control terminal of first buffer module 4051, which is connected to, to be put The Regulate signal that the output terminal (node N1) of big device 403 is exported with reception amplifier 403.The first end of first buffer module 4051 Son is connected to the first end (node N2) of the first biasing circuit 4053, and is connected to the control terminal of output module 401 (and therefore It is connected to the grid of transmission transistor Mp).

The second end of first biasing circuit 4053 may be coupled to input terminal IN to receive the supply voltage V of input_INOr It can connect to receive other supply voltage V_PS.In other words, power supply V_PSIt can be with the power supply V of input_INIt is identical or different.

In sample implementation, the first buffer module 4051 can include the first transistor M1.The first transistor M1's Coordination electrode (for example, grid) may be coupled to the control terminal of the first buffer module 4051, the first electric current of the first transistor Carrying electrode (for example, source electrode) may be coupled to the first terminal of the first buffer module 4051, and be therefore connected to the first biasing The first end (that is, being connected to node N2) of circuit 4053.The second current carrying electrode (for example, drain electrode) of the first transistor can To be connected to low potential reference mode NL (such as, but not limited to, ground).In other embodiments, the second electric current of the first transistor Carrying electrode (for example, drain electrode) may be coupled to other circuits.As shown in FIG., the first buffer module be provided as source electrode with With device.

Buffer stage 405 can also include feedback module, for providing to the voltage at the control terminal of the output module Negative feedback control.In one implementation, feedback module can include the second buffer module 4055 and the second biasing circuit 4057, as shown in Figure 4.

Second buffer module 4055 has first terminal, Second terminal and control terminal.The control of second buffer module 4055 Terminal processed is connected to the Second terminal (that is, being connected to node N5) of the first buffer module 4051.Second buffer module 4055 First terminal is connected to the first end of the first biasing circuit 4053, is also attached to node N2.

Second buffer module 4055 can include second transistor.In the example depicted in fig. 4, transistor Q1 is shown as Bipolar tube, however the present disclosure is not limited thereto, transistor Q1 can also be realized with MOS transistor (for example, N-type MOS transistor). The coordination electrode (for example, base stage or grid) of second transistor is connected to the control terminal of the second buffer module 4055, Ye Jilian It is connected to node N5.The first current carrying electrode (for example, collector or drain electrode) of second transistor is connected to the second buffer module 4055 first terminal is also attached to node N2.Second current carrying electrode of second transistor may be coupled to low potential Reference mode (for example, ground (GND)) or other circuits (for example, biasing circuit).

Second biasing circuit 4057 can include third transistor M3, the 4th transistor M4 and the 5th transistor M5.Third The coordination electrode (for example, grid) of transistor M3 is connected to the first end (that is, being connected to node N2) of the first biasing circuit 4053. The first current carrying electrode (for example, source electrode) of third transistor M3 is connected to supply voltage V_PS.The second of third transistor M3 Current carrying electrode (for example, drain electrode) is connected to the first current carrying electrode (for example, drain electrode) of the 4th transistor M4.Here, As an example, N-type MOS transistor is set in transistor M3, and transistor M4 and M5 are arranged to N-type MOS transistor.

The coordination electrode (for example, grid) of 4th transistor M4 is connected to the coordination electrode of the 5th transistor M5 (for example, grid Pole) and it is connected to the first current carrying electrode (for example, drain electrode) of the 4th transistor.The second current load of 4th transistor M4 Electrode (for example, source electrode) is connected to low potential reference mode NL (its may be coupled to (GND)).The first of 5th transistor M5 The Second terminal that current carrying electrode (for example, drain electrode) is connected to the first buffer module 4051 (and therefore, is connected to first crystal The second current carrying electrode (for example, drain electrode) of pipe M1).The second current carrying electrode (for example, source electrode) of 5th transistor M5 It is connected to low potential reference mode (NL).

When node N2 current potential (V_N2) so that P-type transistor M3 conducting (ON) (that is, | V_N2-V_PS|>| Vth_M3 |, In " | | " represent absolute value, Vth_M3 is the threshold value of transistor M3), and when therefore transistor M4 and M5 is connected, node N5 is by under It draws.So as to transistor Q1 shutdowns.In this case, the potential minimum that the current potential of node N2 can be pulled down to is：Ground (0V)+ The drain-source of the gate-source voltage Vgs (Vgs_M1) of transistor M1+transistor M4 or M5 (if M4 and M5 are symmetrical) Voltage Vds (Vds_M4)=Vgs_M1+Vds_M4.

And when node N2 current potential cause P-type transistor M3 shutdown (OFF) (that is, | V_N2-V_PS|<| Vth_M3 |), and because When this transistor M4 and M5 is turned off, transistor M1 conductings so that transistor Q1 opens (conducting), so that the current potential of node N2 is by under It draws.Therefore, the maximum potential of node N2 can be：V_PS–|Vth_M3|。

In addition, when the current potential increase of node N2 so that the current potential of the coordination electrode (here, base stage) of transistor Q1 ( That is, the current potential of node N5) increase, so that the electric current Ic of the collector of Q1 increases into+1 times of ground of β.So as to further reduced Output resistance.With the increase of electric current, the current potential at node N2 reduces, so as to which output be maintained to stablize.

By above-mentioned feedback mechanism, output can be stablized；And the output impedance of buffer stage can be further reduced, from And secondary pole can further be made to offset out desired frequency range.

In some embodiments, buffer stage 405 can also include third buffer module 4059, as shown in Figure 4.Third is delayed Die block 4059 can be used for measuring the output current of the output terminal output, and provide associated with the output current anti- It is fed to the feedback module.Third buffer module 4059 can have first terminal, Second terminal and control terminal.Third buffers The control terminal of module 4059 is connected to the first end (node N2) of the first biasing circuit 3053.The of third buffer module 4059 One terminal is connected to supply voltage V_PS.The Second terminal of third buffer module 4059 is connected to the first of the second buffer module 4055 Terminal is also attached to node N2.The Second terminal of second buffer module 4055 may be coupled to low potential reference mode NL.

Third buffer module 4059 can include the 6th transistor MPS.The coordination electrode of 6th transistor MPS is (for example, grid Pole) control terminal of third buffer module 4059 is connected to, and be therefore connected to node N2.The first electricity of 6th transistor MPS Stream carrying electrode (for example, source electrode) is connected to the first terminal of third buffer module 4059, and be therefore connected to supply voltage V_PS。 The second current carrying electrode (for example, drain electrode) of 6th transistor MPS is connected to the Second terminal of third buffer module 4059, and Therefore it is connected to node N2.Here, transistor MPS is formed by N-type MOS transistor.The drain electrode of P-type transistor MPS is connected to it Grid.

The size with the transmission transistor (Mp) in the output module can be set in the size of 6th transistor Proportionally reduce.Since there is MPS the grid voltage and source voltage identical with Mp (to set V_PS=V_IN), therefore, pass through MPS The output current for flowing through Mp can be sensed to a certain extent, and feedback associated with the output current is provided.It can lead to It crosses feedback module and provides and associated with output current feed back to buffer module 4051 (it is configured as source follower).This In, buffer module 4059 can also be referred to as current sensing module.

The source follower with feedback module is configured as by as shown in Figure 4 buffer stage (transistor M1 and Q1), relative to the output impedance of amplifier, it can cause the output impedance of source follower to reduce, so that secondary Pole is except the desired gain frequency range of adjuster.In addition, by buffer module 4051,4055 and 4059, can make Output is stablized, and can also adaptively be tracked output current and is adjusted.

Adjuster 400 can also include feedback circuit 407.Feedback circuit 407 is connected to the output terminal OUT and low potential Between reference mode (for example, ground), for providing the first feedback signal FB1 to amplifier 403.In the example of fig. 4, feedback electricity Road 407 includes the resistor R1 and R2 that are connected in series with.Feedback signal FB1 is provided from series connection node N4.Here, feedback circuit 407 It can be also used for adjusting the voltage of power supply output Vout.

Compared with scheme shown in Fig. 3, the output impedance of the buffer stage in embodiment shown in Fig. 4 is significantly reduced.And And output impedance adaptively tracks output current, so that improving stability on entire loading range.

Fig. 5 shows the schematic diagram of the adjuster according to disclosure further embodiment.Adjuster shown in fig. 5 is in front It is further improved on the basis of shown embodiment.

In scheme shown in Fig. 4, the minimum grid voltage of power transistor (transmission transistor) Mp is limited to | Vgs | +Vds.However, in order to drive big output current, electric current is driven in big the crossing of output transistor Mp to be examined prior to its big size Consider.Secondly, current sense transistor MPS and transmission transistor Mp has different drain voltages.Therefore, channel length modulation It will influence the order of accuarcy of the current sense of output current.For large-scale production, it is also necessary to consider these problems.

For one or more of these problems, it is proposed that the scheme shown to example as shown in Figure 5.

As shown in figure 5, adjuster 500 includes input terminal IN, for receiving the power supply V from chip exterior_IN, further include defeated Outlet OUT, for providing power supply output Vout.Adjuster 500 further includes output module 501, as indicated by 501 in Fig. 5 Shown in dotted line frame, for receiving the power supply, and the power supply output is provided.Adjuster 500 further includes amplifier 503, connects Reference voltage VREF and the first feedback signal (FB1) associated with power supply output Vout are received, and is provided defeated for stabilized power source The Regulate signal (not indicating) gone out is to node N1.Adjuster 500 further includes buffer stage 505, receives the Regulate signal, and Control terminal of the control signal to output module 501 is provided.It is more defeated than amplifier 503 that buffer stage 505 can be configured as presentation Go out the low output impedance of impedance, to increase frequency response range of the output module 501 under expected gain.

Here, as shown in Figure 5, output module 501 can include transmission transistor Mp.The control electricity of transmission transistor Mp Pole (for example, grid G) is connected to the control terminal (therefore, which can also be indicated with G) of output module 501, and Therefore it is connected to the output of buffer stage 505.In this example, transistor Mp is shown as N-type MOS transistor.Transmission transistor The size (for example, grid width/grid length is than (assuming that other conditions are identical)) of Mp can be that other transistors (such as form amplifier 503 and buffer stage 505 transistor or logic in transistor or pixel unit in transistor) hundred times of size, thousand Again, ten thousand times of even higher magnitudes.Correspondingly, the coordination electrode capacitance (grid capacitance) of transmission transistor Mp can be that other are brilliant Hundred times of the coordination electrode capacitance of body pipe, thousand times, ten thousand times it is even higher.

It can similarly or adaptively be suitable for the reality with regard to the content of the corresponding component of other embodiment description above Apply the described corresponding component of example.Repeated explanation is no longer carried out herein.

As shown in Figure 5, buffer stage 505 can include the first buffer part 3051 ' and for bias current is provided first Biasing circuit 5053.It is slow that first buffer part 3051 ' can include the first buffer module 5051, the second buffer module 5055 and the 4th Die block 5057.First buffer part 3051 ' is configured as that the output impedance lower than the output impedance of amplifier 503 is presented.At this In embodiment, the first buffer part 3051 ' is configured as showing lower than the buffer module 305 or 405 shown in Fig. 3 and Fig. 4 Output impedance.First buffer module 5051 can be configured as source follower form.Second buffer module 5055 and the 4th Buffer module 5057 may be used as the feedback path provided to the first buffer module 5051.4th buffer module 5057 may be used as Level shifter.

The control terminal of first buffer module 5051 receives control signal, the first terminal connection of the first buffer module 5051 To the first biasing circuit 5053 first end N2 and be connected to the control terminal of the 4th buffer module 5057, the first buffer module 5051 Second terminal is connected to the control terminal of the second buffer module 5055.

The first terminal of second buffer module 5055 is connected to the Second terminal (node N2) of the 4th buffer module 5057, and It is connected to the control terminal of output module 501.The second end of first biasing circuit 5053 is connected to input terminal IN or supply voltage V_PS。

The first terminal of 4th buffer module 5057 is connected to the first end (node N3) of the first biasing circuit 5053.4th Buffer module can be formed by primary (native) transistor.Here, term " native transistor " is that the generality of this field is normal With term, represent that threshold voltage is essentially the MOS transistor of 0V.

More specifically, the first buffer module 5051 can include the first transistor M1A.The control electricity of the first transistor M1A Pole is connected to the control terminal of the first buffer module 5051.First current carrying electrode of the first transistor is connected to the first buffering The first terminal of module 5051.Second current carrying electrode of the first transistor is connected to the second end of the first buffer module 5051 Son.

Second buffer module 5055 can include second transistor Q1.The coordination electrode of wherein second transistor is connected to The control terminal of two buffer modules 5055.The first current carrying electrode of second transistor Q1 is connected to the second buffer module 5055 First terminal.The second current carrying electrode of second transistor Q1 is connected to the Second terminal of the second buffer module 5055.Class As, although Q1 is shown as bipolar transistor here, can also be realized in other embodiments using MOS transistor.

4th buffer module 5057 includes the 7th transistor M1B.The coordination electrode of 7th transistor is connected to the 4th buffering The control terminal of module 5057.The first current carrying electrode of 7th transistor M1B is connected to the of the 4th buffer module 5057 One terminal.The second current carrying electrode of 7th transistor M1B is connected to the Second terminal of the 4th buffer module 5057.7th is brilliant Body pipe can be native transistor.4th buffer module 5057 can be used as level shifter, so that transmission PMOS transistor Mp Grid voltage close to low reference potential rail (for example, track), so as to use smaller power P MOS transistor.This It is it is required that especially beneficial in the application of high current output.On the other hand, the smaller situation of current loading and low current are exported Situation, flow through the electric current of entire module (the first buffer module) for Ib, the voltage at the source and drain both ends of primary NMOS is very small.Work( The grid voltage of rate MOSFET can be pulled near in upper power rail (V_PS).However, the disclosure is not limited to this.According to not Same application scenario, may be used appropriate transistor to form buffer module.

In some embodiments, buffer stage 505 can also include the second buffer part, for measuring the output of output terminal output Electric current, and provide and associated with output current feed back to the first buffer part 3051 '.Example implementations shown in Fig. 5 In, the second buffer part can include the 5th buffer module 509 and current sense feedback circuit 511.5th buffer module 509 can be with For measuring the output current of the output terminal output, so as to provide information associated with the output current.Current sense Feedback circuit 511 can be used for providing essentially identical bias voltage for the 5th buffer module and the output stage 501, and Described information feedback can be provided to first buffer part 3051 ' by electric signal (current or voltage).

5th buffer module 509 can have first terminal, Second terminal and control terminal.5th buffer module 509 Control terminal is connected to the first terminal (node N2) of the second buffer module 5055, and the first terminal of the 5th buffer module 509 connects Input terminal IN is connected to, the Second terminal of the 5th buffer module 509 is connected to current sense feedback circuit 511.

As shown in figure 5, current sense feedback circuit 511 can include the first current mirror 5111, pull-down module 5113 and sense Survey biasing module 5115.First output terminal of the first current mirror 5111 is connected to the first end N3 of the first biasing circuit 5053, the The second output terminal of one current mirror 5111 is connected to pull-down module 5113.The first terminal of 5th buffer module 509 is connected to defeated Enter and hold IN, the control terminal of the 5th buffer module 509 is connected to the first terminal (node N2) of the second buffer module 5055.

Sensing biasing module 5115 can include transistor M9B, M9C, M10A and M10B.Transistor M9B, M9C's of N-type Grid links together, and is connected to the drain electrode of transistor M9B, as shown in the figure.Transistor M10A and M10B grid is connected to one It rises, and is connected to the drain electrode of transistor M10B.The drain electrode of transistor M9B is connected to the drain electrode of P-type transistor M10A.Transistor The drain electrode of M9C is connected to the drain electrode of P-type transistor M10B.In this way, one branch of transistor M9B and M10A formation, and transistor M9C and M10B forms another branch.The Liang Ge branches of sensing biasing module 5115 are connected respectively to the of the first output module 501 The Second terminal of two-terminal and the 5th buffer module 509, as shown in FIG..It is thus possible to for the 5th buffer module 509 and output Module 501 provides essentially identical biasing.

Pull-down circuit 5113 includes transistor M9A.Transistor M9A can be with transistor M9B, M9C matchingly or symmetrically Setting.So that three forms current mirror.Accordingly it is also possible to say, sensing biasing module 5115 is formed with pull-down circuit 5113 Current mirror (the second current mirror).The first input end of second current mirror is connected to the second output terminal of the first current mirror, and Second input terminal of two current mirrors is connected to the output terminal OUT of adjuster.

In more specific example, the 5th buffer module 509 can include the 6th transistor Mps.6th transistor Mps's Coordination electrode is connected to the control terminal of the 5th buffer module 509, and the first current carrying electrode of the 6th transistor Mps is connected to The first terminal of 5th buffer module 509, the second current carrying electrode of the 6th transistor Mps are connected to the 5th buffer module 509 Second terminal.Here, the size with the transmission transistor Mp in output module can be set in the size of the 6th transistor Proportionally reduce.The drain electrode of 6th transistor Mps and transmission transistor Mp can be set to essentially identical biasing.

Adjuster 500 can also include feedback circuit 507.Feedback circuit 507 is connected to the output terminal OUT and low potential Between reference mode (for example, ground), for providing the first feedback signal FB1 to amplifier 503.In the example of hgure 5, feedback electricity Road 507 includes the resistor R1 and R2 that are connected in series with.Feedback signal FB1 is provided from series connection node N4.Here, feedback circuit 507 It can be also used for adjusting the voltage of power supply output Vout.

Adjuster 500 can also include capacitive feedback circuit, such as capacitor Cc, be connected to output terminal OUT and amplification Between device 503, for providing the second feedback signal associated with exporting to amplifier 503.

By the buffer stage being configured as illustrated in fig. 5, relative to the output impedance of amplifier, it can cause source follower Output impedance reduce so that secondary pole is except the desired gain frequency range of adjuster.In addition, pass through Buffer module 5051,5055 and 509, can stablize output, and can adaptively track output current and be adjusted.Separately Outside, since circuit is symmetrical, compared with the scheme of Fig. 4, transistor Mps and Mp have preferably matching, so as to The more accurately variation of follow current.According to the present embodiment, rail-to-rail grid can also be provided in the grid of output transistor Mp Pole tension, so that the fan-out capability of output transistor maximizes.

Fig. 5 also shows a kind of example implementations of the amplifier according to the embodiment of the present disclosure.Amplifier 503 includes First order circuit and second level circuit.The first order includes first and second input transistors M11A, M11B and provides it biasing Bias current sources Ia.First and second input transistors receive reference voltage VREF and first instead respectively by its coordination electrode Feedback signal, bias current sources IA provide biasing to the first current carrying electrode of the first and second input transistors.It the second level can To include multiple transistor M12A-M12B and optional M12C and M12D, M13A-M13B, M14A-M14B, M15A-M15B. The multiple transistor forms Liang Ge branches.Second current carrying electrode of the first and second input transistors is connected respectively to this Node N6, N7 in Liang Ge branches.

The grid of NMOS transistor M12A-M12B and optional M12C and M12D link together, and source electrode is connected to Low potential reference mode.The drain electrode of transistor M12A is connected to node N6, and the drain electrode of transistor M12B is connected to node N7.PMOS The grid of transistor M14A-M14B links together.The grid of PMOS transistor M15A-M15B links together, and is connected to The drain electrode of transistor M14A.The drain electrode of transistor M15A-M15B is connected respectively to the source electrode of transistor M14A-M14B.Transistor The source electrode of M15A-M15B is connected to voltage VPS.The drain electrode of transistor M14A-M14B be connected respectively to transistor M13A and The drain electrode of M13B.The source electrode of transistor M13A and M13B are connected respectively to node N6 and N7.

The output of amplifier between the drain electrode of transistor M13B and the drain electrode of transistor M14B is provided, is connected to node N1.In the example depicted in fig. 5, the second feedback signal FB2 is provided to node N7, that is, being connected to the first and second inputs The second current carrying electrode of the input transistors of reference voltage is not received in transistor.

Although a transistor may be illustrated only in the accompanying drawings, it will be understood by those skilled in the art that it can also lead to Multiple transistors are crossed to implement.

So far, it should be appreciated that the disclosure is contemplated that a kind of chip, can include the adjusting of disclosure any embodiment Device.

It should also be understood that the disclosure be contemplated that it is following.

Adjuster on a kind of 1. chip of project, including：Input terminal, for receiving the power supply from chip exterior；Output End, for providing power supply output；Output module for receiving the power supply, and provides the power supply output, wherein the output Module includes transmission transistor, and the transmission transistor has coordination electrode capacitance, and the coordination electrode capacitance causes the tune Secondary pole is presented in section device in the frequency response；Amplifier receives reference voltage and associated with power supply output the One feedback signal, and the Regulate signal for stablizing the power supply output is provided；Buffer stage receives the Regulate signal, and Control terminal of the control signal to the output module is provided, wherein the buffer stage is configured as presenting than the amplifier The low output impedance of output impedance, and it is configured such that the secondary pole except desired gain frequency range.

Adjuster of the project 2. according to project 1, wherein：The coordination electrode of the transmission transistor is connected to described defeated Go out the control terminal of module, the first current carrying electrode of the transmission transistor is connected to the first end of the output module Son, the second current carrying electrode of the transmission transistor are connected to the Second terminal of the output module.

Adjuster of the project 3. according to project 1, wherein：Desired gain is unit gain, the desired gain Frequency range is the frequency range that wherein described adjuster has unit gain under open loop.

Adjuster of the project 4. according to project 1, wherein：The coordination electrode capacitance of the transmission transistor is configured as Form the 10 of the coordination electrode capacitance of the amplifier and the transistor of the buffer stage²Times or higher.

Adjuster of the project 5. according to project 1, wherein the buffer stage includes：First buffer module and offer biasing First biasing circuit of electric current, wherein：First buffer module has first terminal, Second terminal and control terminal, described The control terminal of first buffer module receives the Regulate signal, and the first terminal of first buffer module is connected to described the The first end of one biasing circuit, and it is connected to the control terminal of the output module；The second end of first biasing circuit connects It is connected to the input terminal or supply voltage.

Adjuster of the project 6. according to project 5, first buffer module include the first transistor, wherein：It is described The coordination electrode of the first transistor is connected to the control terminal of first buffer module, the first electric current of the first transistor Carrying electrode is connected to the first terminal of first buffer module.

Adjuster of the project 7. according to project 5, wherein, the buffer stage further includes feedback module, for offer pair The negative feedback control of voltage at the control terminal of the output module.

Adjuster of the project 8. according to project 7, wherein, the feedback module includes the second buffer module and second partially Circuits, second buffer module include second transistor, and the coordination electrode of the second transistor is connected to described first The Second terminal of buffer module, the first current carrying electrode of the second transistor are connected to the of first biasing circuit One end；Second biasing circuit includes third transistor, the 4th transistor and the 5th transistor, wherein：The third crystal The coordination electrode of pipe is connected to the first end of first biasing circuit, and the first current carrying electrode of the third transistor connects It is connected to supply voltage, the first electric current that the second current carrying electrode of the third transistor is connected to the 4th transistor is held Electrode is carried, the coordination electrode of the 4th transistor is connected to the coordination electrode of the 5th transistor and is connected to the described 4th First current carrying electrode of transistor, the second current carrying electrode of the 4th transistor are connected to low potential reference node Point, and the first current carrying electrode of the 5th transistor is connected to the second current load electricity of the first transistor Pole, the second current carrying electrode of the 5th transistor are connected to low potential reference mode.

Adjuster of the project 9. according to project 8, wherein：The second current carrying electrode connection of the second transistor To low potential reference mode.

Adjuster of the project 10. according to project 6, wherein：The Second terminal of first buffer module is connected to low Potential reference node；Second current carrying electrode of the first transistor is connected to the second end of first buffer module Son.

Adjuster of the project 11. according to project 7, the buffer stage further includes third buffer module, for measuring State the output current of output terminal output, and provide it is associated with the output current feed back to the feedback module, described the Three buffer modules have first terminal, Second terminal and control terminal, wherein：The control terminal of third buffer module is connected to The first end of one biasing circuit, the first terminal of third buffer module are connected to supply voltage, and the of third buffer module 4059 Two-terminal is connected to the first terminal of the second buffer module, is also attached to node.

Adjuster of the project 12. according to project 11, the third buffer module include the 6th transistor, wherein：Institute The coordination electrode for stating the 6th transistor is connected to the control terminal of the third buffer module, the first electricity of the 6th transistor Stream carrying electrode is connected to the first terminal of the third buffer module, and the second current carrying electrode of the 6th transistor connects The Second terminal of the third buffer module is connected to, the size of the 6th transistor is set and the biography in the output module The size of defeated transistor proportionally reduces.

Adjuster of the project 13. according to project 1, further includes：Feedback circuit is connected to the output terminal and described low Between potential reference node, for providing first feedback signal.

Adjuster of the project 14. according to project 1, wherein the buffer stage includes：First buffer part and for providing First biasing circuit of bias current, first buffer part include the first buffer module, the second buffer module, the 4th buffering mould Block, the first buffer part are configured as that the output impedance lower than the output impedance of amplifier 503 is presented, and the first buffer module is configured For source follower form, the second buffer module and the 4th buffer module are suitable for use as providing feedback to the anti-of the first buffer module Feeder diameter, the 4th buffer module are suitable for use as level shifter.

Adjuster of the project 15. according to project 14, wherein：Described in the control terminal of first buffer module receives Signal is controlled, the first terminal of first buffer module is connected to the first end of first biasing circuit and is connected to described The control terminal of 4th buffer module, the Second terminal of first buffer module are connected to the control of second buffer module Terminal；The first terminal of second buffer module is connected to the Second terminal of the 4th buffer module, and is connected to described The control terminal of output module；The second end of first biasing circuit is connected to the input terminal or supply voltage；Described The first terminal of four buffer modules is connected to the first end of first biasing circuit, and the 4th buffer module is by native transistors Pipe is formed.

The adjuster according to project 15 of project 16., wherein：First buffer module includes the first transistor, wherein The coordination electrode of the first transistor is connected to the control terminal of first buffer module, and the first of the first transistor Current carrying electrode is connected to the first terminal of first buffer module, the second current carrying electrode of the first transistor It is connected to the Second terminal of first buffer module；Second buffer module includes second transistor, wherein described second The coordination electrode of transistor is connected to the control terminal of second buffer module, the first current load of the second transistor Electrode is connected to the first terminal of second buffer module；4th buffer module includes the 7th transistor, wherein described The coordination electrode of 7th transistor is connected to the control terminal of the 4th buffer module, the first electric current of the 7th transistor Carrying electrode is connected to the first terminal of the 4th buffer module, wherein the 7th transistor is native transistor.

Adjuster of the project 17. according to project 14, the buffer stage further include the second buffer part, described for measuring The output current of output terminal output, and provide it is associated with the output current feed back to first buffer part, described the Two buffer parts include the 5th buffer module and current sense feedback circuit, and the 5th buffer module is for offer and the output current Associated information, current sense feedback circuit are used to provide for the 5th buffer module and the output stage essentially identical Bias voltage, and provide described information feedback to first buffer part.

Adjuster of the project 18. according to project 17, wherein：5th buffer module has first terminal, second Terminal and control terminal, wherein the control terminal of the 5th buffer module is connected to the first end of the second buffer module, the 5th The first terminal of buffer module is connected to the input terminal, and it is anti-that the Second terminal of the 5th buffer module is connected to the current sense Current feed circuit, the current sense feedback circuit include the first current mirror, pull-down module and sensing biasing module, wherein：Described First output terminal of one current mirror is connected to the first end of first biasing circuit, the second output terminal of first current mirror The pull-down module is connected to, the Liang Ge branches of the sensing biasing module are connected respectively to the second of first output module The Second terminal of terminal and the 5th buffer module；The sensing biasing module forms the second electric current with the pull-down circuit Mirror, the first input end of second current mirror are connected to the second output terminal of first current mirror, second current mirror The second input terminal be connected to the Second terminal of the 5th buffer module, and the third input terminal of second current mirror connects To the output terminal of the adjuster.

Adjuster of the project 19. according to project 17, the 5th buffer module include the 6th transistor, wherein：Institute The coordination electrode for stating the 6th transistor is connected to the control terminal of the 5th buffer module, the first electricity of the 6th transistor Stream carrying electrode is connected to the first terminal of the 5th buffer module, and the second current carrying electrode of the 6th transistor connects The Second terminal of the 5th buffer module is connected to, the size of the 6th transistor is set and the biography in the output module The size of defeated transistor proportionally reduces.

Adjuster of the project 20. according to project 1, further includes：Capacitive feedback circuit, be connected to the output terminal and Between the amplifier, for providing the second feedback signal associated with the output to the amplifier.

Adjuster of the project 21. according to project 1, wherein the amplifier includes：The first order, including first and second Input transistors and bias current sources, first and second input transistors receive the reference respectively by its coordination electrode Voltage and first feedback signal, the bias current sources are to the first current load of first and second input transistors Electrode provides biasing；The second level, including multiple transistors, the multiple transistor formation Liang Ge branches, described first and second Second current carrying electrode of input transistors is connected respectively to the node in the two branches.

Adjuster of the project 22. according to project 21, further includes：Capacitive feedback circuit is connected to the output terminal Between the amplifier, for providing the second feedback signal associated with the output to the amplifier, wherein described Second feedback signal is provided to the input transistors for not receiving the reference voltage in first and second input transistors The second current carrying electrode.

Adjuster of the project 23. according to project 1, further includes：Compensation circuit is connected to first buffer module Between control terminal and low potential reference mode, the compensation circuit has variable or programmable RC coefficients.

24. a kind of chip of project, including the adjuster as described in any one of project 1-23.

Be disclosed or can thus disclose can apparently obtain embodiment can include specific operation it is more A example, and operation order can be changed in other various embodiments.But others are changed, variations and alternatives are similary It is possible.Therefore, the specification and drawings should be counted as illustrative and not restrictive.

Although some specific embodiments of the disclosure are described in detail by example, the skill of this field Art personnel it should be understood that above example merely to illustrating rather than in order to limit the scope of the present disclosure.It is disclosed herein Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with A variety of modifications are carried out to embodiment without departing from the scope and spirit of the disclosure.The scope of the present disclosure is limited by appended claims It is fixed.

Claims

1. a kind of adjuster on chip, which is characterized in that including：

Input terminal, for receiving the power supply from chip exterior；

Output terminal, for providing power supply output；

Output module for receiving the power supply, and provides the power supply output, wherein the output module includes transmission crystal Pipe, the transmission transistor have coordination electrode capacitance, and the coordination electrode capacitance causes the adjuster in the frequency response Secondary pole is presented；

Amplifier receives reference voltage and the first feedback signal associated with power supply output, and provides to stablize The Regulate signal of the power supply output；

Buffer stage receives the Regulate signal, and provides control terminal of the control signal to the output module,

Wherein described buffer stage is configured as the output impedance lower than the output impedance of the amplifier being presented, and be configured as making The secondary pole is obtained except desired gain frequency range.

2. adjuster according to claim 1, which is characterized in that wherein：

The coordination electrode of the transmission transistor is connected to the control terminal of the output module,

First current carrying electrode of the transmission transistor is connected to the first terminal of the output module,

Second current carrying electrode of the transmission transistor is connected to the Second terminal of the output module.

3. adjuster according to claim 1, which is characterized in that wherein：

Desired gain is unit gain, and the desired gain frequency range is that wherein described adjuster has list under open loop The frequency range of position gain.

4. adjuster according to claim 1, which is characterized in that wherein：

The coordination electrode capacitance of the transmission transistor is configured as forming the transistor of the amplifier and the buffer stage The 10 of coordination electrode capacitance²Times or higher.

5. adjuster according to claim 1, which is characterized in that wherein described buffer stage includes：First buffer module and First biasing circuit of bias current is provided, wherein：

First buffer module has first terminal, Second terminal and control terminal,

The control terminal of first buffer module receives the Regulate signal, the first terminal connection of first buffer module To the first end of first biasing circuit, and it is connected to the control terminal of the output module；

The second end of first biasing circuit is connected to the input terminal or supply voltage.

6. adjuster according to claim 5, which is characterized in that first buffer module includes the first transistor, In：

The coordination electrode of the first transistor is connected to the control terminal of first buffer module, the first transistor First current carrying electrode is connected to the first terminal of first buffer module.

7. adjuster according to claim 5, which is characterized in that wherein, the buffer stage further includes feedback module, is used for Negative feedback control to the voltage at the control terminal of the output module is provided.

8. adjuster according to claim 7, which is characterized in that wherein, the feedback module includes the second buffer module With the second biasing circuit,

Second buffer module includes second transistor, and the coordination electrode of the second transistor is connected to first buffering The Second terminal of module, the first current carrying electrode of the second transistor are connected to the first of first biasing circuit End；

Second biasing circuit includes third transistor, the 4th transistor and the 5th transistor, wherein：

The coordination electrode of the third transistor is connected to the first end of first biasing circuit, and the of the third transistor One current carrying electrode is connected to supply voltage, and the second current carrying electrode of the third transistor is connected to the 4th crystalline substance First current carrying electrode of body pipe,

The coordination electrode of 4th transistor is connected to the coordination electrode of the 5th transistor and is connected to the 4th crystalline substance First current carrying electrode of body pipe, the second current carrying electrode of the 4th transistor are connected to low potential reference mode, And

First current carrying electrode of the 5th transistor is connected to the second current carrying electrode of the first transistor, institute The second current carrying electrode for stating the 5th transistor is connected to low potential reference mode.

9. adjuster according to claim 8, which is characterized in that wherein：

Second current carrying electrode of the second transistor is connected to low potential reference mode.

10. adjuster according to claim 6, which is characterized in that wherein：

The Second terminal of first buffer module is connected to low potential reference mode；

Second current carrying electrode of the first transistor is connected to the Second terminal of first buffer module.