CN108122901A - Integrated circuit - Google Patents

Integrated circuit Download PDF

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Publication number
CN108122901A
CN108122901A CN201710669088.XA CN201710669088A CN108122901A CN 108122901 A CN108122901 A CN 108122901A CN 201710669088 A CN201710669088 A CN 201710669088A CN 108122901 A CN108122901 A CN 108122901A
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China
Prior art keywords
unit
active area
functional
same parents
continuous active
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Granted
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CN201710669088.XA
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Chinese (zh)
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CN108122901B (en
Inventor
彭士玮
王中兴
陈志良
杨超源
曾健庭
邱奕勋
侯元德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN108122901A publication Critical patent/CN108122901A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/11868—Macro-architecture
    • H01L2027/11874—Layout specification, i.e. inner core region
    • H01L2027/11875—Wiring region, routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/11868—Macro-architecture
    • H01L2027/11874—Layout specification, i.e. inner core region
    • H01L2027/11881—Power supply lines

Abstract

A kind of integrated circuit includes substrate and the first group of function born of the same parents unit (functional cell unit) being formed on the substrate.Each function born of the same parents unit includes a pair of of functional unit with different threshold voltages and the fills unit (filler cell) between functional unit its described (functional cell).The number of the function born of the same parents unit in first group of function born of the same parents' unit is equal to or more than the number of second group of function born of the same parents' unit, and each second group of function born of the same parents unit includes having different threshold voltages and against each other a pair of of functional unit of (abut).Thus, the leakage current (leakage current) of the integrated circuit can be reduced.

Description

Integrated circuit
Technical field
There is fills unit the present embodiments relate to a kind of integrated circuit and its manufacturing method, and more particularly to one kind Integrated circuit and its manufacturing method.
Background technology
Standard block (standard cell) is widely used in the design of integrated circuit.Standard block has predetermined electricity It road function and is stored in cell library (cell library).In the during the design of integrated circuit, standard is captured from cell library Unit is simultaneously placed on desired position in layout.Then wiring (routing) is performed so that each standard block to be connected each other It connects.
The content of the invention
According to some embodiments of the present invention, a kind of integrated circuit includes substrate and first group of function born of the same parents' unit (functional cell unit).The function born of the same parents unit is formed on the substrate.Each first group of function born of the same parents are single Member include with different threshold voltages a pair of of functional unit (functional cell) and positioned at functional unit its described it Between fills unit (filler cell).The number of the function born of the same parents unit in first group of function born of the same parents' unit be equal to or The number of more than second group function born of the same parents' unit, each second group of function born of the same parents unit is including with different threshold voltages and each other Recline a pair of of functional unit of (abut).
Description of the drawings
Following detailed description is read in conjunction with the figure, various aspects of the invention may be best understood.It should be noted that according to one's own profession Standard convention in industry, various features are not necessarily drawn to scale.In fact, for the sake of discussing clearly, can arbitrarily increase or reduce The size of various features.
Fig. 1 shows the schematic diagram of Exemplary semiconductor element in accordance with some embodiments.
Fig. 2 shows the exemplary of the functional unit (functional cell) of semiconductor element in accordance with some embodiments The schematic diagram of layout.
Fig. 3 shows the schematic diagram of the exemplary layout of a pair of of functional unit of semiconductor element in accordance with some embodiments.
Fig. 4 shows the function born of the same parents unit (functional cell unit) of semiconductor element in accordance with some embodiments The schematic diagram of exemplary layout.
Fig. 5 shows the signal of the another exemplary layout of function born of the same parents' unit of semiconductor element in accordance with some embodiments Figure.
Fig. 6 shows the signal of the another exemplary layout of function born of the same parents' unit of semiconductor element in accordance with some embodiments Figure.
Fig. 7 shows the signal of the another exemplary layout of function born of the same parents' unit of semiconductor element in accordance with some embodiments Figure.
Fig. 8 shows the flow chart of the illustrative methods of manufacture semiconductor element in accordance with some embodiments.
Fig. 9 shows the flow chart of the another exemplary method of manufacture semiconductor element in accordance with some embodiments.
Drawing reference numeral explanation
100：Semiconductor element
110、120、130、140：Function born of the same parents' unit
110a、120b、140a、150、160、170：Standard voltage threshold (SVT) functional unit
110b、130a、140b：Low voltage threshold (LVT) functional unit
110c、120c、130c、180：Fills unit
120a、130b：Ultra low voltage threshold value (uLVT) functional unit
200、300、400、500、600、700：Layout
210、220、310、320、410、420、510、520、610、620、710、720：Power supply line
230、330、340、430、530、640：SVT transistors
230a、330a、340a、430a、440a、530a、540a、630a、640a、730a、740a：First source/drain Area
230b、330b、340b、430b、440b、530b、540b、630b、640b、730b、740b：Second source/drain Area
230c、330c、340c、430c、440c、530c、540c、630c、640c、730c、740c：Active gate electrode
260a、260b、360a、360b、360c、460a、460b、460c、560a、560b、560c、560d、660a、 660b、660c、660d、760b、760c、760d、760e、760f：Dummy gate electrode electrode
280、380a、380b、480a、480b、580a、580b、580c、680a、680b、680c、780a、780b、780c、 780d：Border
290、390、490、590、690、790：Substrate
440、540、730：LVT transistors
550、760a：Fill gate electrode
630、740：ULVT transistors
800、900：Method
810、820、830、910、920、930、940：Operation
CNOD：Continuous active area
D1、D2：Distance
Ileakage：Leakage current
P：Pitch
VDD：First supply voltage
VSS：Second supply voltage
Specific embodiment
Disclosure below provides many different embodiments or example of the different characteristic for implementation institute claimed subject matter. Component set forth below and the specific example of arrangement are to simplify present disclosure.Certainly, these are only that example and being not intended to is limited System.For example, below illustrate in by fisrt feature be formed in second feature " on " or second feature " on " may include wherein Fisrt feature and second feature are formed the embodiment contacted directly, and may also comprise wherein fisrt feature and second feature it Between can be formed with supplementary features, so that the embodiment that the fisrt feature and the second feature may be not directly contacted with. In addition, present disclosure may reuse Ref. No. and/or letter in various examples.This reuse is in order at letter Relation between various embodiments clean and that clearly purpose rather than itself expression are discussed and/or configuration.
In addition, for ease of explanation, such as " under (beneath) ", " following (below) ", " lower part may be used herein (lower) ", " top (above) ", the spaces relativity term such as " (upper) on top " illustrate one shown in figure Component or feature and another (other) component or the relation of feature.The space relativity term is intended to take except depicted in figure Outwards also include the different orientation of element in use or operation.Equipment can have other orientations (to be rotated by 90 ° or in other Orientation) and relativity description in space used herein equally can correspondingly explain.
Semiconductor element (for example, semiconductor element 100 in Fig. 1) includes multiple function born of the same parents unit (functional cell unit).Example illustrated in fig. 1 includes function born of the same parents unit 110, function born of the same parents unit 120, function born of the same parents unit 130 and function Born of the same parents' unit 140.Each function born of the same parents unit 110,120,130,140 includes having different threshold voltages (threshold Voltage a pair of of functional unit (functional cell)).Functional unit is performing predetermining circuit function.Citing comes Say, functional unit can implementation phase inverter (inverter), the phase inverter be configured to be from low reverse phase (invert) by signal Height, or vice versa.
As shown in Figure 1, function born of the same parents unit 110 include standard voltage threshold (standard voltage threshold, SVT) functional unit 110a and low voltage threshold (low voltage threshold, LVT) functional unit 110b.Function born of the same parents are single Member 120 includes ultra low voltage threshold value (ultra-low voltage threshold, uLVT) functional unit 120a and SVT function Unit 120b.Threshold voltage of the threshold voltage of LVT functional units less than SVT functional units but the threshold higher than uLVT functional units Threshold voltage.
Can perform series of process during the manufacture of semiconductor element has the function of different threshold voltages list to be formed First (such as functional unit shown in FIG. 1).For example, during the manufacture of such semiconductor element, first to wherein by shape Into the continuous active area (continuous for having the first functional unit (for example, SVT functional unit 140a of function born of the same parents unit 140) Active region) CNOD (for example, region across functional unit 140a, 140b of function born of the same parents unit 140) first end Part performs the first doping process.Then, to will wherein be formed with the second functional unit (for example, the LVT of function born of the same parents unit 140 Functional unit 140b) continuous active area the second end part perform the second doping process.First doping process is mixed with second General labourer's skill is performed with different concentration of dopant, so that the first functional unit has different threshold values from the second functional unit Voltage.Due to the first functional unit and the second functional unit against each other (abut), the first doping process and the second doping Technique may cause the first end part of continuous active area and the second end part unexpected pollution and have not just True concentration of dopant (for example, near junction of functional unit 140a, 140b).This can be formed in the first functional unit and Occurs the semiconductor element of high leakage current (leakage current) between two functional units.
Another a series of technique be can perform during the manufacture of semiconductor element to form the work(with different threshold voltages It can unit (such as functional unit shown in FIG. 1).For example, during the manufacture of such semiconductor element, first wherein To be formed with the first functional unit (for example, SVT functional unit 140a of function born of the same parents unit 140) continuous active area (for example, across The more region of functional unit 140a, 140b of function born of the same parents unit 140) first end part in transistor channel region on sink The first metal gates of product.Then, the second functional unit will be formed with wherein (for example, the LVT function lists of function born of the same parents unit 140 First 140b) continuous active area the second end part in transistor channel region on deposit the second metal gates.First gold medal Belong to grid and the second metal gates with different work function (work function) (for example, different materials, different-thickness, no The same number of plies or its combination) so that the first functional unit and the second functional unit have different threshold voltages.Due to the first work( Can unit and the second functional unit against each other, therefore it is described deposit the first metal gates may be to being made to the second metal gates Into unexpected pollution (and vice versa) with incorrect work function.This can be formed in the first functional unit and the second work( The semiconductor element of high leakage current can occur between unit.
The present invention provides the various exemplary of the semiconductor element (for example, semiconductor element 100) with low current leakage Embodiment.The semiconductor element includes multiple function born of the same parents units (functional cell unit), such as function born of the same parents' unit 110th, 120, one or more of 130.Each function born of the same parents unit 110,120,130 includes being filled unit (filler Cell a pair of of the functional unit (functional cell)) separated.For example, function born of the same parents unit 110 includes SVT functions Unit 110a and LVT functional unit 110b and the filling list between SVT functional unit 110a and LVT functional units 110b First 110c.It is such when the end sections to continuous active area perform more dopant technique (multi-dopant process) Fills unit can be such that the pollution of the respective end part of the continuous active area substantially minimizes (even if cannot completely eliminate).
Fig. 1 shows the schematic diagram of Exemplary semiconductor element 100 in accordance with some embodiments.As shown in Figure 1, semiconductor element Part 100 (for example, application specific integrated circuit (application specific integrated circuit, ASIC)) quilt It is divided into multiple rows.Include multiple functional units with different threshold voltages, such as the uLVT functions in the first row per a line Unit 120a, SVT functional unit 120b and LVT functional unit 140b.Functional unit is described pre- to perform predetermining circuit function Determining circuit function includes cloth woods logical function (Boolean logic function) (for example, phase inverter).In some embodiments In, functional unit include NOT gate (NOT gate), with door (AND gate), NAND gate (NAND gate), OR gate (OR gate), Nor gate (NOR gate), XOR gate (XOR gate), same to OR gate (XNOR gate), another logic gate or its combination.Such work( Therefore energy unit can be referred to as standard block.In other embodiments, functional unit includes logic gate and passive/active component, For example, resistor, capacitor, inductor, transistor, diode or similar assembly.
Semiconductor element 100 further comprise having same threshold voltage and against each other a pair of of functional unit (for example, SVT functional units 150,160).Since the functional unit has same threshold voltage, between each functional unit Leakage current is small or insignificant.Thus, it may not include fills unit between these functional units.However, In other situations, it may be present between a pair of of functional unit (for example, SVT functional units 160,170) with same threshold voltage Fills unit (for example, fills unit 180), for example to fill the gap between the functional unit.
Semiconductor element 100 further comprises multiple function born of the same parents units 110,120,130,140.It should be noted that herein The function born of the same parents unit at place includes a pair of of functional unit with different threshold voltages.For example, as shown in Figure 1, function born of the same parents are single Member 110 includes SVT functional unit 110a and LVT functional units 110b.Function born of the same parents unit 120 include uLVT functional units 120a and SVT functional units 120b.Function born of the same parents unit 130 includes LVT functional unit 130a and uLVT functional units 130b.Function born of the same parents' unit 140 include SVT functional unit 140a and LVT functional units 140b.
Function born of the same parents' unit may include independent functional unit.For example, as shown in Figure 1, function born of the same parents unit 110 includes position Fills unit 110c between SVT functional unit 110a and LVT functional units 110b.Function born of the same parents unit 120 further comprises Fills unit 120c between uLVT functional unit 120a and SVT functional units 120b.Function born of the same parents unit 130 further wraps Include the fills unit 130c between LVT functional unit 130a and uLVT functional units 130b.
Function born of the same parents' unit may include the functional unit to recline.For example, as shown in Figure 1, the SVT of function born of the same parents unit 140 Functional unit 140a and LVT functional units 140b is against each other.It is present with high-leakage electricity between functional unit 140a, 140b Stream.Thus, semiconductor element 100 may include or may not include this kind of function born of the same parents' unit.
In some embodiments, have the function of that the number of independent functional unit born of the same parents' unit is equal to or more than have to recline Functional unit function born of the same parents' unit number.In other words, there is the number pair of independent functional unit born of the same parents' unit The number that there is independent functional unit born of the same parents' unit and the number with the functional unit born of the same parents' unit to recline The ratio of sum is in the range of 0.5 to 1.This can be such that the leakage current of semiconductor element 100 decreases below with lower semiconductor The leakage current of element：The number of the functional unit born of the same parents' unit for having the function of to recline of the semiconductor element, which is more than, to be had solely The number of function born of the same parents' unit of vertical functional unit.In some described embodiments, semiconductor element 100 with the work(to recline The number of function born of the same parents' unit of energy unit can be or can be not zero.
In other embodiments, there is the number of independent functional unit born of the same parents' unit to having the function of independent list Member function born of the same parents' unit number and have the function of the number of the functional unit born of the same parents' unit to recline and ratio between about 0.6 To in the range of about 1.0, about 0.7 to about 1.0, about 0.8 to about 1.0 or about 0.9 to about 1.0.This can be by semiconductor element 100 Leakage current decrease below the leakage current of following semiconductor element：The semiconductor element has the function of independent list The number of function born of the same parents' unit of member is equal to the number with the functional unit born of the same parents' unit to recline.In the other embodiment In, the number of the functional unit born of the same parents' unit for having the function of to recline of semiconductor element 100 can be or can be not zero.
Fig. 2 shows the functional unit of semiconductor element in accordance with some embodiments (for example, the SVT work(of semiconductor element 100 Can unit 150) exemplary layout 200 schematic diagram.Semiconductor element 100 includes having continuous active area CNOD (i.e., continuously Oxide defines (oxide definition, OD) area) substrate 290.
SVT functional units 150 impaled by border (as shown in dotted line 280) (enclosed) and including power supply line 210, 220.Power supply line 210 is receiving the first supply voltage, such as VDD.Power supply line 220 is supplied to receive than first The second low supply voltage of voltage, such as VSS.
SVT functional units 150 further comprise being field-effect transistor (field-effect in this embodiment Transistor, FET) (for example, p-type or n-type metal oxide semiconductor field-effect transistor (metal-oxide- Semiconductor FET, MOSFET)) SVT transistors 230.Continuously have as shown in Fig. 2, SVT transistors 230 include being located at The first source/drain regions 230a and the second source/drain regions 230b on source region CNOD, positioned at the first source/drain regions 230a Channel region (invisible) between the second source/drain regions 230b and positioned at the active gate electrode its described on channel region 230c。
SVT functional units 150 further comprise the dummy gate electrode electrode for being respectively arranged at 280 left side of border and right side 260a、260b.In this embodiment, dummy gate electrode electrode 260a, 260b are coupled by horizontal metal wire and/or vertical metal line (that is, connect) is to power supply line 210.In an alternative embodiment, one of dummy gate electrode electrode 260a, 260b are connected to Power supply line 220.
Fig. 3 shows a pair of of functional unit of semiconductor element in accordance with some embodiments (for example, semiconductor element 100 The schematic diagram of SVT functional units 150, exemplary layout 300 160).Semiconductor element 100 includes having continuous active area The substrate 390 of CNOD.Continuous active area CNOD includes opposite first end part with the second end part and positioned at its institute State the center section between first end part and the second end part.
SVT functional units 150,160 have same threshold voltage and against each other.SVT functional units 150 by border (by Shown in dotted line 380a) it impales.SVT functional units 150 are arranged in the first end part of continuous active area CNOD and including electricity Source supply line 310,320.Power supply line 310 is receiving the first supply voltage, such as VDD.Power supply line 320 is connecing Receive the second supply voltage lower than the first supply voltage, such as VSS.
SVT functional units 150 further comprise brilliant for the SVT of FET (for example, p-type or n-type MOSFET) in this embodiment Body pipe 330.As shown in figure 3, SVT transistors 330 include the first source on the first end part of continuous active area CNOD Pole/drain region 330a and the second source/drain regions 330b, positioned at the first source/drain regions 330a and the second source/drain regions Channel region (invisible) between 330b and positioned at the active gate electrode 330c its described on channel region.
SVT functional units 160 are impaled by border (as shown in dotted line 380b).SVT functional units 160 are arranged at continuous active Power supply line 310,320 is shared in the second end part of area CNOD and with SVT functional units 150.
SVT functional units 160 further comprise brilliant for the SVT of FET (for example, p-type or n-type MOSFET) in this embodiment Body pipe 340.As shown in Figure 3, SVT transistors 340 include first on the second end part of continuous active area CNOD Source/drain regions 340a and the second source/drain regions 340b, positioned at the first source/drain regions 340a and the second source/drain regions Channel region (invisible) between 340b and positioned at the active gate electrode 340c its described on channel region.
SVT functional units 150 further comprise being arranged at the dummy gate electrode electrode 360a on the left of the 380a of border.SVT functions Unit 160 further comprises being arranged at the dummy gate electrode electrode 360b on the right side of the 380b of border.SVT functional units 150,160 are shared It is arranged at the dummy gate electrode electrode 360c of the interface of border 380a, 380b.
In this embodiment, dummy gate electrode electrode 360a, 360b, 360c pass through horizontal metal wire and/or vertical metal line Couple and (that is, connect) to power supply line 310.In an alternative embodiment, in dummy gate electrode electrode 360a, 360b, 360c At least one is connected to power supply line 320.
It should be noted that dummy gate electrode electrode 360c, the second source/drain regions 330b and the first source/drain regions 340a Parasitic transistor (parasitic transistor) can be formed together.Thus, between SVT functional units 150,160 It is likely to occur leakage current Ileakage.However, since SVT functional units 150,160 have same threshold voltage, it is such to let out Leakage current IleakageFor small (that is, insignificant).This is because SVT functional units 150,160 are by with identical dopant Concentration performs doping process (or by depositing the metal gates with identical work function) to be formed.
Fig. 4 shows a pair of of functional unit of semiconductor element in accordance with some embodiments (for example, semiconductor element 100 SVT functional unit 140a and LVT functional unit 140b) exemplary layout 400 schematic diagram.Semiconductor element 100 includes tool There is the substrate 490 of continuous active area CNOD.Continuous active area CNOD includes opposite first end part and the second end part And the center section between first end part its described and the second end part.
SVT functional units 140a and LVT functional units 140b have different threshold voltages and against each other.SVT function lists First 140a is impaled by border (as shown in dotted line 480a).SVT functional units 140a is arranged at the first end of continuous active area CNOD In portion part and including power supply line 410,420.Power supply line 410 is receiving the first supply voltage, such as VDD.Electricity Source supply line 420 supplies voltage, such as VSS to receive second lower than the first supply voltage.
SVT functional units 140a further comprises in this embodiment for the SVT of FET (for example, p-type or n-type MOSFET) Transistor 430.As shown in figure 4, SVT transistors 430 include first on the first end part of continuous active area CNOD Source/drain regions 430a and the second source/drain regions 430b, positioned at the first source/drain regions 430a and the second source/drain regions Channel region (invisible) between 430b and positioned at the active gate electrode 430c its described on channel region.
LVT functional units 140b is impaled by border (as shown in dotted line 480b).LVT functional units 140b, which is arranged at, continuously to be had Power supply line 410,420 is shared in the second end part of source region CNOD and with SVT functional units 140a.
LVT functional units 140b further comprises in this embodiment for the LVT of FET (for example, p-type or n-type MOSFET) Transistor 440.As shown in figure 4, LVT transistors 440 include first on the second end part of continuous active area CNOD Source/drain regions 440a and the second source/drain regions 440b, positioned at the first source/drain regions 440a and the second source/drain regions Channel region (invisible) between 440b and positioned at the active gate electrode 440c its described on channel region.
SVT functional units 140a further comprises being arranged at the dummy gate electrode electrode 460a on the left of the 480a of border.LVT functions Unit 140b further comprises being arranged at the dummy gate electrode electrode 460b on the right side of the 480b of border.SVT functional units 140a and LVT work( Energy unit 140b shares the dummy gate electrode electrode 460c for the interface for being arranged at border 480a, 480b.
In this embodiment, dummy gate electrode electrode 460a, 460b, 460c pass through horizontal metal wire and/or vertical metal line Couple and (that is, connect) to power supply line 410.In an alternative embodiment, in dummy gate electrode electrode 460a, 460b, 460c At least one is connected to power supply line 420.
It should be noted that dummy gate electrode electrode 460c, the second source/drain regions 430b and the first source/drain regions 440a Parasitic transistor can be formed together.Thus, it is likely to occur between SVT functional unit 140a and LVT functional units 140b High leakage current Ileakage.This is because SVT functional units 140a and LVT functional units 140b is by dense with different dopant Degree performs doping process (or by depositing the metal gates with different work functions) to be formed.As described above, the doping work Skill (or described deposited metal grid) may cause the first end part of continuous active area CNOD and the second end part Unexpected pollution and with incorrect concentration of dopant (or the gold to SVT functional unit 140a and LVT functional units 140b Belong to grid to cause unexpected pollution and there is incorrect work function).
In an alternative embodiment, semiconductor element does not include function born of the same parents unit (that is, function born of the same parents unit 140), the work( Energy born of the same parents unit includes a pair of of functional unit with different threshold voltages and against each other.
Fig. 5 shows the function born of the same parents unit of semiconductor element in accordance with some embodiments (for example, the work(of semiconductor element 100 Can born of the same parents unit 110) exemplary layout 500 schematic diagram.Semiconductor element 100 includes the substrate with continuous active area CNOD 590.Continuous active area CNOD includes opposite first end part with the second end part and positioned at first end its described Center section between part and the second end part.
Function born of the same parents unit 110 includes SVT functional units 110a and LVT functional unit 110b and fills unit 110c.SVT Functional unit 110a is impaled by border (as shown in dotted line 580a).SVT functional units 110a is arranged at continuous active area CNOD's In first end part and including power supply line 510,520.Power supply line 510 receiving the first supply voltage, such as VDD.Power supply line 520 supplies voltage, such as VSS to receive second lower than the first supply voltage.
SVT functional units 110a further comprises in this embodiment for the SVT of FET (for example, p-type or n-type MOSFET) Transistor 530.As shown in figure 5, SVT transistors 530 include first on the first end part of continuous active area CNOD Source/drain regions 530a and the second source/drain regions 530b, positioned at the first source/drain regions 530a and the second source/drain regions Channel region (invisible) between 530b and positioned at the active gate electrode 530c its described on channel region.
LVT functional units 110b is impaled by border (as shown in dotted line 580b).LVT functional units 110b, which is arranged at, continuously to be had Power supply line 510,520 is shared in the second end part of source region CNOD and with SVT functional units 110a.
LVT functional units 110b further comprises in this embodiment for the LVT of FET (for example, p-type or n-type MOSFET) Transistor 540.As shown in figure 5, LVT transistors 540 include first on the second end part of continuous active area CNOD Source/drain regions 540a and the second source/drain regions 540b, positioned at the first source/drain regions 540a and the second source/drain regions Channel region (invisible) between 540b and positioned at the active gate electrode 540c its described on channel region.
In some embodiments, the first end part of continuous active area CNOD has different mix from the second end part Thus miscellaneous agent concentration allows SVT functional units 110a and LVT functional units 110b to have different threshold voltages.In other implementations In example, SVT transistors 530 have different work functions from LVT transistors 540, so that SVT functional units 110a and LVT Functional unit 110b can have different threshold voltages.
Fills unit 110c is impaled (as shown in dotted line 580c) by border and is arranged at the middle part of continuous active area CNOD Office (that is, between SVT functional units 110a and LVT functional unit 110b).The center section of continuous active area CNOD do not couple/ It is connected to power supply line 510/520 or arbitrary signal generator.In this embodiment, fills unit 110c includes filling gate electrode (filler gate electrode)550.As shown in figure 5, filling gate electrode 550 be float (floating), i.e., not with Power supply line 510/520 connects.In an alternative embodiment, fill gate electrode 550 and pass through horizontal metal wire and/or vertical Metal wire couples and (that is, connects) to power supply line 510/520.
Although function born of the same parents unit 110, which is illustrated as fills unit 110c, includes single filling gate electrode 550, filling Unit 110c can optionally include any number of filling gate electrode 550.
SVT functional units 110a further comprises being arranged at the dummy gate electrode electrode 560a on the left of the 580a of border.LVT functions Unit 110b further comprises being arranged at the dummy gate electrode electrode 560b on the right side of the 580b of border.SVT functional units 110a and filling Unit 110c shares the dummy gate electrode electrode 560c for the interface for being arranged at border 580a, 580c.LVT functional units 110b is with filling out Fill the dummy gate electrode electrode 560d that unit 110c shares the interface for being arranged at border 580b, 580c.
In this embodiment, dummy gate electrode electrode 560a, 560b, 560c, 560d pass through horizontal metal wire and/or vertical gold Belong to line connection (that is, connecting) to power supply line 510.In an alternative embodiment, dummy gate electrode electrode 560a, 560b, 560c, At least one of 560d is connected to power supply line 520.
It should be noted that dummy gate electrode electrode 560c, 560d, the second source/drain regions 530b and the first source/drain regions 540a can form parasitic transistor together.It thus, may between SVT functional unit 110a and LVT functional units 110b There is leakage current Ileakage.However, since fills unit 110c is by SVT functional units 110a and LVT functional units 110b points It separates, therefore such leakage current IleakageIt can be reduced.This is because SVT functional units 110a and LVT functional units 110b It is to be formed by performing doping process (or by depositing the metal gates with different work functions) with different dopant concentration. As described above, the doping process (or described deposited metal grid) may be to the first end part of continuous active area CNOD And the second end part cause unexpected pollution and with incorrect concentration of dopant (or to SVT functional units 110a and The metal gates of LVT functional units 110b cause unexpected pollution and have incorrect work function).Fills unit 110c meetings Minimize such unexpected pollution.
As shown in figure 5, gate electrode 530c, 540c, 550,560a, 560b, 560c, 560d are with pitch (pitch) P progress Arrangement.By SVT functional units 110a and fills unit 110c the dummy gate electrode electrode 560c shared and by LVT functional units 110b The dummy gate electrode electrode 560d shared with fills unit 110c is arranged with distance D1.In this embodiment, distance D1 is to section Ratio away from P is substantially equal to 2.
Fig. 6 shows the function born of the same parents unit of semiconductor element in accordance with some embodiments (for example, the work(of semiconductor element 100 Can born of the same parents unit 120) exemplary layout 600 schematic diagram.Semiconductor element 100 includes the substrate with continuous active area CNOD 690.Continuous active area CNOD includes opposite first end part with the second end part and positioned at first end its described Center section between part and the second end part.
Function born of the same parents unit 120 includes uLVT functional units 120a, SVT functional unit 120b and fills unit 120c. ULVT functional units 120a is impaled by border (as shown in dotted line 680a).ULVT functional units 120a is arranged at continuous active area In the first end part of CNOD and including power supply line 610,620.Power supply line 610 is electric to receive the first supply Pressure, such as VDD.Power supply line 620 supplies voltage, such as VSS to receive second lower than the first supply voltage.
ULVT functional units 120a further comprises in this embodiment for FET's (for example, p-type or n-type MOSFET) ULVT transistors 630.As shown in fig. 6, uLVT transistors 630 are included on the first end part of continuous active area CNOD First source/drain regions 630a and the second source/drain regions 630b, positioned at the first source/drain regions 630a and the second source/drain Channel region (invisible) between polar region 630b and positioned at the active gate electrode 630c its described on channel region.
SVT functional units 120b is impaled by border (as shown in dotted line 680b).SVT functional units 120b, which is arranged at, continuously to be had Power supply line 610,620 is shared in the second end part of source region CNOD and with uLVT functional units 120a.
SVT functional units 120b further comprises in this embodiment for the SVT of FET (for example, p-type or n-type MOSFET) Transistor 640.As shown in fig. 6, SVT transistors 640 include first on the second end part of continuous active area CNOD Source/drain regions 640a and the second source/drain regions 640b, positioned at the first source/drain regions 640a and the second source/drain regions Channel region (invisible) between 640b and positioned at the active gate electrode 640c its described on channel region.
In some embodiments, the first end part of continuous active area CNOD has different mix from the second end part Thus miscellaneous agent concentration allows uLVT functional units 120a and SVT functional units 120b to have different threshold voltages.In other implementations In example, uLVT transistors 630 and SVT transistors 640 have different work functions so that uLVT functional units 120a and SVT functional units 120b can have different threshold voltages.
Fills unit 120c is impaled (as shown in dotted line 680c) by border and is arranged at the middle part of continuous active area CNOD Office (that is, between uLVT functional units 120a and SVT functional unit 120b).The center section of continuous active area CNOD does not join Connect/be connected to power supply line 610/620 or arbitrary signal generator.In this embodiment, fills unit 120c does not have filling grid Pole electrode (for example, filling gate electrode 550 shown in Fig. 5).
ULVT functional units 120a further comprises being arranged at the dummy gate electrode electrode 660a on the left of the 680a of border.SVT work( Energy unit 120b further comprises being arranged at the dummy gate electrode electrode 660b on the right side of the 680b of border.ULVT functional units 120a is with filling out Fill the dummy gate electrode electrode 660c that unit 120c shares the interface for being arranged at border 680a, 680c.SVT functional units 120b with Fills unit 120c shares the dummy gate electrode electrode 660d for the interface for being arranged at border 680b, 680c.
In this embodiment, dummy gate electrode electrode 660a, 660b, 660c, 660d pass through horizontal metal wire and/or vertical gold Belong to line connection (that is, connecting) to power supply line 610.In an alternative embodiment, dummy gate electrode electrode 660a, 660b, 660c, At least one of 660d is connected to power supply line 620.
It should be noted that dummy gate electrode electrode 660c, 660d, the second source/drain regions 630b and the first source/drain regions 640a can form parasitic transistor together.It thus, may between uLVT functional unit 120a and SVT functional units 120b There is leakage current Ileakage.However, since fills unit 120c is by uLVT functional units 120a and SVT functional units 120b points It separates, therefore such leakage current IleakageIt can be reduced.This is because uLVT functional units 120a and SVT functional units 120b It is to be formed by performing doping process (or by depositing the metal gates with different work functions) with different dopant concentration. As described above, the doping process (or described deposited metal grid) may be to the first end part of continuous active area CNOD And the second end part cause unexpected pollution and with incorrect concentration of dopant (or to uLVT functional units 120a and The metal gates of SVT functional units 120b cause unexpected pollution and have incorrect work function).Fills unit 120c meetings Minimize such unexpected pollution.
As shown in fig. 6, gate electrode 630c, 640c, 660a, 660b, 660c, 660d are arranged with pitch P.By uLVT Dummy gate electrode electrode 660c that functional unit 120a and fills unit 120c share and by SVT functional units 120b and fills unit The dummy gate electrode electrode 660d that 120c shares is arranged with distance D2.In this embodiment, distance D2 is real to the ratio of pitch P It is equal to 1 in matter.
Fig. 7 shows the function born of the same parents unit of semiconductor element in accordance with some embodiments (for example, semiconductor element shown in Fig. 1 100 function born of the same parents unit 130) exemplary layout 700 schematic diagram.Semiconductor element 100 includes having continuous active area The substrate 790 of CNOD.Continuous active area CNOD includes opposite first end part with the second end part and positioned at its institute State the center section between first end part and the second end part.
Function born of the same parents unit 130 includes LVT functional units 130a, uLVT functional unit 130b and fills unit 130c.LVT Functional unit 130a is impaled by border (as shown in dotted line 780a).LVT functional units 130a is arranged at continuous active area CNOD's In first end part and including power supply line 710,720.Power supply line 710 receiving the first supply voltage, such as VDD.Power supply line 720 supplies voltage, such as VSS to receive second lower than the first supply voltage.
LVT functional units 130a further comprises in this embodiment for the LVT of FET (for example, p-type or n-type MOSFET) Transistor 730.As shown in fig. 7, LVT transistors 730 include first on the first end part of continuous active area CNOD Source/drain regions 730a and the second source/drain regions 730b, positioned at the first source/drain regions 730a and the second source/drain regions Channel region (invisible) between 730b and positioned at the active gate electrode 730c its described on channel region.
ULVT functional units 130b is impaled by border (as shown in dotted line 780b).ULVT functional units 130b is arranged at continuously Power supply line 710,720 is shared in the second end part of active area CNOD and with LVT functional units 130a.
ULVT functional units 130b further comprises in this embodiment for FET's (for example, p-type or n-type MOSFET) ULVT transistors 740.As shown in fig. 7, uLVT transistors 740 are included on the second end part of continuous active area CNOD First source/drain regions 740a and the second source/drain regions 740b, positioned at the first source/drain regions 740a and the second source/drain Channel region (invisible) between polar region 740b and positioned at the active gate electrode 740c its described on channel region.
In some embodiments, the first end part of continuous active area CNOD has different mix from the second end part Thus miscellaneous agent concentration allows LVT functional units 130a and uLVT functional units 130b to have different threshold voltages.In other implementations In example, LVT transistors 730 and uLVT transistors 740 have different work functions so that LVT functional units 130a and ULVT functional units 130b can have different threshold voltages.
Fills unit 130c is a pair of of fills unit (for example, the filling shown in fills unit 110c shown in Fig. 5 and Fig. 6 Unit 120c) combination.Fills unit 130c is impaled (as shown in dotted line 780c) by border and is arranged at continuous active area CNOD Center section in (that is, between LVT functional units 130a and fills unit 110c).Fills unit 110c is by border (by dotted line Shown in 780d) it impales.Fills unit 110c includes filling gate electrode 760a and is arranged at the middle part of continuous active area CNOD In point (that is, between uLVT functional units 130b and fills unit 120c).The center section of continuous active area CNOD does not couple/connects It is connected to power supply line 710/720 or arbitrary signal generator.
LVT functional units 130a further comprises being arranged at the dummy gate electrode electrode 760b on the left of the 780a of border.ULVT work( Energy unit 130b further comprises being arranged at the dummy gate electrode electrode 760c on the right side of the 780b of border.LVT functional units 130a is with filling out Fill the dummy gate electrode electrode 760d that unit 120c shares the interface for being arranged at border 780a, 780c.ULVT functional units 130b The dummy gate electrode electrode 760e for the interface for being arranged at border 780b, 780d is shared with fills unit 110c.Fills unit 110c, 120c shares the dummy gate electrode electrode 760f for the interface for being arranged at border 780c, 780d.
In this embodiment, dummy gate electrode electrode 760b, 760c, 760d, 760e, 760f by horizontal metal wire and/or Vertical metal line couples and (that is, connects) to power supply line 710.In an alternative embodiment, dummy gate electrode electrode 760b, At least one of 760c, 760d, 760e, 760f are connected to power supply line 720.
It should be noted that dummy gate electrode electrode 760d, 760e, 760f, the second source/drain regions 730b and the first source electrode/ Drain region 740a can form parasitic transistor together.Thus, LVT functional units 130a and uLVT functional units 130b it Between be likely to occur leakage current Ileakage.However, since fills unit 130c is by LVT functional units 130a and uLVT functional units 130b is separated, therefore such leakage current IleakageIt can be reduced.This is because LVT functional units 130a and uLVT function lists First 130b is by performing doping process (or by depositing the metal gates with different work functions) with different dopant concentration And it is formed.As described above, the doping process (or described deposited metal grid) may be to the first of continuous active area CNOD End sections and the second end part cause unexpected pollution and have the function of that incorrect concentration of dopant is (or mono- to LVT The metal gates of first 130a and uLVT functional units 130b cause unexpected pollution and have incorrect work function).Filling Unit 130c can minimize such unexpected pollution.
As shown in fig. 7, gate electrode 730c, 740c, 760a, 760b, 760c, 760d, 760e, 760f are carried out with pitch P Arrangement.By uLVT functional units 130b and fills unit 110c the dummy gate electrode electrode 760e shared and by fills unit 110c, The dummy gate electrode electrode 760f that 120c shares is arranged with distance D1.Distance D1 is substantially equal to 2 to the ratio of pitch P.By The dummy gate electrode electrode 760d and shared by fills unit 110c, 120c that LVT functional units 130a is shared with fills unit 120c Dummy gate electrode electrode 760f arranged with distance D2.Distance D2 is substantially equal to 1 to the ratio of pitch P.
Fig. 8 shows the flow chart of the method 800 of manufacture semiconductor element in accordance with some embodiments.Although method 800 can Applied to many different structures, however it is illustrated to help to understand as example herein with reference to Fig. 1 and Fig. 5 to Fig. 7.It is operating In 810, the substrate of the semiconductor element with first group of continuous active area (for example, continuous active area CNOD) is provided (for example, half The substrate of conductor element 100).Continuous active area in each first group of continuous active area includes opposite first end portion Divide with the second end part (for example, continuous active area CNOD's is wherein respectively formed with SVT functional unit 110a and LVT functions Unit 110b, uLVT functional unit 120a and SVT functional unit 120b or LVT functional unit 130a and uLVT functional unit The first end part of 130b and the second end part) and positioned at first end part its described and the second end part Between center section (for example, continuous active area CNOD's is formed with fills unit 110c, fills unit 120c or fills out Fill the center section of unit 130c).
In operation 820, filling is defined in the center section of each continuous active area in first group of continuous active area Unit (for example, fills unit 110c, fills unit 120c or fills unit 130c).In certain embodiments, operation is performed 820 so that the number of the continuous active area in first group of continuous active area is equal to or more than the number of second group of continuous active area, Each second group of continuous active area includes first end part and the second end part against each other.In other words, hold Row operation 820 so that the number of the continuous active area in first group of continuous active area is to continuous in first group of continuous active area The number of active area and the number of the continuous active area in second group of continuous active area and ratio between about 0.5 to about 1 In the range of.In other embodiments, operation 820 is performed so that the number pair of the continuous active area in first group of continuous active area The number of continuous active area in first group of continuous active area and the number of the continuous active area in second group of continuous active area The ratio of sum is in the range of about 0.6 to about 1.0, about 0.7 to about 1.0, about 0.8 to about 1.0 or about 0.9 to about 1.0.
In operation 830, each continuous active area is doped with such as n-type or p-type dopant so that its first end Portion part has different concentration of dopant from the second end part.In this embodiment, operation 830 includes：Shape on substrate Into the first mask layer；By the first mask patterns to form the first opening, and the first end part of continuous active area is by institute The first opening is stated to expose；The first end part of continuous active area is mixed with the first concentration of dopant by the opening It is miscellaneous；Divest the first mask layer；The second mask layer is formed on substrate；By the second mask patterns to form the second opening, and The second end part of continuous active area is exposed by the described second opening；By second opening with the first concentration of dopant not The second same concentration of dopant is doped the second end part of continuous active area；And divest the second mask layer.
Due to defining fills unit in operation 820, operation 830 will not be to the first end part of continuous active area And the second end part causes unexpected pollution and has incorrect concentration of dopant.
Method 800 further comprises：Formed in the first end part of continuous active area the first functional unit (for example, SVT functional unit 110a, uLVT functional unit 120a or LVT functional unit 130a)；And the second end in continuous active area The second functional unit is formed in portion part (for example, LVT functional unit 110b, SVT functional unit 120b or uLVT functional units 130b)。
Due to operation 830 in different concentration of dopant to the first end part of continuous active area and the second end Part is doped, therefore the first functional unit and the second functional unit will have different threshold voltages.
Fig. 9 shows the flow chart of the method 900 of manufacture semiconductor element in accordance with some embodiments.Although method 900 can Applied to many different structures, however it is illustrated to help to understand as example herein with reference to Fig. 1 and Fig. 5 to Fig. 7.It is operating In 910, the substrate of the semiconductor element with first group of continuous active area (for example, continuous active area CNOD) is provided (for example, half The substrate of conductor element 100).Continuous active area in each first group of continuous active area includes opposite first end portion Divide with the second end part (for example, continuous active area CNOD's is wherein respectively formed with SVT functional unit 110a and LVT functions Unit 110b, uLVT functional unit 120a and SVT functional unit 120b or LVT functional unit 130a and uLVT functional unit The first end part of 130b and the second end part) and positioned at first end part its described and the second end part Between center section (for example, continuous active area CNOD's is formed with fills unit 110c, fills unit 120c or fills out Fill the center section of unit 130c).
In operation 920, filling is defined in the center section of each continuous active area in first group of continuous active area Unit (for example, fills unit 110c, fills unit 120c or fills unit 130c).In certain embodiments, operation is performed 920 so that the number of the continuous active area in first group of continuous active area is equal to or more than the number of second group of continuous active area, Each second group of continuous active area includes first end part and the second end part against each other.In other words, hold Row operation 920 so that the number of the continuous active area in first group of continuous active area is to continuous in first group of continuous active area The number of active area and the number of the continuous active area in second group of continuous active area and ratio between about 0.5 to about 1 In the range of.In other embodiments, operation 920 is performed so that the number pair of the continuous active area in first group of continuous active area The number of continuous active area in first group of continuous active area and the number of the continuous active area in second group of continuous active area The ratio of sum is in the range of about 0.6 to about 1.0, about 0.7 to about 1.0, about 0.8 to about 1.0 or about 0.9 to about 1.0.
In operation 930, the first functional unit is formed in the first end part of each continuous active area (for example, work( Energy unit 110a, functional unit 120a or functional unit 130a).In this embodiment, operation 930 includes：In continuous active area First end part in define first source/drain of transistor (for example, transistor 530, transistor 630 or transistor 730) Polar region, the second source/drain regions and channel region；Depositing gate dielectric matter is (for example, high K dielectric matter over the channel region (high-K dielectric))；First metal gates of the deposition with the first work function on gate dielectric；And Active gate electrode is deposited on one metal gates.
In operation 940, the second functional unit is formed in the second end part of each continuous active area (for example, work( Energy unit 110b, functional unit 120b or functional unit 130b).In this embodiment, operation 940 includes：In continuous active area The second end part in define first source/drain of transistor (for example, transistor 540, transistor 640 or transistor 740) Polar region, the second source/drain regions and channel region；Depositing gate dielectric matter is (for example, high K dielectric over the channel region Matter)；Second metal gates of the deposition with second work function different from the first work function on gate dielectric；And Active gate electrode is deposited on two metal gates.
Since the first metal gates deposited in operation 930,940 have different work functions from the second metal gates, Therefore the first functional unit and the second functional unit will have different threshold voltages in these operations.Further, since it is operating Fills unit is defined in 920, therefore operates 930,940 to cause transistor unexpected pollution and there is incorrect work content Number.
Although fills unit may increase the area of semiconductor element, such increased influence can pass through execution pair Wiring technique that each functional unit of semiconductor element is attached mitigates, and the wiring technique is for semiconductor element The combination of the leakage current of power consumption, the area of semiconductor element and semiconductor element optimizes rather than such as traditional wiring work It is the same in skill to be optimized only for power consumption.
As described above, the semiconductor element of the embodiment of the present invention includes multiple function born of the same parents units, each function Born of the same parents' unit includes a pair of of functional unit with different threshold voltages and the fills unit between functional unit its described. Compared with conventional semiconductors element, such construction can make the leakage current of semiconductor element be reduced by about 14% to about 17%.
In some embodiments, a kind of integrated circuit includes substrate and first group of function born of the same parents' unit (functional cell unit).The function born of the same parents unit is formed on the substrate.Each first group of function born of the same parents unit includes having not With a pair of of functional unit (functional cell) of threshold voltage and the fills unit between functional unit its described (filler cell).The number of the function born of the same parents unit in first group of function born of the same parents' unit is equal to or more than second group of work( Can born of the same parents' unit number, each second group of function born of the same parents unit includes with different threshold voltages and against each other (abut) A pair of of functional unit.
In some embodiments, the number of the function born of the same parents unit in first group of function born of the same parents' unit is to described The number of the function born of the same parents unit in first group of function born of the same parents' unit and the work(in second group of function born of the same parents' unit The ratio of the sum of the number of energy born of the same parents' unit is in the range of 0.5 to 1.
In some embodiments, a function born of the same parents in the function born of the same parents unit in first group of function born of the same parents' unit are single The fills unit of member has filling gate electrode (filler gate electrode).
In some embodiments, the filling gate electrode is to float (floating).
In some embodiments, the filling gate electrode is attached to power supply line (power supply line).
In some embodiments, a function born of the same parents in the function born of the same parents unit in first group of function born of the same parents' unit are single The fills unit of member does not have filling gate electrode.
In some embodiments, a function born of the same parents in the function born of the same parents unit in first group of function born of the same parents' unit are single Member further comprises another fills unit between its described functional unit.
In some embodiments, the integrated circuit further comprise active gate electrode, the first dummy gate electrode electrode with And the second dummy gate electrode electrode.The distance between the first dummy gate electrode electrode and described second dummy gate electrode electrode are to described The ratio of the pitch (pitch) of active gate electrode and the first dummy gate electrode electrode is about 2.
In some embodiments, the integrated circuit further comprise active gate electrode, the first dummy gate electrode electrode with And the second dummy gate electrode electrode.The distance between the first dummy gate electrode electrode and described second dummy gate electrode electrode are to described The ratio of the pitch of active gate electrode and the first dummy gate electrode electrode is about 1.
In further embodiments, a kind of method for manufacturing semiconductor element includes at least following steps.There is provided has the The substrate of one group of continuous active area, each first group of continuous active area have opposite first end part and the second end Part and the center section between the first end part and the second end part.It is continuous at described first group Fills unit is defined in the center section of each continuous active area in active area so that described first group continuously has The number of the continuous active area in source region is equal to or more than the number of second group of continuous active area, each second group of company Continuous active area includes first end part and the second end part against each other.To first group of continuous active area and described Each continuous active area in second group of continuous active area is doped so that its described first end part and described the Two end sections have different concentration of dopant.
In some embodiments, the method for the manufacture semiconductor element further comprises the steps.Described first In the first end part of the continuous active area of group and each continuous active area in second group of continuous active area Form the first functional unit.It is each described continuous in first group of continuous active area and second group of continuous active area The second functional unit is formed in the second end part of active area.
In some embodiments, defining the fills unit includes forming the fills unit with filling gate electrode.
In some embodiments, defining the fills unit includes forming the fills unit without filling gate electrode.
In some embodiments, defining the fills unit includes forming the fills unit and not with filling gate electrode Fills unit with filling gate electrode.
In some embodiments, define the fills unit can cause it is described continuous in first group of continuous active area The number of active area is to the number and described second of the continuous active area in first group of continuous active area The ratio of the sum of the number of the continuous active area in the continuous active area of group is in the range of 0.5 to 1.
In further embodiments, a kind of method for manufacturing semiconductor element includes at least following steps.There is provided has the The substrate of one group of continuous active area, each first group of continuous active area have opposite first end part and the second end Part and the center section between the first end part and the second end part.It is continuous at described first group Fills unit is defined in the center section of each continuous active area in active area so that described first group continuously has The number of the continuous active area in source region is equal to or more than the number of second group of continuous active area, each second group of company Continuous active area includes first end part and the second end part against each other.In first group of continuous active area and described The first functional unit is formed in the first end part of each continuous active area in second group of continuous active area. The second end of each continuous active area in first group of continuous active area and second group of continuous active area The second functional unit is formed in portion part, second functional unit has the work function (work with first functional unit Function) different work function.
In some embodiments, defining the fills unit includes being formed the filling list of the filling gate electrode including floating Member.
In some embodiments, defining the fills unit includes forming the filling grid including being attached to power supply line The fills unit of electrode.
In some embodiments, defining the fills unit includes forming the fills unit without filling gate electrode.
In some embodiments, the number of the continuous active area in first group of continuous active area is to described The number of the continuous active area in first group of continuous active area and the company in second group of continuous active area The ratio of the sum of the number of continuous active area is in the range of 0.5 to 1.
Foregoing has outlined the feature of several embodiments, so that one of skill in the art are better understood the present invention Various aspects.One of skill in the art are, it should be understood that it can easily use the present invention as design or change other works The basis of skill and structure come implement the purpose identical with embodiment described herein and/or realize with it is described herein The advantages of embodiment is identical.One of skill in the art will also be appreciated that these equivalent constructions without departing from the present invention's Spirit and scope, and they it can be variously modified under conditions of without departing substantially from spirit and scope of the present invention, instead of, And change.

Claims (1)

1. a kind of integrated circuit, which is characterized in that including：
Substrate；And
First group of function born of the same parents' unit, is formed on the substrate, and each first group of function born of the same parents unit includes having different thresholds A pair of of functional unit of threshold voltage and the fills unit between functional unit its described, wherein first group of function born of the same parents The number of the function born of the same parents unit in unit is equal to or more than the number of second group of function born of the same parents' unit, each second group of work( Energy born of the same parents unit includes a pair of of functional unit with different threshold voltages and against each other.
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CN108122901B (en) 2022-10-28

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