TW201631667A - Semiconductor device and fabrication method - Google Patents

Abstract

Some implementations provide a method for fabricating a semiconductor device and the method includes, providing a substrate; removing a part of the substrate to form one or more pairs of trench and a fin therebetween; further processing each fin by: forming a substantially flat top on the fin; and forming a top portion, a transition portion and a bottom portion of the fin, wherein the top portion having a first width and being substantially consistent over its length, and wherein the transition portion has a first taper for transitioning from the top portion to the bottom portion, the transition portion having the first width at a first interface to the top portion and a second larger width at a second interface to the bottom portion wherein the first taper being defined by a first angle that is between 10 and 85 degrees.

Description

Semiconductor component and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same.

Semiconductor components are widely used in electronic devices, and one of the semiconductor components is a field effect transistor (hereinafter referred to as FET). The FET is an electric field that controls the charge of a certain conductivity type in the semiconductor material. An element of the shape of the channel formed by the carrier. There are many types of FETs in the prior art, one of which is a fin field effect transistor (hereinafter referred to as FinFET). FinFET was first used to define a nonplanar double-gate fabricated on a silicon-on-insulator (SOI) substrate based on an early DELTA (single gate) transistor design. Transistor. A significant feature of the FinFET is that its channel region with conductive properties is wrapped in a thin layer of fins, and the fins serve as the substrate of the component, and the thickness of the fin (from source to drain) The direction measurement determines the effective channel length of this component. The gate structure of the wrapped fins provides better electrical control of the channel region and helps to reduce leakage current and overcome short-channel effects. In recent years, the definition of FinFET is not limited to the above, but is more widely used to describe Any multigate transistor component having a fin structure and without limiting the number of gates.

According to the patent application scope of the present invention, a method of fabricating a semiconductor device is provided. The fabrication method first provides a substrate and then removes a portion of the substrate to form one or more pairs of trenches and fins formed between the trenches. Next, each of the fins is further subjected to the following steps: forming an approximately flat top surface on the fin, and then forming a top portion, a transition portion and a bottom portion of the fin (bottom) Portion). The top portion has a first width and substantially maintains the first width from bottom to top. The engaging portion includes a first taper for engaging the top portion and the bottom portion. Between the connecting portion and the top portion, a first interface is included, and the first connecting surface includes the first width, and the second connecting surface is included between the connecting portion and the bottom portion, and the second connection The mask has a larger second width. In addition, the first slope is defined by a first angle, and the first angle is between 10° and 85°.

Embodiments provided by the present invention further include the following features. The top portion may approximately comprise a quadrilateral shape. The bottom portion has a second inclined surface defined by a second angle, and the second angle is greater than the first angle. The second angle can be from 70° to 88°. The height of the top may be 10 nanometers (hereinafter referred to as nm) to 40 nm. The height of the top portion and the one of the engaging portions may be 40 nm to 52 nm. One of the heights of the bottom is 110 nm to 140 nm. The first width of the top is 15 nm or less.

The manufacturing method provided by the embodiment of the present invention is further included in a trench erosion In the engraving step, a different etch chemistry is used to form a straight profile on the top portion and a tapered profile is formed on the bottom portion, and a filling material filling the trench is formed in the gap of the trench to perform a wet process. Etching to remove a portion of the filler until the bottom, and forming the interface using an isotropic etch. The steps of forming the top, the connecting portion and the bottom of the fin may include trench etching, trench filling, wet etching to remove part of the filler, dry etching to form the top, wet etching exposing the joint, and forming the joint. Directional etching.

According to the patent application of the present invention, there is further provided a semiconductor device comprising a FinFET formed on a substrate, the FinFET comprising at least one fin, the fin comprising a top portion, an engaging portion and a bottom portion. The top portion includes a first width and the first width is maintained from bottom to top. The engaging portion includes a first inclined surface that connects the top portion and the bottom portion. The connecting portion and the top portion have a first connecting surface, and the first connecting surface includes the first width, the connecting portion and the bottom portion have a second connecting surface, and the second connecting surface comprises a larger first Two widths. The first bevel is defined by a first angle and the first angle is between 10° and 85°.

According to an embodiment of the present invention, the top portion includes a quadrangular shape. The bottom portion includes a second inclined surface defined by a second angle, and the second angle is greater than the first angle. The second angle can be from 70° to 88°. The height of the top can be from 10 nm to 40 nm. The top portion and the interface portion comprise a height sum, and the height sum may be 40 nm to 52 nm. The first width of the top portion can be 15 nm or less. The height of the bottom can be from 110 nm to 140 nm. In addition, the FinFET provided by the embodiment of the present invention may include a top height between the top, the connecting portion and the bottom The height is between one third and one half of the fin.

100‧‧‧Semiconductor components

101‧‧‧ gate electrode layer

102‧‧‧ gate dielectric layer

104‧‧‧ top

106‧‧‧Connecting Department

108‧‧‧ bottom

110‧‧‧Insulated area

111‧‧‧Base

204‧‧‧hard mask layer

206‧‧‧Oxide groove area

H ₁ , H ₂ , H ₃ , S‧‧‧ height

θ ₁ , θ ₂ , θ ₃ ‧‧‧ angle

200A, 200B, 200C, 200D, 200E, 200F, 200G‧‧‧ steps

300A, 300B, 300C, 300D, 300E, 300F, 300G, 300H, 300I‧‧‧ steps

Figure 1 is a schematic diagram of a FinFET element comprising two fins, and the two fins comprise three distinct contour regions.

2A-2G is a schematic diagram of a preferred embodiment of a method of fabricating a FinFET shown in FIG. 1.

3A to 3I are schematic views showing another preferred embodiment of a method of fabricating one of the FinFETs shown in Fig. 1.

The preferred embodiment provides a method of fabricating a semiconductor device. The FinFET component referred to in the preferred embodiment refers to a multi-gate transistor or a fin-type multi-gate transistor. The FinFET device provided in the preferred embodiment may include a p-type metal oxide semiconductor FinFET device or an n-type MOS semiconductor FinFET device. The FinFET component provided by the preferred embodiment may include a dual-gate component, a tri-gate component, and/or other component structures. Importantly, the FinFET device provided by the preferred embodiment may include a gate and a plurality of fins, and each of the fins has three different contour regions, that is, a top under the gate, a bottom below the top, And an interface between the top and the bottom.

The top portion approximately comprises a quadrilateral shape comprising two side walls and a top surface. In embodiments of the invention, the sidewalls may be 40 nm or higher. In an embodiment of the invention The width of the top is not more than 15 nm due to the short channel effect. The fin substantially maintains the quadrilateral shape. The top is covered by a gate dielectric material so that when the gate is turned on, the on current will be formed along both sidewalls and top surface of the fin. In other embodiments of the invention, the top portion may comprise a corner-rounded quadrilateral shape by a cleaning or oxidation process. In other embodiments of the invention, the width of the top may have a 10% difference due to process tolerance.

In an embodiment of the invention, the bottom portion has a beveled profile that is constructed on a stack of substrates and is surrounded by an insulating material. In an embodiment of the invention, the bevel profile has an angle and the angle is 70° to 88°. The bottom portion can comprise a height and the height is between 110 nm and 140 nm. The bottom portion can comprise any desired shape and dopant so that the leakage current can be effectively reduced when the gate is not turned on.

The joint can serve as the neck between the top and the bottom. The engaging portion includes a slanted side wall for connecting the side wall of the top portion and a side wall of the bottom portion, and the slanting side wall includes an angle, which may be, for example, 10° to 85°. An embodiment of the FinFET provided by the present invention will be described in detail later as shown in FIG.

According to the manufacturing method of the semiconductor device provided by the preferred embodiment, a trench etching step is first performed on a substrate, and the trench etching step is formed on a substrate by using a hard mask layer as an etching mask. A plurality of columnar structures stacked from top to bottom. Next, a shallow trench isolation (hereinafter referred to as STI) void filling process is performed, and an insulating material is used to fill the space between the pillar structures. Subsequently, an STI chemical mechanical polishing is performed to Hereinafter referred to as CMP) process. After the STI CMP process, a trench fabrication process (e.g., a wet etch process and/or a dry etch process) is performed to etch the insulating material between the pillar structures and substantially etch to a predetermined level of the STI region. Next, a wet etching method and a silicon nitride (hereinafter referred to as SiN) removal method can be used to form an interface between the top and the bottom. The above method includes an isotropic etch to create a defect in the columnar structure and to form the junction. Next, a gate dielectric material containing a high dielectric constant (hereinafter referred to as high K) material is formed on the top surface, the surface of the insulating material between the columnar structures, and the sidewalls of the bonding portion. Finally, a metal gate is formed on the surface of the gate dielectric material. Subsequently, the method of fabricating the semiconductor device provided by the preferred embodiment will be described in detail as shown in Figs. 2A to 2G.

In another embodiment of the present invention, the wet etching and/or dry etching method for etching the insulating material between the columnar structures and substantially etching to a predetermined level of the STI region may be regarded as a first etching process. After the first etching process, an anisotropic etching process is further performed to create a stepped junction between the bottom and the top. Subsequently, a second etching process (including, for example, wet etching and/or dry etching) is performed to further etch the insulating material between the columnar structures to expose the stepped junction. Subsequently, a wet cleaning process and a SiN removal process can be utilized to form a beveled interface between the top and the bottom. It should be noted that the above removal process includes an isotropic etch to create a germanium loss to form the interface. Thereafter, a gate dielectric layer and a metal gate are formed as described above. Subsequently, the method of fabricating the semiconductor device provided by the preferred embodiment will be described in detail as shown in FIGS. 3A to 3I.

Figure 1 is a schematic view of one of the semiconductor components provided by the preferred embodiment. this The preferred embodiment provides a semiconductor component 100 that can be an element within an integrated circuit (IC), such as a microprocessor or a memory component. The semiconductor device 100 includes a FinFET type transistor disposed on a substrate 111. The FinFET type transistor may comprise a fin, and the fin comprises three different contour regions, namely a top portion 104, an interface portion 106, and a bottom portion 108.

The substrate 111 can be a crucible substrate. Alternatively, substrate 111 may comprise other elementary semiconductors such as germanium (germamiun). The substrate 111 may also comprise a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenic. ), and / or indium antimonide. The substrate 111 may also comprise an alloy semiconductor such as a germanium alloy semiconductor (SiGe), a gallium arsenide alloy semiconductor (GaAsP), an aluminum indium arsenide alloy semiconductor (AlInAs), an aluminum gallium arsenide alloy semiconductor (AlGaAs), gallium indium. An alloy semiconductor of arsenic alloy semiconductor (GaInAs), gallium indium phosphorus alloy semiconductor (GaInP), and/or gallium indium arsenide alloy semiconductor (GaInAsP). Substrate 111 may also comprise a combination of the above materials. In an embodiment of the invention, the substrate 111 can be a semiconductor on insulator (SOI) substrate.

The top portion 104 includes a source/drain region (not shown), and the source/drain region is where the source or drain of the field effect transistor element is formed, which may be formed within and above the top portion 104. Or around the top 104. The top portion 104 is covered by a gate structure including a gate dielectric layer 102 and a gate electrode layer 101.

The top portion 104 can include an active one that can form one or more transistor elements therein region. The top portion 104 can comprise germanium or other elemental semiconductors such as germanium. The top portion 104 may also comprise a composite semiconductor such as tantalum carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. The top portion 104 may also comprise an alloy semiconductor such as an alloy semiconductor of SiG, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. The top portion 104 can also comprise a combination of the above materials. The top can be formed by any suitable process, including lithography and etching processes, etc., as shown in Figures 2A through 3I. The lithography process may include forming a photoresist layer (barrier layer) on a substrate (for example, a semiconductor layer or an alloy layer), exposing the barrier layer by using a pattern, and performing an exposure-bake (post-exposure bake). a process, a barrier development step, etc., to form a mask structure comprising the barrier layer. The mask structure protects other areas on the substrate in an etching process used to form recesses in the germanium layer and obtain fins that protrude from the substrate. The recesses described above may be formed using reactive ion etch (RIE) methods and/or other suitable processes. In addition, there are other processes that can be used to form fins (including the top portion 104) on the substrate 111, which will not be described again.

In one embodiment of the invention, the top portion 104 has a width of less than about 15 nm and a height of between about 10 nm and 40 nm. However, those skilled in the art will recognize that in other embodiments, the size of the top portion 104 is not limited thereto. The height H1 of the top portion 104 is obtained by measuring the distance between the top surface of each of the top portions 104 and the beginning of the engaging portion 106. The height of the top portion 104 and the engaging portion 106 and H2 are obtained by measuring the distance between the top surface of the top portion 104 and a protruding portion for indicating the end point of the engaging portion 106/the starting point of the bottom portion 108. The top portion 104 can comprise an n-type or p-type dopant. In an embodiment of the invention, the top portion 104 is characterized in that it approximately comprises a quadrilateral shape. In one embodiment of the invention, it is known from its cross-sectional view that the top portion 104 includes two side walls and a top surface, and the height of the side walls may be 40 nm or higher. In an embodiment of the invention, the height of the top portion 104 can be approximately 25 nm. In an embodiment of the invention, the width of the top portion 104 is no greater than 15 nm due to short channel effect considerations to improve electrostatic control. In addition, the top portion 104 generally maintains a quadrangular shape from bottom to top. As shown, wherein the top line 104 of FIG. 1 comprises a first angle θ _2, an angle θ ₂ line by the bottom surface of the top of the sidewalls 104 and top 104, i.e. the horizontal plane, as it is defined, and the angle θ ₂ is approximately 90 °.

The top portion 104 is covered by the gate structure, and when the gate is open, the sidewalls of the top portion 104 form an on current with the top surface. It is worth noting that the current direction can be incident or exiting the paper of Figure 1. The gate structure can include a gate dielectric layer 102, a gate electrode layer 101, and/or other film layers. In an embodiment of the invention, the gate electrode comprises at least one metal layer.

According to an embodiment of the invention, the gate dielectric layer 102 of the gate structure may comprise silicon dioxide (hereinafter referred to as SiO ₂ ), and the cerium oxide may be oxidized and/or deposited by any suitable method. form. In an embodiment of the invention, the gate dielectric layer 102 may include an interfacial layer, such as a SiO ₂ layer formed on the top portion 104, and a high-k dielectric is formed on the dielectric layer. Layer (such as hafnium oxide (HfO ₂ )). Alternatively, the high-k dielectric layer may optionally comprise other high-k dielectric materials such as titanium dioxide (TiO ₂ ), hafnium zirconium oxide (HfZrO), tantalum trioxide (Ta ₂ O ₃ ), tantalum citrate ( HfSiO ₄ ), zirconium dioxide (ZrO ₂ ), zirconium silicate (ZrSiO ₂ ), combinations of the above materials, or other suitable materials. The high-k dielectric layer can be formed by atomic layer deposition (hereinafter abbreviated as ALD) and/or other suitable methods. The dielectric layer may comprise a dielectric material such as a SiO ₂ layer or a silicon oxynitride (SiON) layer. The dielectric layer can be formed by chemical oxidation, thermal oxidation, ALD, chemical vapor deposition (hereinafter referred to as CVD), and/or other suitable methods.

In other embodiments of the invention, the gate structure may include at least one metal layer to form the gate electrode layer 101. The gate electrode layer 101 may include a barrier layer, a work function layer, a fill metal layer, and/or other materials suitable for the metal gate structure. In other embodiments of the invention, the metal gate structure may further comprise a cap layer, an etch stop layer, and/or other suitable materials.

The gate structure may include a p-type work function metal, and the p-type work function metal may include, for example, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al). , tungsten nitride (WN), zirconium dichloride (ZrSi ₂ ), molybdenum disilicide (MoSi ₂ ), tantalum telluride (TaSi ₂ ), nickel dihydride (NiSi ₂ ), other suitable p-type work function materials, or A combination of the above materials. The gate structure may also include an n-type work function metal, and the n-type work function metal may include, for example, titanium (Ti), silver (Ag), tantalum aluminide (TaAl), tantalum aluminum carbide (TaAlC), aluminum nitride. TiAlN, TaC, TaCN, TaSiN, Mn, Zr . Since the work function value is related to the material combination of the work function layer, the work function value can be adjusted by the material selection of the work function layer, so that the semiconductor components in each region can reach the desired threshold voltage (Vt). . The work function layer can be formed by CVD, ALD, physical vapor deposition (PVD), and/or other suitable processes.

The fill metal layer may comprise a conductive metal such as aluminum (Al), tungsten (W) or copper (Cu), and/or other suitable materials. The fill metal layer can be formed by CVD, PVD, plating, and/or other suitable processes. Additionally, a fill metal layer can be formed on the work function metal layer.

The insulating region 110 (ie, the STI region 110) may be formed of tantalum oxide, tantalum nitride, hafnium oxynitride, and/or fluoride-doped glass (FSG). The insulating region 110 can be etched into the substrate 111 by a plurality of existing processes, and the trenches are filled by an insulating material, and then planarized by a planarization process such as CMP to planarize the surface of the insulating material. However, the preferred embodiment does not limit the formation of the insulating region 110 by other processing methods. Moreover, the insulating region 110 can comprise a multi-layer structure, for example, which can include one or more layers of a layer.

As shown in FIG. 1, the cross section of the bottom portion 108 has a beveled profile that is constructed on the crucible base 111 and is surrounded by the insulative region 110. Wherein the bottom 108 of a system comprising an angle θ _1, the angle θ ₁ based sidewall and a bottom portion 108 of the substrate 111, i.e. the horizontal plane, it is defined. In an embodiment of the invention, the angle θ _{1 is} approximately 70° to 88°. The bottom portion 108 can include a height S and a height S between 110 nm and 140 nm. In an embodiment of the invention, the height S may for example be 125 nm. The bottom portion 108 can comprise any desired shape and dopant so that the leakage current can be effectively reduced when the gate is not turned on.

The semiconductor device 100 may include other film layers or constituent elements such as a source/drain region, an interlayer dielectric (ILD), a contact plug, and an interconnect structure ( Interconnections) and / or other suitable components The components and the like are not described here.

In accordance with an embodiment of the present invention, the engagement portion 106 provides a beveled profile that engages the bottom portion 108 and the top portion 104, and the bevel profile is characterized by an angle θ ₃ that is the junction of the engagement portion 106 and the bottom portion 108. The side walls are defined with the horizontal plane. In an embodiment of the invention, the angle θ ₃ is between 10° and 85°. In an embodiment of the invention, the angle θ ₃ may be approximately 78°. In an embodiment of the present invention, the height of one of the engagement portion 104 with the top 106 lines and H ₂ is 40nm to 52nm. In an embodiment of the present invention, the height H ₂ and may be for example, about 44nm. In addition, the height of the top portion 104 is between the top portion 104, one-third and one-half the height of one of the joint portion 106 and the bottom portion 108. The connecting portion 106 and the top portion 104 have a first connecting surface, and the first connecting surface includes a first width, the connecting portion 106 and the bottom portion 108 have a second connecting surface, and the second connecting surface includes a first width greater than the first width The second width.

The above three parts, namely the top portion 104, the connecting portion 106 and the bottom portion 108, define the fin structure of the FinFET element provided by the preferred embodiment, and the FinFET element may comprise more than two fin structures. For example, the FinFET elements provided by the present invention can include three or more fin structures.

The FinFET type transistor element including the joint portion provided by the present invention has better performance. Compared with the FinFET type transistor element of the prior art in which the fin width is 14 nm and which does not have the connection portion, the foregoing structure, for example, has a width of 10 nm and a quadrangular shape, and the feature system including the connection portion 106 can be increased by 20 %~30% of driving current, and has a more average conduction current density (conducting current) Density).

The FinFET type transistor element provided by the present invention can also provide a better sub-threshold slope. In detail, the fin structure and depletion doping provided by the present invention can provide a steeper slope at a threshold level when the gate is turned on, and the steep slope can be lowered when the FinFET element is not turned on. Leakage current. Compared with the fin structure in the prior art which only has two parts at the top and the bottom, and the two parts have a beveled profile, the present invention provides three parts (ie, a top, a bottom with a quadrilateral shape, and The fin structure of the intervening portion can effectively mitigate the short channel effect on the subcritical slope. In summary, there are only two parts in the prior art, so that the three-part fin structure provided by the present invention is substantially the same as the fin structure having a relatively inclined bevel profile at the top and the bottom. It exhibits excellent electrostatic performance for the top of the quadrilateral shape. The semiconductor device provided by the invention further reduces the problems of subthreshold swing and drain induced barrier lowering (DIBL) due to the reduction of the short channel effect, and increases the output conductance ( Improved results such as output conductance). In addition, the above improvement results include an increase in on-state current and a more uniform conduction current density.

Please refer to FIG. 2A to FIG. 2G, which are schematic diagrams of a preferred embodiment of the method for fabricating the FinFET shown in FIG. 1. In accordance with the preferred embodiment, a top portion 104 having a quadrilateral profile and a bottom portion 108 having a beveled profile may be formed on a single wafer substrate 111. The top portion 104 can first be defined by a hard mask layer 204 formed by a combination of a pad oxide layer and SiN as shown in FIG. 2A. Moreover, in an embodiment of the invention, this step can be accomplished by STI trench etching. This step is defined as step 200A, and step 200A includes a deep trench reactive ion etch (DRIE) process, which can be performed using a variety of different etching chemistries, for example, DIRE. The process may utilize a fluorine-containing gas (fluorine-containing at least one of nitrogen trifluoride (NF ₃ ), sulfur hexafluoride (SF ₆ ), and carbon tetrafluoride (CF ₄ ). Containing gas), and/or containing at least one of carbon tetrafluoride (CF ₄ ), hexafluoroethane (C ₂ F ₆ ), and octafluorocyclobutane (C ₄ F ₈ ) a fluorocarbon-containing gas, and/or a hydrogen containing at least one of difluoromethane (CH ₂ F ₂ ), carbon tetrafluoride (CF ₄ ), and trifluoromethane (CHF ₃ ) Hydrofluorocarbon-containing gas, and/or halogen containing at least one of chlorine (Cl ₂ gas), tetrachlorosilane (SiCl ₄ ), hydrogen bromide (HBr) Gas (halogen-conta Ining gas), and/or at least sulfur dioxide (SO ₂ ), oxygen (oxygen O ₂ gas), nitrogen (nitrogen (N ₂ gas), hydrogen (hydrogen, H ₂ gas), and helium (helium, He gas) one of the other gases. As shown in FIG. 2A, the DRIE process forms at least one trench extending downward into the substrate 111 and having a depth L under the hard mask layer 204. In the preferred embodiment, the depth L is generally greater than 40 nm. For example, the depth L can be between 150 nm and 200 nm. In the structure provided by embodiments of the present invention, the top portion 140 includes a quadrilateral profile having a width of less than 15 nm. In the configuration provided by embodiments of the present invention, the etched bottom portion 108 can have a beveled surface such that the bottom portion 108 has a wider pedestal. In the structure provided by the above embodiment, the diagonal mask has an oblique angle, and the inclination angle is between 70 and 88.

Please refer to FIG. 2B, and FIG. 2B illustrates step 200B. Step 200B includes An STI void fill process for filling the trench region with an insulating material such as cerium oxide, and the cerium oxide can be formed by a suitable oxidation and/or deposition method. For example, the above process can include a CVD process. The CVD process may include a plasma-enhanced CVD (PECVD) process, a remote plasma-enhanced CVD (RPECVD) process, or an atomic layer chemical vapor deposition process. (atomic layer CVD, ALCVD) process, etc. In addition, the CVD process may be one of a low pressure CVD (LPCVD) process or an ultra vacuum CVD (UVCVD) process. In the embodiments provided by the present invention, the CVD process may also include a flow-through chemical vapor deposition (FCVD) process for utilizing in-situ steam generated (hereinafter referred to as ISSG). Oxide) forms an oxide material as described above with an ALD oxide.

Please refer to FIG. 2C, and FIG. 2C shows step 200C. Step 200C includes an STI CMP process for planarizing the filled trench surface such that the oxide used to fill the trench is aligned with the top surface of the hard mask layer 204. The CMP process is a composite process of chemical etching and free abrasive grinding that can be used to form a flat and smooth surface. In an embodiment provided by the present invention, the STI CMP process can be performed after a first steam anneal process, and after the STI CMP process, a second vapor anneal process and an etch back can be performed (etch back) The process is to remove oxides on top of the hard mask layer 204.

Please refer to FIG. 2D, and FIG. 2D shows step 200D. Step 200D includes a wet etching process and/or a dry etching process to form an oxide recess region 206. And the surface of the oxide filling the trench is lower than the top 104. In the preferred embodiment, the wet etch may be an isotropic etch and may include an immersion process to form the oxide recess region 206. In this step, an etching process having a high etching selectivity can be used.

Next, please refer to FIG. 2E, and FIG. 2E shows step 200E. Step 200E includes forming an interface 106 in the neck portion between the top portion 104 and the bottom portion 108. For example, the exposed top sidewalls 104 and bottom 106 can be etched using a wet cleaning process and a SiN removal process. The etch step can include an isotropic etch process to create a bond 106 in the resulting sidewall loss of the exposed top portion 104 and the exposed bottom portion. The purpose of this step also includes removing the hard mask (SiN), and the etchant (usually hot phosphoric acid (H ₃ PO ₄ )) used to remove the hard mask can also be used to remove the exposed germanium material, thus The joint 106 can be formed.

Subsequently, a gate dielectric material is formed on the sidewalls of the top portion 104 and the sidewalls of the connector portion 106 that is formed. The gate dielectric material can be deposited by a CVD process or formed by an oxidation process. In addition, the gate dielectric material also covers the insulating region 110 as shown in FIG. 2F. The deposition process may include a chemical oxidation process, a thermal oxidation process, an ALD process, a CVD process, and/or other suitable processes. This gate dielectric material acts as the gate dielectric layer 102.

Finally, as shown in FIG. 2G, a gate forming process is performed, and the gate electrode layer 101 covers the gate dielectric layer 102 formed. The gate electrode layer 101 may include one or more layers of a work function layer and a conductive metal material such as Al, W, or Cu. Gate electric The pole layer 101 can be formed by CVD, PVD, electroplating, and/or other suitable processes.

Please refer to FIG. 3A to FIG. 3I , which are schematic diagrams of another preferred embodiment of the method for fabricating the FinFET shown in FIG. 1 . As shown in FIG. 3A, the top portion 104 and the bottom portion 108 having a beveled profile provided by the preferred embodiment may be formed on a single wafer substrate 111. The top portion 104 can first be defined by a hard mask layer 204 as shown in FIG. 2A. As shown in the foregoing embodiment and FIG. 2A, the preferred embodiment benefits may be formed by a STI trench etching process such as DRIE under the hard mask layer 204 to form a trench extending downward into the substrate 111 and having a depth L. In the preferred embodiment, the depth L is substantially greater than 40 nm. For example, the depth L can be between 150 nm and 200 nm. In accordance with an embodiment of the present invention, the top portion 104 also has a beveled profile and a width of no greater than 15 nm. In accordance with an embodiment of the present invention, the etched bottom portion 108 can comprise the same bevel profile with a larger base width. According to an embodiment of the invention, the bevel comprises an angle of inclination and the angle is between 70 and 88.

A mask layer 204 can be formed on the substrate 111. Please refer to FIG. 3B, and FIG. 3B illustrates step 300B. Step 300B includes an STI void fill process for filling the trench region with an insulating material such as cerium oxide, and the cerium oxide can be formed using a suitable oxidation and/or deposition method. For example, the above process can include a CVD process. In accordance with an embodiment of the present invention, a CVD process can include a flow CVD process for forming the oxide material described above using ISSG oxide and ALD oxide.

Please refer to FIG. 3C, and FIG. 3C illustrates step 300C. Step 300C includes an STI CMP process for planarizing the surface of the filled trench to fill the trench The oxide is aligned with the top surface of the hard mask layer 204. This step is the same as the step 200C described in the foregoing embodiment, and is the same as that shown in FIG. 2C, and thus will not be described again.

Please refer to FIG. 3D, and FIG. 3D illustrates step 300D. Step 300D includes a wet etch process to form an oxide recess region 206 such that the surface of the oxide filling the trench is lower than the top portion 104. This step is the same as the step 200D described in the foregoing embodiment, and is the same as that shown in FIG. 2D, and thus will not be described again.

Next, please refer to FIG. 3E, and FIG. 3E shows step 300E. Step 300E includes forming a stepped engagement portion 106 between the top portion 104 and the bottom portion 108. For example, the contour of the top portion 104 can be modified using an anisotropic etch process. This etch step can include an orientation-dependent anisotropic etch process to create enthalpy losses on the sidewalls of the exposed top portion 104. Thereafter, a step 300F as shown in FIG. 3F is performed, and a portion of the yttrium oxide 110 is removed by a wet etching to form a niobium oxide groove region. Next, step 300G is performed to etch the exposed top portion 104 by using another wet cleaning process and a SiN removal process while etching the sidewalls of the stepped junction to form the junction portion 106 as shown in FIG. 3G.

Subsequently, a gate dielectric material is formed on the sidewalls of the top portion 104 and the sidewalls of the connector 106 formed, and the gate dielectric material also covers the insulating recess region 206, as shown in FIG. 3H. This step is the same as the step 200F described in the foregoing embodiment, and therefore will not be described again.

Finally, as shown in FIG. 3I, a gate forming process is performed, and the gate is The electrode layer 101 covers the gate dielectric layer 102 formed. The gate electrode layer 101 may include one or more layers of a work function layer and a conductive metal material such as Al, W, or Cu. This step is the same as the step 200F described in the foregoing embodiment, and is the same as that shown in FIG. 2F, and thus will not be described again.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Semiconductor components

101‧‧‧ gate electrode layer

102‧‧‧ gate dielectric layer

104‧‧‧ top

106‧‧‧Connecting Department

108‧‧‧ bottom

110‧‧‧Insulated area

111‧‧‧Base

H ₁ , H ₂ , S‧‧‧ height

θ ₁ , θ ₂ , θ ₃ ‧‧‧ angle

Claims (20)

A method of fabricating a semiconductor device, comprising: providing a substrate; removing a portion of the substrate to form one or more pairs of trenches and a fin formed between the trenches; and performing the fins further: Forming a flat top surface on the fin; and forming a top portion, a transition portion, and a bottom portion of the fin, wherein the top portion includes a first width, and Maintaining the first width from bottom to top, the engaging portion includes a first inclined surface for engaging the top portion and the bottom portion, the engaging portion and the top portion have a first connecting surface, and the first connecting surface includes the first connecting surface Width, the connecting portion and the bottom portion have a second connecting surface, and the second connecting surface includes a larger second width, the first oblique angle is defined by a first angle, and the first angle is introduced Between 10° and 85°. The manufacturing method of claim 1, wherein the top portion comprises a quadrilateral shape. The manufacturing method of claim 1, wherein the bottom portion comprises a second inclined surface defined by a second angle, and the second angle is greater than the first angle. The manufacturing method of claim 3, wherein the second angle is 70° to 88°. The manufacturing method of claim 1, wherein the top portion comprises a height, and the height is 10 nanometers (nm) to 40 nm. The manufacturing method of claim 1, wherein the top portion and the engaging portion comprise a height sum, and the height sum is 40 nm to 52 nm. The manufacturing method of claim 1, wherein the bottom portion comprises a height, and the height is 110 nm to 140 nm. The manufacturing method of claim 1, wherein the first width of the top portion is 15 nm or less. The manufacturing method of claim 1, further comprising forming a straight profile at the top and forming a tapered profile at the bottom by using different etching chemistry in a trench etching step. A material filling the gap between the trenches, a wet etching to remove a portion of the material up to the bottom, and forming the interface by an isotropic etching process. The manufacturing method of claim 1, wherein the step of forming the top portion of the fin, the connecting portion and the bottom portion further comprises etching each of the trenches to form a material filling a gap between the trenches. A wet etching is performed to remove a portion of the material, a dry etching is performed to form the top portion, a wet etch is performed to expose the bonding portion, and the bonding portion is formed by an isotropic etching method. The manufacturing method of claim 1, wherein the height of the top portion is between the top portion, a third and one-half of a height of one of the joint portion and the bottom portion. A semiconductor device comprising: a fin field effect transistor (FinFET) disposed on a substrate, the FinFET comprising at least one fin, wherein the fin comprises a top portion, an engaging portion and a bottom portion, wherein the top portion Having a first width and maintaining the first width from bottom to top, the engaging portion includes a first inclined surface that connects the top portion and the bottom portion, the connecting portion and the top portion have a first connecting surface, and the first The junction includes the first width, the interface has a second junction with the bottom, and the second junction includes a larger second width, the first slope is defined by a first angle, and the The first angle is between 10° and 85°. The semiconductor component of claim 12, wherein the top portion comprises a quadrilateral shape. The semiconductor component of claim 12, wherein the bottom portion comprises a second slope, the second slope is defined by a second angle, and the second angle is greater than the first angle. The semiconductor component of claim 14, wherein the second angle is 70° to 88°. The semiconductor device of claim 12, wherein the top portion comprises a height and the height is from 10 nm to 40 nm. The semiconductor device of claim 12, wherein the top portion and the interface portion comprise a height sum, and the height sum is 40 nm to 52 nm. The semiconductor device of claim 17, wherein the first width of the top portion is 15 nm or less. The semiconductor device of claim 12, wherein the bottom portion comprises a height and the height is 110 nm to 140 nm. The semiconductor component of claim 12, wherein the height of the top portion is between the top portion, the interface portion and a height of one third and one half of the bottom portion.