CN108110016B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN108110016B CN108110016B CN201611059571.8A CN201611059571A CN108110016B CN 108110016 B CN108110016 B CN 108110016B CN 201611059571 A CN201611059571 A CN 201611059571A CN 108110016 B CN108110016 B CN 108110016B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 247
- 239000000463 material Substances 0.000 claims abstract description 104
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- 239000002184 metal Substances 0.000 claims abstract description 81
- 238000000034 method Methods 0.000 claims abstract description 50
- 125000006850 spacer group Chemical group 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 238000000059 patterning Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 5
- 239000000470 constituent Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229920001665 Poly-4-vinylphenol Polymers 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910000086 alane Inorganic materials 0.000 description 2
- 125000000217 alkyl group Chemical group 0.000 description 2
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical compound [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- TUTOKIOKAWTABR-UHFFFAOYSA-N dimethylalumane Chemical compound C[AlH]C TUTOKIOKAWTABR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000004678 hydrides Chemical class 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- BSKHPKMHTQYZBB-UHFFFAOYSA-N 2-methylpyridine Chemical compound CC1=CC=CC=N1 BSKHPKMHTQYZBB-UHFFFAOYSA-N 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- -1 Siloxanes Chemical class 0.000 description 1
- 125000005376 alkyl siloxane group Chemical group 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- DAZXVJBJRMWXJP-UHFFFAOYSA-N n,n-dimethylethylamine Chemical compound CCN(C)C DAZXVJBJRMWXJP-UHFFFAOYSA-N 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein the method comprises the steps of providing a substrate, and sequentially forming an interlayer dielectric layer and a semiconductor material layer on the substrate from bottom to top; patterning the semiconductor material layer to form an opening in the semiconductor material layer exposing the interlayer dielectric layer; forming a spacer structure at the bottom of the side wall of the opening; forming a dielectric layer on the substrate to cover the surface of the semiconductor material layer, the bottom and the side wall of the opening and the gap wall structure; and forming a metal layer on the surface of the dielectric layer, and patterning the metal layer to form a first metal pattern at the bottom of the opening and a second metal pattern on the semiconductor material layer. According to the manufacturing method of the semiconductor device, the gap wall structure located at the bottom of the side wall of the opening is formed, so that metal residue is effectively avoided, and the stable performance of the semiconductor device is ensured.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
The metal line film forming process has a critical influence on the characteristics of a complementary metal oxide semiconductor Image Sensor (CIS), especially on the conductive resistance of the device. Due to the trend of semiconductor process integration, the performance of semiconductor chips is more and more abundant, and along with the circuit concentration caused by the integration degree of semiconductor wafers, the heat productivity of devices is increased, and the performance and the service life of the devices are finally influenced.
The conventional CIS manufacturing process generally includes completing a manufacturing process on a front surface of a semiconductor substrate (typically, a silicon substrate), for example, forming an interlayer dielectric layer and a metal interconnection structure on the front surface of the silicon substrate; then, bonding a supporting substrate on the front surface of the silicon substrate, and then carrying out a back surface process of the silicon substrate; in the back process of the silicon substrate, an opening penetrating through the silicon substrate is usually formed to expose the interlayer dielectric layer, then a metal layer (usually an aluminum layer) is deposited on the back of the silicon substrate, and then the metal layer is etched and patterned to form a required metal pattern, such as an interconnection line, a pad, and the like.
Metal residue is one of the difficulties in the subsequent CIS process, and incomplete removal of metal residue has a significant effect on resistivity, leakage current and yield. However, the overetching metal residue will cause the loss of the bottom oxide of the semiconductor and the damage of the silicon nitride, which will affect the stability of the semiconductor.
Therefore, it is necessary to provide a method for manufacturing a semiconductor device, which can effectively avoid metal residue and ensure stable performance of the semiconductor device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, and sequentially forming an interlayer dielectric layer and a semiconductor material layer on the substrate from bottom to top;
patterning the semiconductor material layer to form an opening in the semiconductor material layer exposing the interlayer dielectric layer;
forming a spacer structure at the bottom of the side wall of the opening;
forming a dielectric layer on the substrate to cover the surface of the semiconductor material layer, the bottom and the side wall of the opening and the gap wall structure;
and forming a metal layer on the surface of the dielectric layer, and patterning the metal layer to form a first metal pattern at the bottom of the opening and a second metal pattern on the semiconductor material layer.
Further, the step of forming the opening includes: and forming a hard mask layer and a patterned photoresist layer on the semiconductor material layer, etching the hard mask layer and the semiconductor material layer by taking the patterned photoresist layer as a mask to form the opening, and then removing the photoresist layer.
Further, the hard mask layer includes an oxide layer and a nitride layer formed in sequence.
Further, the step of forming the spacer structure includes: forming a spacer material layer on the substrate to cover the surface of the semiconductor material layer, the bottom of the opening and the side wall, and performing a full-scale etching step to remove the spacer material layer on the surface of the semiconductor material layer, the bottom of the opening and the upper part of the side wall of the opening, so as to form the spacer structure at the bottom of the side wall of the opening.
Further, the material of the spacer structure includes an oxide.
Further, the dielectric layer includes an oxide.
Further, the metal layer includes aluminum.
Further, the dielectric layer and the spacer structure are made of the same material.
Further, the semiconductor material layer includes a silicon material layer.
In addition, the present invention also provides a semiconductor device including:
the semiconductor device comprises a substrate, wherein an interlayer dielectric layer and a semiconductor material layer are sequentially formed on the substrate from bottom to top, and an opening for exposing the interlayer dielectric layer is formed in the semiconductor material layer;
the spacer structure is positioned at the bottom of the side wall of the opening;
the dielectric layer covers the surface of the semiconductor material layer, the bottom and the side wall of the opening and the gap wall structure;
a first metal pattern at the bottom of the opening and a second metal pattern on the semiconductor material layer.
Further, the dielectric layer and the spacer structure are made of the same material.
Further, the material of the spacer structure includes an oxide.
According to the manufacturing method of the semiconductor device, in the process of forming the metal wire film, the inclined angle of the bottom part of the side wall of the opening is changed by forming the gap wall structure positioned at the bottom of the side wall of the opening, and metal residue is avoided in the process of forming and patterning the metal layer. The method can effectively avoid metal residue and ensure the stable performance of the semiconductor device.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.
In the drawings:
fig. 1 is a schematic flow chart of a method of fabricating a semiconductor device according to a first exemplary embodiment of the present invention.
Fig. 2A-2G are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor device with metal residue fabricated according to the prior art.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
The metal line film forming process has a critical influence on the characteristics of the CIS, particularly the conductive resistance of the device. Due to the trend of semiconductor process integration, the performance of semiconductor chips is more and more abundant, and along with the circuit concentration caused by the integration degree of semiconductor wafers, the heat productivity of devices is increased, and the performance and the service life of the devices are finally influenced.
A conventional CIS manufacturing process, as shown in fig. 3, generally includes first completing a manufacturing process on a front surface of a semiconductor substrate 302 (typically, a silicon substrate), for example, forming an interlayer dielectric layer 301 and a metal interconnection structure (not shown) on the front surface of the silicon substrate 302; then, bonding a supporting substrate 300 on the front surface of the silicon substrate, and then performing a back surface process of the silicon substrate; in the back process of the silicon substrate, an opening penetrating through the silicon substrate is usually formed to expose the interlayer dielectric layer 301, then a hard mask layer 303 (including an oxide layer 303a and a nitride layer 303b which are formed in sequence), a dielectric layer 306 and a metal layer 307 (usually an aluminum layer) are deposited on the back surface of the silicon substrate 302, and then the metal layer 307 is etched and patterned to form a required metal pattern, such as an interconnection line 307b, a pad 307a and the like.
Metal residue is one of the difficulties in the subsequent CIS process, and incomplete removal of metal residue has a significant effect on resistivity, leakage current and yield. However, the overetching metal residue may cause the loss of the bottom oxide of the semiconductor and the damage of SiN, which affects the stability of the semiconductor.
Therefore, it is necessary to provide a method for manufacturing a semiconductor device, which can effectively avoid metal residue and ensure stable performance of the semiconductor device.
Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, and sequentially forming an interlayer dielectric layer and a semiconductor material layer on the substrate from bottom to top;
patterning the semiconductor material layer to form an opening in the semiconductor material layer exposing the interlayer dielectric layer;
forming a spacer structure at the bottom of the side wall of the opening;
forming a dielectric layer on the substrate to cover the surface of the semiconductor material layer, the bottom and the side wall of the opening and the gap wall structure;
and forming a metal layer on the surface of the dielectric layer, and patterning the metal layer to form a first metal pattern at the bottom of the opening and a second metal pattern on the semiconductor material layer.
Wherein the step of forming the opening comprises: forming a hard mask layer and a patterned photoresist layer on the semiconductor material layer, etching the hard mask layer and the semiconductor material layer by taking the patterned photoresist layer as a mask to form the opening, and then removing the photoresist layer, wherein the hard mask layer comprises an oxide layer and a nitride layer which are sequentially formed; the step of forming the spacer structure comprises: forming a spacer material layer on the substrate to cover the surface of the semiconductor material layer, the bottom of the opening and the side wall, and performing a full-scale etching step to remove the spacer material layer on the surface of the semiconductor material layer, the bottom of the opening and the upper part of the side wall of the opening, so as to form the spacer structure at the bottom of the side wall of the opening, wherein the material of the spacer structure comprises oxide; the dielectric layer comprises oxide and is made of the same material as the clearance wall structure; the metal layer comprises aluminum; the semiconductor material layer includes a silicon material layer.
According to the manufacturing method of the semiconductor device, in the process of forming the metal wire film, the inclined angle of the bottom part of the side wall of the opening is changed by forming the gap wall structure positioned at the bottom of the side wall of the opening, and metal residue is avoided in the process of forming and patterning the metal layer. The method can effectively avoid metal residue and ensure the stable performance of the semiconductor device.
[ example one ]
Reference is now made to fig. 1, 2A-2G, wherein fig. 1 illustrates a schematic flow chart diagram of a method of fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention. Fig. 2A-2G are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention.
The invention provides a preparation method of a semiconductor device, as shown in figure 1, the main steps of the preparation method comprise:
step S101: providing a substrate, and sequentially forming an interlayer dielectric layer and a semiconductor material layer on the substrate from bottom to top;
step S102: patterning the semiconductor material layer to form an opening in the semiconductor material layer exposing the interlayer dielectric layer;
step S103: forming a spacer structure at the bottom of the side wall of the opening;
step S104: forming a dielectric layer on the substrate to cover the surface of the semiconductor material layer, the bottom and the side wall of the opening and the gap wall structure;
step S105: and forming a metal layer on the surface of the dielectric layer, and patterning the metal layer to form a first metal pattern at the bottom of the opening and a second metal pattern on the semiconductor material layer.
Next, a detailed description will be given of a specific embodiment of a method for manufacturing a semiconductor device of the present invention.
Firstly, step S101 is executed, as shown in fig. 2A, a substrate 200 is provided, and an interlayer dielectric layer 201 and a semiconductor material layer 202 are sequentially formed on the substrate 200 from bottom to top;
specifically, as shown in fig. 2A, the substrate 200 includes a manufacturing process of a front surface of a semiconductor material layer 202, such as an interlayer dielectric layer 201 and a metal interconnection structure formed on the front surface of the semiconductor material layer 202. A support substrate is bonded to the front surface of the base 200, and then a back surface process of the semiconductor material layer 202 is performed. The interlayer dielectric layer 201 may be formed using an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, an insulating layer containing polyvinyl phenol, polyimide, siloxane, or the like; the semiconductor material layer 202 includes a silicon material layer, which may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
Next, step 102 is performed, as shown in fig. 2B, to pattern the semiconductor material layer 202 so as to form an opening in the semiconductor material layer, which exposes the interlayer dielectric layer 201. The step of forming the opening includes: forming a hard mask layer 203 and a patterned photoresist layer 204 on the semiconductor material layer 202, etching the hard mask layer 203 and the semiconductor material layer 202 by using the patterned photoresist layer 204 as a mask to form the opening, and then removing the photoresist layer 204, wherein the hard mask layer 203 comprises an oxide layer 203a and a nitride layer 203b which are formed in sequence.
Specifically, as shown in fig. 2B, a hard mask layer 203 and a patterned photoresist layer 204 are formed on the semiconductor material layer 202, and the hard mask layer 203 includes an oxide layer 203a and a nitride layer 203B which are sequentially formed. And etching the hard mask layer 203 and the semiconductor material layer 202 by using the patterned photoresist layer 204 as a mask to form an opening exposing the interlayer dielectric layer 201.
The hard mask layer 203 and the semiconductor material layer 202 can be etched by a dry etching method or a wet etching method. Illustratively, the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used. The source gas for the dry etch may comprise HBr and/or CF4A gas.
Next, step 103 is executed, as shown in fig. 2C and 2D, a spacer structure 2050 is formed at the bottom of the sidewall of the opening; the step of forming the spacer structure 2050 includes: a spacer material layer 205 is formed on the semiconductor material layer 202 to cover the surface of the semiconductor material layer 202, the bottom and the sidewalls of the opening, and a full etching step is performed to remove the spacer material layer 205 on the surface of the semiconductor material layer 202, the bottom of the opening and the upper portion of the sidewalls of the opening, so as to form the spacer structure 2050 at the bottom of the sidewalls of the opening.
Specifically, as shown in fig. 2C, a spacer material layer 205 is formed to cover the surface of the semiconductor material layer 202, the bottom and the sidewalls of the opening. The spacer material layer 205 may be formed using an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, an insulating layer containing polyvinyl phenol, polyimide, siloxane, or the like. Further, polyvinyl phenol, polyimide, or siloxane can be effectively formed by a droplet discharge method, printing, or spin coating method. Siloxanes can be classified according to their structure into silica glass, alkyl siloxane polymers, alkyl silsesquioxane polymers, silsesquioxane hydride polymers, alkyl silsesquioxane hydride polymers, and the like. The spacer material layer 205 may be formed by any conventional method known to those skilled in the art, including Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD).
Next, as shown in fig. 2D, a full etching step is performed to remove the spacer material layer 205 on the surface of the semiconductor material layer 202, the bottom of the opening and the upper portion of the sidewall of the opening, so as to form the spacer structure 2050 at the bottom of the sidewall of the opening. The etching step is stopped on the surface of the hard mask layer 203b, and the etching causes the spacer material to remain at the bottom of the sidewall of the opening, forming the spacer structure 2050. The spacer structure 2050 changes the angle of inclination of the bottom portion of the opening sidewall.
The spacer material layer 205 may be removed by etching by any method known to those skilled in the art, including dry etching or wet etching, preferably dry etching.
Next, step 104 is performed, as shown in fig. 2E, a dielectric layer 206 is formed on the substrate 200 to cover the surface of the semiconductor material layer 202, the bottom and the sidewalls of the opening, and the spacer structure 2050;
specifically, as shown in fig. 2E, the dielectric layer 206 may be formed by any conventional method known to those skilled in the art, including Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD), preferably Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Plasma Enhanced Chemical Vapor Deposition (PECVD). In one example, the dielectric layer is made of the same material as the spacer structure.
Next, step 105 is performed, as shown in fig. 2F and 2G, a metal layer 207 is formed on the surface of the dielectric layer 206, and the metal layer 207 is patterned to form a first metal pattern 207a at the bottom of the opening and a second metal pattern 207b on the semiconductor material layer.
Specifically, as shown in fig. 2F, a metal layer 207 is formed on the surface of the dielectric layer 206, and the metal layer 207 may be formed by any conventional method known to those skilled in the art, including Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD). Illustratively, the metal layer 207 is a metal aluminum layer formed by a chemical vapor deposition process. The forming method comprises the following steps: the source gas for forming the metallic aluminum film may include compounds such as dimethylethylamine alane (DEMMA), picoline alane (MPA), dimethylaluminum hydride (DMAH), and the like. The source gas may comprise one of these, or may comprise a mixture of more than two or more compounds. The flow rate of the source gas is about 1-10 sccm, the temperature is 120-160 ℃, the pressure is 0.2-0.5 torr, and the time is 20-180 s. A metal layer having good step coverage can be formed by the above method.
Next, as shown in fig. 2G, the metal layer 207 is patterned to form a first metal pattern 207a located at the bottom of the opening and a second metal pattern 207b located on the semiconductor material layer. The metal layer 207 may be patterned by developing, exposing, and etching processes using a photosensitive property of a photoresist. The etching method may be any of the existing techniques known to those skilled in the art, including dry etching or wet etching, preferably dry etching. As an example, Cl may be selected in the present invention2/BCl3，Ar，N2，CHF3The etching pressure may be 5to 300mTorr, preferably 8 to 10mTorr, as the etching gas. Illustratively, the first metal pattern includes a metal pad structure and the second metal pattern includes an interconnect line structure.
[ example two ]
The structure of the semiconductor device provided by the embodiment of the present invention is described below with reference to fig. 2G and 2D. The semiconductor device includes a substrate 200, a spacer structure 2050, a dielectric layer 206, a first metal pattern 207a, and a second metal pattern 207 b. Wherein:
an interlayer dielectric layer 201 and a semiconductor material layer 202 are sequentially formed on the substrate 200 from bottom to top, and an opening exposing the interlayer dielectric layer 201 is formed in the semiconductor material layer 202. Illustratively, the substrate 200 includes a manufacturing process of a front surface of the semiconductor material layer 202, such as an interlayer dielectric layer 201 and a metal interconnection structure formed on the front surface of the semiconductor material layer 202. The interlayer dielectric layer 201 may be formed using an insulating layer; the semiconductor material layer 202 includes a silicon material layer, which may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
A dielectric layer 206 covers the surface of the semiconductor material layer 202, the bottom and sidewalls of the opening, and the spacer structure 2050. Illustratively, the dielectric layer 206 is the same material as the spacer structure 2050.
A first metal pattern 207a is located at the bottom of the opening and a second metal pattern 207b is located on the semiconductor material layer.
According to the manufacturing method of the semiconductor device, in the process of forming the metal wire film, the inclined angle of the bottom part of the side wall of the opening is changed by forming the gap wall structure positioned at the bottom of the side wall of the opening, and metal residue is avoided in the process of forming and patterning the metal layer. The method can effectively avoid metal residue and ensure the stable performance of the semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (12)
1. A method for manufacturing a semiconductor device is characterized by comprising the following steps:
providing a substrate, and sequentially forming an interlayer dielectric layer and a semiconductor material layer on the substrate from bottom to top;
patterning the semiconductor material layer to form an opening in the semiconductor material layer exposing the interlayer dielectric layer;
forming a spacer structure at the bottom of the opening sidewall to change an inclination angle of a bottom portion of the opening sidewall;
forming a dielectric layer on the substrate to cover the surface of the semiconductor material layer, the bottom and the side wall of the opening and the gap wall structure;
and forming a metal layer on the surface of the dielectric layer, and patterning the metal layer to form a first metal pattern at the bottom of the opening and a second metal pattern on the semiconductor material layer.
2. The method of claim 1, wherein the step of forming the opening comprises: and forming a hard mask layer and a patterned photoresist layer on the semiconductor material layer, etching the hard mask layer and the semiconductor material layer by taking the patterned photoresist layer as a mask to form the opening, and then removing the photoresist layer.
3. The method of claim 2, wherein the hard mask layer comprises an oxide layer and a nitride layer formed sequentially.
4. The method of claim 1, wherein the step of forming the spacer structure comprises: forming a spacer material layer on the substrate to cover the surface of the semiconductor material layer, the bottom of the opening and the side wall, and performing a full-scale etching step to remove the spacer material layer on the surface of the semiconductor material layer, the bottom of the opening and the upper part of the side wall of the opening, so as to form the spacer structure at the bottom of the side wall of the opening.
5. The method of claim 1, wherein the material of the spacer structure comprises an oxide.
6. The method of claim 1, wherein the dielectric layer comprises an oxide.
7. The method of claim 1, wherein the metal layer comprises aluminum.
8. The method of claim 1, wherein the dielectric layer is the same material as the spacer structure.
9. The method of claim 1, wherein the layer of semiconductor material comprises a layer of silicon material.
10. A semiconductor device, comprising:
the semiconductor device comprises a substrate, wherein an interlayer dielectric layer and a semiconductor material layer are sequentially formed on the substrate from bottom to top, and an opening for exposing the interlayer dielectric layer is formed in the semiconductor material layer;
a spacer structure at a bottom of the opening sidewall to change an inclination angle of a bottom portion of the opening sidewall;
the dielectric layer covers the surface of the semiconductor material layer, the bottom and the side wall of the opening and the gap wall structure;
a first metal pattern at the bottom of the opening and a second metal pattern on the semiconductor material layer.
11. The semiconductor device according to claim 10, wherein the dielectric layer is the same as a constituent material of the spacer structure.
12. The semiconductor device of claim 10, in which a material of the spacer structure comprises an oxide.
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